TE0715 TRM

Overview

The Trenz Electronic TE0715 is an industrial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC (XC7Z015 or XC7Z030) with 1GB of DDR3 SDRAM, 32MB of SPI flash memory, gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.

Block diagram

Main components

   1. Zynq-7000 all programmable SoC.

   2. System controller CPLD.

   3. Programmable clock generator.

   4. 10/100/1000 Mbps Ethernet PHY.

   5. DDR3-SDRAM.

   6. Hi-Speed USB 2.0 ULPI transceiver.

   7a. B2B connector JM1.

   7b. B2B connector JM2.

   7c. B2B connector JM3.

   8. 256 Mbit (32 Mbyte) 3.0V SPI flash memory.

   9. Low power RTC with battery backed SRAM.

   10. PowerSoC DC-DC converter.

Key features

• Industrial-grade Xilinx Zynq-7000 (XC7Z015, XC7Z030) SoM

• Rugged for shock and high vibration
• 2 × ARM Cortex-A9
• 10/100/1000 tri-speed gigabit Ethernet transceiver PHY
• MAC address EEPROM
• 32-Bit wide 1GB DDR3 SDRAM
• 32 MByte QSPI flash memory
• Programmable clock generator
  • Transceiver clock (default 125 MHz)
• Plug-on module with 2 × 100-pin and 1 × 60-pin high-speed hermaphroditic strips
• 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
• 4 GTP/GTX (high-performance transceiver) lanes
  • GTP/GTX (high-performance transceiver) clock input
• USB 2.0 high-speed ULPI transceiver
• On-board high-efficiency DC-DC converters
  • 4.0 A x 1.0 V power rail
  • 1.5 A x 1.5 V power rail
  • 1.5 A x 1.8 V power rail
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Temperature compensated RTC (real-time clock)
• User LED
• Evenly-spread supply pins for good signal integrity

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

Interfaces and Pins

Board to Board (B2B) I/O's

I/O signals connected to the SoC's I/O bank and B2B connector: 

For detailed information about the pin out, please refer to the Master Pinout Table. 

Default MIO Mapping

Gigabit Ethernet

On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an onboard 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).

Ethernet PHY connection

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an onboard 52MHz oscillator (U15).

USB PHY connection

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I2C devices are connected to MIO48 and MIO49 which are configured as I2C1 by default. I2C addresses for on-board devices are listed in the table below:

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2. 

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Boot Mode Pin

By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.

LED's

Onboard Peripherals

Processing System (PS) Peripherals

Clocking

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the main board. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.

PLL - Phase-Locked Loop

There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.

PLL connection

MAC-Address EEPROM

A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

 * TBD - To Be Determined soon with reference design setup.

Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise, this is due to the DC/DC converter efficiency (it decreases when VIN/VOUT ratio rises). Typical power consumption is between 2-3W.

Power-On Sequence

For highest efficiency of on board DC/DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/O's are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.

Bank Voltages

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

• Module size: 50 mm × 40 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 8mm

• PCB thickness: 1.6mm

• Highest part on PCB: approx. 2.5mm. Please download the step model for exact numbers

 All dimensions are given in mm.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Weight

26 g - Plain module

8.8 g - Set of bolts and nuts

Document Change History

Date	Rrevision	Contributors	Description
2016-06-28			New overall document layout with shorter table of contents. Revision 01 PCB pictures replaced with the revision 03 ones. Fixed link to Master Pinout Table. New default MIO mapping table design. Revised Power-on section. Added links to related Xilinx online documents. Physical dimensions pictures revised. Revision number picture with explanation added.
2016-04-27	V33	Philipp Bernhardt, Antti Lukats, Thorsten Trenz, Emmanuel Vassilakis	Added the table "Recommended Operating Conditions" Storage Temperature edited.
2016-03-31	V10	Philipp Bernhardt, Antti Lukats, Thorsten Trenz	Initial version.

Hardware Revision History

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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