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Table of Contents
Overview
The Trenz Electronic TEI0015 is a commercial-grade, low cost and small size module integrated with Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Refer to http://trenz.org/tei0015-info for the current online version of this manual and other available documentation.
Key Features
Intel® MAX 10 Commercial [10M08SAU169C8G]
Package: UBGA-169
Speed Grade: C8 (Slowest)
Temperature: 0°C ~ 85°C
Package compatible device 10M02...10M16 as assembly variant on request possible
SDRAM Memory up to 64Mb, 166MHz
Dual High Speed USB to Multipurpose UART/FIFO IC
64 Mb Quad SPI Flash
4Kb EEPROM Memory
8x User LED
Micro USB2 Receptacle 90
18 Bit 2MSPS Analog to Digital Converter
2x SMA Female Connector
I/O interface:
23x GPIO
Power Supply:
5V
Minimum 1A
Dimension: 86.5mm x 25mm
Others:
Instrumentation Amplifier
Differential Amplifier
Operational Amplifier
Block Diagram
TEI0015 block diagram
Main Components
TEI0015 main components
SMA Connector, J5...6
Amplifier, U12- U14- U6
Series Voltage Reference, U8
Analog to Digital Convertor, U15
Voltage Regulator, U10- U13- U16
Switching Voltage Regulator, U11- U4
SDRAM Memory, U2
- Intel® MAX 10, U1
Active serial Memory, U5
12.00 MHz MEMS oscillator, U7
FTDI USB2 to JTAG/UART adapter, U3
User LEDs, D2...9
4Kb EEPROM, U9
Configuration LED (Red) , D10
Power-on LED (Green), D1
Push button, S1...2
Micro USB2 Receptacle, J9
1x14 pin header (Not assembled), J2
1x6 pin header (Not assembled), J4
Jumper, J3
1x14 pin header (Not assembled), J1
Initial Delivery State
Storage device name | Content | Notes |
|---|---|---|
Quad SPI Flash | Not Programmed | |
| EEPROM | Programmed | FTDI configuration |
| SDRAM | Not Programmed |
Initial delivery state of programmable devices on the module
Configuration Signals
The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Reset process must be done by pressing push button S1.
Signal | Push Button | Pin Header | Note |
|---|---|---|---|
RESET | S1 | J2 | connected to nCONFIG |
Reset process.
Signals, Interfaces and Pins
I/Os on Pin Headers and Connectors
| FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
|---|---|---|---|---|
| Bank 1A | J1 | 7 | 3.3V | AIN0...6 |
| Bank 1B | J4 | 5 | 3.3V | JTAG interface |
| Bank 2 | J1 | 4 | 3.3V | DIO2...5 |
| Bank 5 | J2 | 9 | 3.3V | DIO6...14 |
| J1 | 2 | 3.3V | DIO0...1 | |
| Bank 8 | J2 | 1 | 3.3V | RESET |
General I/Os to Pin Headers and connectors information
FPGA I/O Banks
| FPGA Bank | I/O Signal Count | Connected to | Notes |
|---|---|---|---|
| Bank 1A | 7 | 1x14 Pin header, J1 | AIN0...6 |
| 1 | Jumper, J3 | AIN7 | |
| Bank 1B | 5 | 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK |
| Bank 2 | 4 | 1x14 Pin header, J1 | D2...5 |
| 5 | A2D, U15 | ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV | |
| 1 | 12MHz Oscillator, U7 | CLK12M | |
| 2 | Amplifier, U12 | nIAMP_A0, nIAMP_A1 | |
| Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD |
| Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 |
| 2 | 1x14 Pin header, J1 | DIO0...1 | |
| 1 | D12_R | DIO12 | |
| Bank 6 | 16 | SDRAM, U2 | DQ0...15 |
| 2 | SDRAM, U2 | DQM0...1 | |
| 1 | D11_R | DIO11 | |
| Bank 8 | 8 | User Red LEDs, D2...9 | LED0...7 |
| 6 | SPI Flash, U5 | F_CS, F_CKL, F_DI, F_DO, nSTATUS, DEVCLRn | |
| 1 | Red LED, D10 | CONF_DONE | |
| 6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 | |
| 1 | Push Button, S2 | USER_BTN |
FPGA I/O Banks
Micro USB2.0 Connector
The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.
| Pins | Connected to | Note |
|---|---|---|
| VBUS | USB_VBUS | It is connected to GND |
| D+ | FTDI FT2232H U3, DP pin | |
| D- | FTDI FT2232H U3, DM pin |
Micro USB-2 connector pins
JTAG Interface
JTAG access to the TEI0015 SoM through pin header connector J4.
JTAG Signal | Pin Header Connector | Note |
|---|---|---|
| TMS | J4-6 | |
| TDI | J4-5 | |
| TDO | J4-4 | |
| TCK | J4-3 | |
| JTAG_EN | J4-2 | Connected to 3.3V |
JTAG pins connection
On-board Peripherals
| Chip/Interface | Designator | Notes |
|---|---|---|
| SDRAM | U2 | |
| FTDI FT2232H | U3 | JTAG/UART Adapter |
| SPI Flash | U5 | |
| EEPROM | U9 | |
| Oscillator | U7 | 12MHz clock source |
| ADC | U12, U14 | Analog to Digital Converter |
| Push Buttons | S1...2 | |
| 8x User LEDs | D2...9 | Red LEDs |
On board peripherals
SDRAM
TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
| SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
|---|---|---|---|
| Address inputs | A0 ... A13 | bank 3 | - |
| Bank address inputs | BA0 / BA1 | bank 3 | - |
| Data input/output | DQ0 ... DQ15 | bank 6 | - |
| Data mask | DQM0 ... DQM1 | bank 6 | - |
| Clock | CLK | bank 3 | |
| Control Signals | CS | bank 3 | Chip select |
CKE | bank 3 | Clock enable | |
RAS | bank 3 | Row Address Strobe | |
CAS | bank 3 | Column Address Strobe | |
| WE | bank 3 | Write Enable |
SDRAM interface IOs and pins
FTDI FT2232H
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip. FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
| FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
|---|---|---|---|
| ADBUS0 | TCK | FPGA bank 1B, pin G2 | JTAG interface |
| ADBUS1 | TDI | FPGA bank 1B, pin F5 | |
| ADBUS2 | TDO | FPGA bank 1B, pin F6 | |
| ADBUS3 | TMS | FPGA bank 1B, pin G1 | |
| BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | user configurable |
| BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | user configurable |
| BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | user configurable |
| BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | user configurable |
| BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | user configurable |
| BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | user configurable |
FTDI chip interfaces and pins
SPI Flash
On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.
| Signal Schematic Name | Connected to | Notes |
|---|---|---|
| F_CS | FPGA bank 8, pin B3 | chip select |
| F_CLK | FPGA bank 8, pin A3 | clock |
| F_DI | FPGA bank 8, pin A2 | data in / out |
| nSTATUS | FPGA bank 8, pin C4 | data in / out, configuration dual-purpose pin of FPGA |
| DEVCLRN | FPGA bank 8, pin B9 | data in / out, configuration dual-purpose pin of FPGA |
| F_DO | FPGA bank 8, pin B2 | data in / out |
Quad SPI Flash memory interface
EEPROM
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
| Schematic | Connected to | Notes |
|---|---|---|
EECS | FTDI U3, Pin EECS | |
| EECLK | FTDI U3, Pin EECLK | |
| EEDATA | FTDI U3, Pin EEDATA |
I2C EEPROM interface MIOs and pins
ADC
The TEI0015 board is equipped with the 18-bit 2MSPS ADC provided by Analog Devices, .
| Pins | Connected to | Notes |
|---|---|---|
IN+ | Diff Amplifier U14, VOUT- | |
| IN- | Diff Amplifier U14, VOUT+ | |
| SDI | FPGA, bank 2, pin M2, ADC_SDI | |
| SDO | FPGA, bank 2, pin M1, ADC_SDO | |
| SCK | FPGA, bank 2, pin N3, ADC_SCK | |
| CNV | FPGA, bank 2, pin N2, ADC_CNV |
A2D converter interface and pins
LEDs
| Designator | Color | Connected to | Active Level | Note |
|---|---|---|---|---|
| D2...9 | Red | LED1...8 | Active High | User LEDs |
| D10 | Red | CONF_DONE | Active Low | Configuration DONE LED |
| D1 | Green | 3.3V | Active High | After power on it will be on |
On-board LEDs
Push Bottuns
| Designator | Connected to | Functionality | Note |
|---|---|---|---|
| S1 | RESET | General reset | |
| S2 | USER_BTN | User push button | Connected to Bank 8 |
On-board Push Buttons
Clock Sources
| Clock Source | Schematic Name | Frequency | Note |
|---|---|---|---|
| Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3 Connected to FPGA SoC bank 2, pin H6 |
Osillators
Power and Power-On Sequence
Power Supply
To power-up the module, power supply with minimum current capability of 1A is recommended.
Power Consumption
| FPGA | Typical Current |
|---|---|
| Intel MAX 10 10M08 FPGA SoC | TBD* |
Power Consumption
* TBD - To Be Determined
Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
Power Distribution
Power-On Sequence
There is no specific or special power-on sequence, just one single power source is needed. After power on the Green LED (D1) will be on.
Power Rails
| Connector Designator | VCC / VCCIO Schematic Name | Voltage | Direction | Notes |
|---|---|---|---|---|
| J2 | VIN | 5V | Input | |
| 3.3V | 3.3V | Output | ||
| 5V | 5V | Output | ||
J9 | USB_VBUS | 5V | Input |
Module power rails.
Bank Voltages
Bank | Schematic Name | Voltage | Notes |
|---|---|---|---|
| Bank 1A | VCCIO1A | 3.3V | |
| Bank 1B | VCCIO1B | 3.3V | |
| Bank 2 | VCCIO2 | 3.3V | |
| Bank 3 | VCCIO3 | 3.3V | |
| Bank 5 | VCCIO5 | 3.3V | |
| Bank 6 | VCCIO6 | 3.3V | |
| Bank 8 | VCCIO8 | 3.3V |
Intel MAX SoC bank voltages.
Technical Specifications
Absolute Maximum Ratings
| Symbols | Description | Min | Max | Unit | Reference Document |
|---|---|---|---|---|---|
VIN | Supply voltage | 4.75 | 5.25 | V | |
| VCC_ONE | Supply voltage for core and periphery through on-die voltage regulator | -0.5 | 3.9 | V | Intel MAX 10 datasheet |
| VCCIO | Supply voltage for input and output bufferse | -0.5 | 3.9 | V | Intel MAX 10 datasheet |
| VCCA | Supply voltage for phase-locked loop (PLL) regulator and ADC | -0.5 | 3.9 | V | Intel MAX 10 datasheet |
| V_AN_IN | Analog Input Voltage on ADC IC U15 pins | –0.3 | 5.4 | V | AD4003BCPZ datasheet |
| V_REF | Analog reference voltage on IC U15 | -0.3 | 6 | V | AD4003BCPZ datasheet |
| CH1+ | Analog input voltage on amplifier U12 pin 10 | 25 | V | AD8251ARMZ datasheet | |
| CH1- | Analog input voltage on amplifier U12 pin 1 | -25 | V | AD8251ARMZ datasheet | |
T_STG | Storage Temperature | -25 | +85 | °C |
Absolute maximum ratings
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
| Symbols | Min | Max | Unit | Reference Document |
|---|---|---|---|---|
VIN supply voltage (5.0V nominal) | 4.75 | 5.25 | V | |
| VCC_ONE | 3.135 | 3.456 | V | see Intel MAX 10 datasheet |
| VCCIO | 3.135 | 3.456 | V | see Intel MAX 10 datasheet |
| VCCA | 3.135 | 3.456 | V | see Intel MAX 10 datasheet |
| V_AN_IN | -0.1 | 5.1 | V | see AD4003BCPZ datasheet |
| V_REF | 2.4 | 5.1 | V | see AD4003BCPZ datasheet |
T_OP | 0 | +70 | °C | W9864G6JT-6 datasheet |
Recommended operating conditions.
Physical Dimensions
Module size: 25 mm × 86.5 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1.22 mm.
Physical Dimension
Currently Offered Variants
| Trenz shop TEI0015 overview page | |
|---|---|
| English page | German page |
Trenz Electronic Shop Overview
Revision History
Hardware Revision History
| Date | Revision | Changes | Documentation Link |
|---|---|---|---|
| 2019-02-11 | 01 | - | REV01 |
Hardware Revision History
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Board hardware revision number.
Document Change History
| Date | Revision | Contributor | Description |
|---|---|---|---|
| |||
-- | all |
|
Document change history.
Disclaimer
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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
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