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The Trenz Electronic TEI0015 is an commercial-grade, low cost and small size module integrated with Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Refer to http://trenz.org/tei0015-info for the current online version of this manual and other available documentation.
8x User LED
USB port
18 Bit Analog to Digital Converter
2x SMA Female Connector
Power Supply:
5V
Others:
Dimension: 86m x 25m
Instrumentation Amplifier
Voltage Feedback Amplifier
Storage device name | Content | Notes |
---|---|---|
Quad SPI Flash | Not Programmed | |
I2C Configuration EEPROM | Programmed | |
SDRAM | Not Programmed |
The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Reset process must be done by pressing push button S1.
Signal | Push Button | Pin Header | Note |
---|---|---|---|
RESET | S1 | J2 | connected to nCONFIG |
FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
---|---|---|---|---|
Bank 1A | J1 | 7 | 3.3V | AIN0...6 |
Bank 1B | J4 | 5 | 3.3V | JTAG interface |
Bank 2 | J1 | 4 | 3.3V | DIO2...5 |
Bank 5 | J2 | 9 | 3.3V | DIO6...14 |
J1 | 2 | 3.3V | DIO0...1 | |
Bank 8 | J2 | 1 | 3.3V | RESET |
FPGA Bank | I/O Signal Count | Connected to | Notes |
---|---|---|---|
Bank 1A | 7 | 1x14 Pin header, J1 | AIN0...6 |
1 | Jumper, J3 | AIN7 | |
Bank 1B | 5 | 1x6 Pin header, J4 | JTAG_EN, TDI, TDO, TMS, TCK |
Bank 2 | 4 | 1x14 Pin header, J1 | D2...5 |
5 | A2D, U15 | ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV | |
1 | 12MHz Oscillator, U7 | CLK12M | |
2 | Amplifier, U12 | nIAMP_A0, nIAMP_A1 | |
Bank 3 | 22 | SDRAM, U2 | RAM_ADDR_CMD |
Bank 5 | 9 | 1x14 Pin header, J2 | DIO6...14 |
2 | 1x14 Pin header, J1 | DIO0...1 | |
1 | D12_R | DIO12 | |
Bank 6 | 16 | SDRAM, U2 | DQ0...15 |
2 | SDRAM, U2 | DQM0...1 | |
1 | D11_R | DIO11 | |
Bank 8 | 8 | User Red LEDs, D2...9 | LED0...7 |
6 | SPI Flash, U5 | F_CS, F_CK, F_DI, F_DO, nSTATUS, DEVCLRn | |
1 | Red LED, D10 | CONF_DONE | |
6 | FTDI JTAG/UART Adapter, U3 | BDBUS0...5 | |
1 | Push Button, S2 | USER_BTN |
JTAG access to the TEI0015 SoM through pin header connector J4.
JTAG Signal | Pin Header Connector |
---|---|
TMS | J4-6 |
TDI | J4-5 |
TDO | J4-4 |
TCK | J4-3 |
JTAG_EN | J4-2 |
Chip/Interface | Designator | Notes |
---|---|---|
SDRAM | U2 | |
FTDI FT2232H | U3 | JTAG/UART Adapter |
SPI Flash Memory | U5 | |
EEPROM | U9 | |
Oscillator | U7 | 12MHz clock source |
A2D Convertor | U12, U14 | Analog to Digital Convertor |
8x User LEDs | D2...9 | Red LEDs |
TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.
SDRAM I/O Signals | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
Address inputs | A0 ... A13 | bank 3 | - |
Bank address inputs | BA0 / BA1 | bank 3 | - |
Data input/output | DQ0 ... DQ15 | bank 6 | - |
Data mask | DQM0 ... DQM1 | bank 6 | - |
Clock | CLK | bank 3 | |
Control Signals | CS | bank 3 | Chip select |
CKE | bank 3 | Clock enable | |
RAS | bank 3 | Row Address Strobe | |
CAS | bank 3 | Column Address Strobe | |
WE | bank 3 | Write Enable |
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
ADBUS0 | TCK | FPGA bank 1B, pin G2 | JTAG interface |
ADBUS1 | TDI | FPGA bank 1B, pin F5 | |
ADBUS2 | TDO | FPGA bank 1B, pin F6 | |
ADBUS3 | TMS | FPGA bank 1B, pin G1 | |
BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | user configurable |
BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | user configurable |
BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | user configurable |
BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | user configurable |
BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | user configurable |
BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | user configurable |
On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.
Signal Schematic Name | Connected to | Notes |
---|---|---|
F_CS | FPGA bank 8, pin B3 | chip select |
F_CLK | FPGA bank 8, pin A3 | clock |
F_DI | FPGA bank 8, pin A2 | data in / out |
nSTATUS | FPGA bank 8, pin C4 | data in / out, configuration dual-purpose pin of FPGA |
DEVCLRN | FPGA bank 8, pin B9 | data in / out, configuration dual-purpose pin of FPGA |
F_DO | FPGA bank 8, pin B2 | data in / out |
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
Schematic | Connected to | Notes |
---|---|---|
EECS | FTDI U3, Pin EECS | |
EECLK | FTDI U3, Pin EECLK | |
EEDATA | FTDI U3, Pin EEDATA |
The TEI0010 board is equipped with the Analog Devices AD4003BCPZ-RL7, 18-bit A2D converter (ADC) ADC and digital GPIO's can be operated at 20MHz.
Schematic | Connected to | Notes |
---|---|---|
EECS | FTDI U3, Pin EECS | |
EECLK | FTDI U3, Pin EECLK | |
EEDATA | FTDI U3, Pin EEDATA |
Designator | Color | Connected to | Active Level | Note |
---|---|---|---|---|
D2...9 | Red | LED1...8 | Active High | User LEDs |
D10 | Red | CONF_DONE | Active Low | Configuration DONE LED |
D1 | Green | 3.3V Power Rail | Active High | After power on it will be on |
Clock Source | Schematic Name | Frequency | Note |
---|---|---|---|
Microchip MEMS Oscillator, U7 | CLK12M | 12.00 MHz | Connected to FTDI FT2232 U3, pin 3 Connected to FPGA SoC bank 2, pin H6 |
Power supply with minimum current capability of xx A for system startup is recommended.
Power Input Pin | Typical Current |
---|---|
VIN | TBD* |
* TBD - To Be Determined
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
---|---|---|---|---|---|
Bank | Schematic Name | Voltage | Notes |
---|---|---|---|
? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
Symbols | Description | Min | Max | Unit |
---|---|---|---|---|
V | ||||
V | ||||
V | ||||
V | ||||
V | ||||
V | ||||
V | ||||
V | ||||
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
V | See ???? datasheets. | |||
V | See Xilinx ???? datasheet. | |||
V | See Xilinx ???? datasheet. | |||
V | See Xilinx ???? datasheet. | |||
V | See Xilinx ???? datasheet. | |||
V | See Xilinx ???? datasheet. | |||
V | See Xilinx ???? datasheet. | |||
°C | See Xilinx ???? datasheet. | |||
°C | See Xilinx ???? datasheet. |
Module size: ?? mm × ?? mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? mm.
PCB thickness: ?? mm.
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Trenz shop TE0728 overview page | |
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English page | German page |
List of online PCN ...Link
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