Table of contents
Overview
Zynq Design PS with Linux and two Ethernet PHYs connected over EMIO and PL.Key Features
Revision History
| Date | Vivado | Project Built | Authors | Description |
|---|---|---|---|---|
| 2017-09-11 | 2017.1 | te0728 | John Hartfiel | initial release |
Release Notes and Know Issues
| Issues | Description | Workaround | To be fixed version |
|---|---|---|---|
| Wrong UBoot ETH PHY Address | PHY Address is not set correctly for UBoot | --- | --- |
Linux Message: "macb ... .ethernet eth...: unable to generate target frequency: 25000000 Hz" | This can be ignored, ETH works. |
Requirements
Software
| Software | Version | Note |
|---|---|---|
| Vivado | 2017.2 | needed |
| SDK | 2017.2 | needed |
| PetaLinux | 2017.2 | needed |
Hardware
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
| Module Model | Board Part Short Name | PCB Revision Support | Notes |
|---|---|---|---|
| TE0728-03-1Q | 03_1q | 01,02,03 | |
| TE0728-04-1Q | 04_1q | 04 |
Design supports following carriers:
| Carrier Model | Notes |
|---|---|
| TEB0728 |
Additional HW Requirements:
| Additional Hardware | Notes |
|---|---|
| USB Cable for JTAG/UART | |
| XMOD Programmer |
Content
For general structure and of the reference design, see Project Delivery
Design Sources
| Type | Location | Notes |
|---|---|---|
| Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
| SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
| PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Additional Sources
| Type | Location | Notes |
|---|---|---|
Prebuilt
File | File-Extension | Description |
|---|---|---|
| BIF-File | *.bif | File with description to generate Bin-File |
| BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
| BIT-File | *.bit | FPGA (PL Part) Configuration File |
| Diverse Reports | --- | Report files in different formats |
| Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
| LabTools Project-File | *.lpr | Vivado Labtools Project File |
| OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
| Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.
MIO Bank 501 Power is Carrier depends and set to 3.3V. Please check Settings, if you use a own carrier.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Use TE Template from /os/petalinux
- HDF is exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
Launch
Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Not used on this Example.
SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- ETH0 works with udhcpc
- ETH1 must be configured manually
- ifconfig eth1 up
- ifconfig eth1 <ip>
Note for Ping test disable ETH0
- RTC check: dmesg | grep rtc
System Design - Vivado
Block Design
PS Interfaces
| Type | Note |
|---|---|
| DDR | --- |
| QSPI | MIO |
| CAN1 | MIO |
| ETH0 | EMIO |
| ETH1 | EMIO |
| SD0 | MIO |
| UART1 | MIO |
| I2C0 | MIO |
| SPI1 | MIO |
| GPIO | MIO/EMIO |
| TIMER0 | EMIO |
Constrains
Basic module constrains
_i_bitgen_common.xdc
# # Common bitgen related settings # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
Design specific constrain
Software Design - SDK/HSI
For SDK project creation, follow instructions from:
Application
FSBL
Xilinx default FSBL
U-Boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
Description currently not available.
Config
No changes.
U-Boot
No changes.
Device Tree
/include/ "system-conf.dtsi"
/ {
};
/* ETH PHY */
&gem0 {
phy-mode = "mii";
status = "okay";
ethernet_phy0: ethernet-phy@0 {
// compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <1>;
};
};
&gem1 {
phy-mode = "mii";
status = "okay";
local-mac-address = [00 0a 35 00 1e 01];
ethernet_phy1: ethernet-phy@1 {
// compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <2>;
};
};
/* RTC */
&i2c0 {
rtc@56 { // Real Time Clock
compatible = "rv3029c2";
reg = <0x56>;
};
};
Kernel
Activate:
- RTC_DRV_RV3029C2
Rootfs
Activate:
- I2C-tools
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Additional Software
No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
| Date | Document Revision | Authors | Description |
|---|---|---|---|
| Work in progress | ||
| 2017-09-11 | v.1 | Initial release | |
| All |
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