TE0865 TRM

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Overview

The Trenz Electronic TE0865  is an industrial/extended grade module based on Xilinx Zunq UltraScale+ MPSoC. The TE0865 is equipped with 4x 2GB DDR4 SDRAM connected to Programmable Logic(PL) and 5x 2GB DDR4 SDRAM connected to Processing System(PS), 8 GB eMMC, 2x 64MB Quad SPI Flash, Gigabit Ethernet Transceiver, USB Transceiver, Ultra micro power terminal and an Intel MAx 10 as system controller CPLD. 

Refer to http://trenz.org/te0865-info for the current online version of this manual and other available documentation.

Key Features

• SoC/FPGA
  
  • Package: C1760
  • Device: ZU11, ZU17, ZU19*
  • Engine: EG*
  • Speed: -1, -2,*, **
  • Temperature: I, E,*, **
• RAM/Storage
  • Low Power DDR4 on PS
    • Data width: 16bit
    • Size: def. 2GB*
    • Speed: 3200 (MT/s) ***
  • Low Power DDR4 on PL
    • Data width: 16bit
    • Size: def. 2GB*
    • Speed:***
  •  eMMC
    • Data width: 8Bit
    • size: def. 8GB *
  • Dual QSPI boot Flash in dual parallel mode (size depends on assembly version)
    • Data width: 8bit
    • size: def. 64MB *
  • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
• On Board
  
  • Intel Max 10 as CPLD
  • 6x MEMS Oscillator
  • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
  • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3340C)
• Interface
  • 214 x PS I/Os
  • 96x HD I/Os
  • 416x HP I/Os
  • 4x PS GTR
  • 3x Samtec Accelerate HD B2B connector
  • 78x MIOs
• Power
  
  • 12V input supply voltage
  • Variable Bank IO Power Input
• Dimension
  • 7.5 cm x 10 cm
• Notes
  • * depends on assembly version
  • ** also non low power assembly options possible
  • *** depends on used U+ Zynq and DDR4 combination

Block Diagram

Main Components

1. ZYNQ Ultrascale+ MPSoC FPGA, U30
2. PL DDR4 SDRAM, U9, U10, U28, U29
3. PS DDR4 SDRAM, U5...U8, U11
4. Intel MAX 10 FPGA, U46
5. eMMC RAM, U1
6. Dual QSPI Flash, U32, U33
7. Crypto Authentication IC, U19
8. OPTIGA Trust M Authentication IC, U16
9. EEPROM MAC Address, U14
10. USB2.0 Transceiver, U2
11. Gigabit Ethernet Transceiver, U17
12. B2B Connector, J2
13. B2B Connector, J3
14. B2B Connector, J1
15. B2B Connector, J4
16. Power Terminal, J5

Initial Delivery State

Configuration Signals

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

Zynq MPSoC's I/O banks signals connected to the B2B connectors:

For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

JTAG Interface

JTAG access to the UltraScale+ MPsoC FPGA through B2B connector J3B.

JTAG access to the system controller CPLD, Intel MAX10 FPGA(U46) through B2B connector J2B.

MIO Pins

Test Points

On-board Peripherals

CPLD

Quad SPI Flash Memory

eMMC Memory

eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.

DDR4 Memory

The TE0820 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.

• Part number: K4A8G165WB-BIRC
• Supply voltage: 1.2V
• Speed: 2400 Mbps
• Temperature: -40 ~ 95 °C

Quad SPI Flash Memory

Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Gigabit Ethernet

On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U11).

High-speed USB ULPI PHY

USB2.0 Transceiver

Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).

EEPROM

There is a 2Kb EEPROM (U25) provided on the module TE0820.

Crypto Authentication

OPTIGA Authentication

EEPROM

PL DDR4 SDRAM

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

• Part number: 
• Supply voltage:
• Speed: 
• NOR Flash
• Temperature: 

PS DDR4 SDRAM

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

• Part number: 
• Supply voltage:
• Speed: 
• NOR Flash
• Temperature:

Ethernet

eMMC

Clock Sources

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

* TBD - To Be Determined

Power Distribution Dependencies

Power-On Sequence

Voltage Monitor Circuit

Power Rails

Bank Voltages

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Components are mainly classified in 3 temperature groups, according to range specifications: commercial: 0°C - 75°C extended: 0°C - 85°C industrial: -40°C - 85°C

Classification of the module can be locked up here: Article Number Information i.e.: TE0803-03-5D"I"21-AS (The I indicates industrial)

The actual operation temperature range depends on the FPGA/SoC design/utilization and cooling, as well as other variables. Please note: These are only indications!

Physical Dimensions

• Module size: 75 mm × 100 mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 5 mm.

PCB thickness: 2 mm.

Currently Offered Variants 

Revision History

Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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