TE0818 TRM (more or less equal to TE0808 but other connectors)

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Overview

The Trenz Electronic TE0818 is an industrial grade MPSoC SOM integrating a Xilinx Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to http://trenz.org/te0818-info for the current online version of this manual and other available documentation.

Key Features

SoC
- Device: ZU6 / ZU9 / ZU15 ¹⁾
- Engine: CG / EG ¹⁾
- Speedgrade: -1 / -2 ¹⁾
- Temperature Range: Extended / Industrial ¹⁾
- Package: FFVC900
RAM/Storage
- 4 GByte DDR4 SDRAM ²⁾
- 2 x 64 MByte Serial Flash ³⁾
- EEPROM with MAC address
On Board
- Oscillator
Interface
- 4 x B2B Connector (ADM6)
  - up to 204 PL IO
    - HP: 156
    - HD: 48
  - up to 65 PS MIO
  - 4 GTR
  - 16 GTH
  - I2C, JTAG, CONFIG
Power
- 3.3 V power supply via B2B Connector needed ⁴⁾.
Dimension
- 76 mm x 52 mm
Notes
¹⁾ Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
²⁾ Up to 32 GByte are possible with a maximum bandwidth of 2400 MBit/s.
³⁾ Please, take care of the possible assembly options.
⁴⁾ Dependant on the assembly option a higher input voltage may be possible

TExxxx block diagram

Main Components

TExxxx main components

SoC, U1
DDR4, U2, U3, U9, U12
Quad SPI Flash, U7, U17
Connector, J1, J2, J3, J4
EEPROM, U4
Clock Generator, U5
Oscillator, U25, U32

Initial Delivery State

Storage device name	Content	Notes
DDR4 SDRAM	not programmed
Quad SPI Flash	not programmed
EEPROM	not programmed besides factory programmed MAC address
Programmable Clock Generator	not programmed

Initial delivery state of programmable devices on the module

Signals, Interfaces and Pins

Connectors

Connector Type	Designator	Interface	IO CNT ¹⁾
B2B	JM1	MGT PL	12 x MGT (RX/TX)
B2B	JM1	HP	52 SE / 24 DIFF
B2B	JM2	MGT PS	2 x MGT CLK
B2B	JM2	CLK	DIFF CLK
B2B	JM2	MGT PL	4 x MGT (RX/TX)
B2B	JM2	MGT PS	4 x MGT (RX/TX)
B2B	JM2	CFG	JTAG
B2B	JM2	CFG	MODE
B2B	JM3	HD	48 SE / 24 DIFF
B2B	JM3	MGT PL	3 x MGT CLK
B2B	JM3	CLK	DIFF CLK
B2B	JM3	MIO	65 GPIO
B2B	JM4	HP	104 SE / 48 DIFF

¹⁾ IO CNT depends on assembly variant. E.g. the MGTs are not available for all FPGAs

Board Connectors

Test Points

Test Point	Signal	Notes¹⁾
TP1	PLL_SCL	pulled-up to PS_1V8
TP2	PLL_SDA	pulled-up to PS_1V8
TP3	LP_DCDC
TP4	DCDCIN
TP5	GND
TP6	TCK
TP7	PL_DCIN
TP8	GND
TP9	GT_DCDC
TP10	GND
TP11	TDI
TP12	TDO
TP13	TMS
TP14	PS_1V8
TP15	No Net Name	REF3312AIDCKT (U33) ouput voltage
TP16	FP_0V85
TP17	DDR_2V5
TP18	DDR_PLL
TP19	PL_VCCINT
TP20	AUX_R
TP21	AVTT_R
TP22	AUX_L
TP24	AVCC_R
TP26	AVTT_L
TP28	AVCC_L
TP30	PS_PLL
TP31	PS_AVTT
TP32	LP_0V85
TP33	PS_AUX
TP34	PS_AVCC
TP36	POR_B

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Test Points Information

On-board Peripherals

Chip/Interface	Designator	Connected To	Notes
DDR4 SDRAM	U2, U3, U9, U12	SoC - PS
Quad SPI Flash	U7, U17	SoC - PS	Booting.
EEPROM	U4	B2B - J2
Clock Generator	U5	SoC, B2B
Oscillator	U25	Clock Generator	25 MHz
Oscillator	U32	SoC	33.333333 MHz

On board peripherals

Configuration and System Control Signals

Connector+Pin	Signal Name	Direction¹⁾	Description
JM1.A45	POR_OVERRIDE	IN	Override power-on reset delay ²⁾.
JM2.A30	PG_PLL_1V8	OUT	SI_PLL_1V8 power rail powered-up.
JM2.A31	ERR_OUT	OUT	PS error indication ²⁾.
JM2.A34	ERR_STATUS	OUT	PS error status ²⁾.
JM2.A35	LP_GOOD	OUT	Low-power domain powered-up. Pulled up to 3.3VIN.
JM2.A36	PLL_SCL	IN	I2C clock. Pulled up to PS_1V8.
JM2.A37	PLL_SDA	IN/OUT	I2C data. Pulled up to PS_1V8.
JM2.A40	PG_GT_L	OUT	Left GTH Transceivers powered-up.
JM2.A41	EN_PSGT	IN	Enable GTR transceiver power-up.
JM2.A44 / JM2.A45 / JM2.A46 / JM2.A47	TCK / TDI / TDO / TMS	Signal-dependent	JTAG configuration and debugging interface. JTAG reference voltage: PS_1V8
JM2.B29	PG_PSGT	OUT	GTR transceivers powered-up.
JM2.B30	PROG_B	IN/OUT	Power-on reset ²⁾. Pulled-up to PS_1V8.
JM2.B33	SRST_B	IN	System reset ²⁾. Pulled-up to PS_1V8.
JM2.B34	INIT_B	IN/OUT	Initialization completion indicator after POR ²⁾. Pulled-up to PS_1V8.
JM2.B37	PG_PL	OUT	Programmable logic powered-up.
JM2.B38	EN_FPD	IN	Enable full-power domain power-up.
JM2.B41	PG_FPD	OUT	Full-power domain powered-up.
JM2.B42	EN_LPD	IN	Enable low-power domain power-up.
JM2.B45	PG_DDR	OUT	DDR power supply powered-up.
JM2.B46	DONE	OUT	PS done signal ²⁾. Pulled-up to PS_1V8.
JM2.B47	EN_DDR	IN	Enable DDR power-up.
JM2.C30	EN_GT_L	IN	Enable left GTH transceiver power-up.
JM2.C31	MR	IN	Manual reset.
JM2.C32	PLL_SEL0	IN	PLL clock selection.
JM2.C33	PLL_RST	IN	PLL reset. Pulled-up to PS_1V8.
JM2.C35	EN_PL	IN	Enable programable logic power-up.
JM2.C36	EN_GT_R	IN	Enable right GTH transceiver power-up.
JM2.C37	PLL_FDEC	IN	PLL Frequency decrementation.
JM2.C44 / JM2.C45 / JM2.C46 / JM2.C47	MODE3..0	IN	Boot mode selection ²⁾: JTAG QUAD-SPI (32 Bit) SD1 (2.0) eMMC (1.8 V) SD1 LS (3.0) Supported Modes depends also on used Carrier.
JM2.D29	EN_PLL_PWR	IN	Enable PLL power supply.
JM2.D30	PLL_FINC	IN	PLL Frequency incrementation.
JM2.D31	PLL_LOLn	OUT	Loss of lock status.
JM2.D32	PLL_SEL1	IN	PLL clock selection.
JM2.D33	PG_GT_R	OUT	Right GTH Transceivers powered-up.
JM2.D37	PSBATT	IN	PS RTC Battery supply voltage ^{2) 3)}.
JM2.D38	PUDC_B	IN	Configuration pull-ups setting ²⁾. Pulled-up to PL_1V8.
JM2.D45 / JM2.D46	DX_P / DX_N	-	SoC temperatur sensing diode pins ²⁾.

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

²⁾ See UG1085 for additional information.

Controller signal.

Power and Power-On Sequence

Power Rails

Power Rail Name/ Schematic Name	Connector + Pin	Direction¹⁾
VCCO_66	JM1.A32 / JM1.A33	IN
VREF_66	JM1.A41	IN
3.3VIN	JM1.A54 / JM1.A55 / JM1.B55 / JM1.B56	IN
PL_1V8	JM1.C32 / JM1.C33 / JM1.D33 / JM1.D34	OUT
PL_DCIN	JM1.C56 / JM1.C57 / JM1.C58 / JM1.C59 / JM1.C60 / JM1.D56 / JM1.D57 / JM1.D58 / JM1.D59 / JM1.D60	IN
LP_DCDC	JM2.A50 / JM2.A51 / JM2.A52 / JM2.B50 / JM2.B51 / JM2.B52 / JM2.C50 / JM2.C51 / JM2.C52 / JM2.D50 / JM2.D51 / JM2.D52	IN
DCDCIN	JM2.A57 / JM2.A58 / JM2.A59 / JM2.A60 / JM2.B57 / JM2.B58 / JM2.B59 / JM2.B60 / JM2.C57 / JM2.C58 / JM2.C59 / JM2.C60 / JM2.D57 / JM2.D58 / JM2.D59 / JM2.D60 /	IN
PS_BATT	JM2.D37	IN
DDR_1V2	JM2.D47	OUT
PS_1V8	JM2.C34 / JM2.D34 / JM3.A56 / JM3.B56 / JM3.C56 / JM3.D56	OUT
PLL_3V3	JM3.A55	IN
GT_DCDC	JM3.A59 / JM3.A60 / JM3.B59 / JM3.B60 / JM3.C59 / JM3.C60 / JM3.D59 / JM3.D60 /	IN
VCCO_48	JM3.C7 / JM3.C8 / JM3.D8 / JM3.D9	IN
VCCO_47	JM3.C19 / JM3.C20 / JM3.D20 / JM3.D21	IN
VCCO_64	JM4.B21 / JM4.B39	IN
VREF_64	JM4.B30	IN
VCCO_65	JM4.C21 / JM4.C39	IN
VREF_65	JM4.C30	IN

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Module power rails.

Recommended Power up Sequencing (ED: Needs to be checked in detail!!! It is only copied from TE0817 TRM.)

The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics.

Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration signal setup.	See Configuration and System Control Signals.
1 ¹⁾	PSBATT	1.2 V ... 1.5 V	-	Battery connection.	Battery Power Domain usage. When not used, tie to GND.
1	3.3VIN	3.3 V (± 5 %)	-	Management power supply.	Management module power supply. 0.5 A recommended.
GTH / GTR Transceiver clocking (Only necessary in cases where the PLL clock is used for GTH / GTH.):
1 ¹⁾	GT_DCDC	3.3 V (± 5 %) ²⁾		GTH transceiver power supply.	Main module power supply for GTH / GTY transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
1 ¹⁾	EN_PLL_PWR	-	PD ³⁾, GND	PLL power enable.
1 ¹⁾	PG_PLL_1V8	-	PU ³⁾, 3.3 V	PLL power good status.
2	Processing System (PS):	Procedure for PS starting.
2.1	Low-power domain:	Bring-up for low-power domain PS.
2.1.1	LP_DCDC	3.3 V (± 5 %) ²⁾	-	Low-power domain power supply.	Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
2.1.2	EN_LPD	-	PU ³⁾, 3.3 V	Low-power domain power enable.
2.1.3	LP_GOOD	-	PU ³⁾, 3.3 V	Low-power domain power good status.	Module power-on sequencing for low-power domain finished.
2.2	Full-power domain:	Bring-up for full-power domain PS.	Full-power PS domain needs powered low-power PS domain.
2.2.1	DCDCIN	3.3 V (± 5 %) ²⁾		Full-power domainand GTR transceiver power supply.	Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
2.2.2	EN_FPD	3.3 V	-	Full-power domain power enable.
2.2.3	PG_FPD	-	PU ³⁾, 3.3 V	Full-power domain power good status.	Module power-on sequencing for full-power domain finished.
2.2.4	EN_DDR	3.3 V	-	DDR memory power enable.
2.2.5	PG_DDR		PU ³⁾, 3.3 V	DDR memory power good status.	Module power-on sequencing for DDR memory finished.
2.3	GTR Transceiver	Procedure for GTR transceiver starting.	PS transceiver usage needs powered PS (low- and full-power domain).
2.3.1	EN_PSGT	3.3 V	-	GTR transceiver power enable.
2.3.2	PG_PSGT	-	PU ³⁾, 3.3 V	GTR transceiver power good status.	Module power-on sequencing for GTR transceiver finished.
2	Programmable Logic (PL)	Procedure for PL starting.	PS and PL can be started independently.
2.1	PL_DCIN	3.3 V (± 5 %) ²⁾ ⁴⁾	-	Programmable logic power supply.	Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.
2.2	EN_PL	-	PU ³⁾, 3.3 V	Programmable logic power enable.
2.3	PG_PL	-	PU ³⁾, 3.3 V	Programmable logic power good status.	Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
2.4	VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66	⁵⁾	-	Module bank voltages.	Enable bank voltages after PG_PL deassertion.
2.5	PG_VCU	-	PU ³⁾, 3.3 V	VCU power good status.
3	GTH / GTY Transceiver	Procedure for GTH / GTY transceiver starting.	PL transceiver usage needs powered PL and low-power PS domain.
3.1	GT_DCDC	3.3 V (± 5 %) ²⁾	-	GTH transceiver power supply.	Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
3.2	EN_GT_R	3.3 V	-	GTH / GTY transceiver power enable.
3.3	PG_GT_R	-	PU ³⁾, 3.3 V	GTH / GTY transceiver power good status.

¹⁾ (optional)

²⁾ Dependent on the assembly option a higher input voltage may be possible.

³⁾ (on module)

⁴⁾ This value depends highly on DCDC U4. Higher values may be possible with different DCDCs. For more information consult schematic and according datasheets.

⁵⁾ See DS925 for additional information.

Baseboard Design Hints

Board to Board Connectors

5.2 x 7.6 cm UltraSoM+ modules use four Samtec AcceleRate HD High-Density Slim Body Arrays on bottom side.
4x ADM6-60-01.5-L-4-2 (240 pins, 60 per row)
Mates with ADF6-60-03.5-L-4-2
5.2 x 7.6 cm UltraSoM+ carrier use four Samtec AcceleRate HD High-Density Slim Body Arrays on top side.
4x ADF6-60-03.5-L-4-2 (160-pins)
Mates with ADM6-60-01.5-L-4-2
Features
Board-to-Board Connector 240-pins, 60 contacts per row
0.025" (0.635 mm) pitch
Data Rate: max 56 Gbps
Mates with: ADM6/APF6
Insulator Material: LCP, Black
Contact Material: Copper Alloy
Plating: Au or Sn over 50 µ" (1.27 µm) N
Operating Temperature Range: -55 ºC to +125 ºC
PCIe 5.0 capable: Yes
Lead-Free Solderable: Yes
RoHS Compliant: Yes
Connector Stacking height
When using the standard type on baseboard and module, the mating height is 5 mm.
Other mating heights are possible by using connectors with a different height:
Order number REF number Samtec Number Type Contribution to stacking height Comment
30095 REF-30095 ADM6-60-01.5-L-4-2 Module connector 1.5 mm Standard connector used on modules
31137 REF-31137 ADF6-60-03.5-L-4-2 Baseboard connector 3.5 mm Standard connector used on carrier
Connectors.
Connector Speed Ratings
The AcceleRate HD High-Density connector speed rating depends on the stacking height; please see the following table:
Stacking height Speed rating
5 mm 56 Gbps
Speed rating.
Current Rating
Current rating of Samtec AcceleRate HD High-Density B2B connectors is 1.34 A per pin (4 pins powered)
Connector Mechanical Ratings
Shock: 100G, 6 ms Sine
Vibration: 7.5G random, 2 hours per axis, 3 axes total

Manufacturer Documentation

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Technical Specifications

Absolute Maximum Ratings ^*)

Power Rail Name/ Schematic Name	Description	Min	Max	Unit
				V
				V
				V
				V
				V
				V
				V
				V
				°C

PS absolute maximum ratings

^*) Stresses beyond those listed under TE0818 TRM (more or less equal to TE0808 but other connectors) may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under TE0818 TRM (more or less equal to TE0808 but other connectors). Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

Parameter	Min	Max	Units	Reference Document
			V	See ???? datasheets.
			V	See ???? datasheet.
			V	See ???? datasheet.
			V	See ???? datasheet.
			V	See ???? datasheet.
			V	See ???? datasheet.
			V	See ???? datasheet.
			°C	See ???? datasheet.

Recommended operating conditions.

Physical Dimensions

Module size: ?? mm × ?? mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? mm.

PCB thickness: ?? mm.

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Physical Dimension

Currently Offered Variants

Trenz shop TEXXXX overview page
English page	German page

Trenz Electronic Shop Overview

Revision History

Hardware Revision History

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Board hardware revision number.

Date	Revision	Changes	Documentation Link

Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

Date

Revision

Contributor

Description

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<add TRM change list here>

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Document change history.

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Document Warranty

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Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

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REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.

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Trenz Electronic Documentation

TE0818 TRM (more or less equal to TE0808 but other connectors)

Overview

Key Features

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Test Points

On-board Peripherals

DDR4 SDRAM

Quad SPI Flash

EEPROM

Clock Generator

Oscillator

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing (ED: Needs to be checked in detail!!! It is only copied from TE0817 TRM.)

Board to Board Connectors

Features

Connector Stacking height

Connector Speed Ratings

Current Rating

Connector Mechanical Ratings

Manufacturer Documentation

Technical Specifications

Absolute Maximum Ratings *)

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Data Privacy

Document Warranty

Limitation of Liability

Copyright Notice

Technology Licenses

Environmental Protection

REACH, RoHS and WEEE

Table of contents

Absolute Maximum Ratings ^*)