Table of Contents
Overview
The Trenz Electronic TE0745 is an industrial-grade SoC module integrating a Xilinx Zynq-7 (Z-7030, Z-7035 or Z-7045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.
Block Diagram
Figure 1: TE0745-02 Block Diagram
Main Components
Figure 2: TE0745-02 SoC module
- Xilinx ZYNQ-7000 family SoC, U1
- 256 Mbit Quad SPI Flash Memory Micron N25Q256A, U12
- Reference clock signal oscillator SiTime SiT8008BI @33.333 MHz, U12
- Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U9
- Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width), U3
- TI TPS51206 DDR3 Memory Termination Regulator with buffered reference votlage VTTREF, U18
- Intersil ISL12020MIRZ Real-Time-Clock, U24
- TI TCA9517 Level-shifting I²C bus repeater, U17
- LED D2 red
- LED D1 green
- Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16 Bit Word-Width), U5
- Altera Enpirion EN63A0QI 12A DCDC PowerSoC @1.0V (VCCINT), U4
- TI TPS74401RGW LDO DC/DC regulator @1.2V (MGTAVTT), U8
- TI TPS72018DRVR LDO DC/DC regulator @1.8V (MGTAUX), U6
- TI TPS74401RGW LDO DC/DC regulator @1.0V (MGTAVCC), U11
- Silicon Labs Si5338A I²C Programmable Quad Clock Generator, U13
- Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
- Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
- 256 Mbit Quad SPI Flash Memory (Micron N25Q256A, U14
- Microchip USB3320 USB Transceiver PHY , U32
- Reference clock signal oscillator SiTime SiT8008BI @52.000 MHz, U33
- Microchip 24AA025E48 EEPROM for MAC Address
- Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
Key Features
Industrial-grade Xilinx Zynq-7000 (Z-7030, Z-7035, Z-7045) SoM
- Rugged for shock and high vibration
- 10/100/1000 Mbps Ethernet transceiver PHY
- EEPROM for storing Ethernet MAC Address
- 16-Bit wide 1GB DDR3 SDRAM
- 32 MByte QSPI flash memory
- Programmable clock generator
- Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
- 132 FPGA I/Os (65 LVDS pairs possible) and 14 PS MIO available on B2B connectors
- 8 GTX (high-performance transceiver) lanes (Z-7030: 4 GTX lanes)
- USB 2.0 OTG high-speed PHY
- On-board high-efficiency DC-DC converters
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Temperature compensated RTC (real-time clock)
- User LED
- Evenly-spread supply pins for good signal integrity
Additional assembly options are available for cost or performance optimization upon request.
Initial Delivery State
Storage device name | Content | Notes |
|---|---|---|
24AA025E48 EEPROM | User content not programmed | Valid MAC Address from manufacturer. |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
eFUSE USER | Not programmed | - |
eFUSE Security | Not programmed | - |
| Si5338 OTP NVM | Default settings pre programmed | OTP not reprogrammable after delivery from factory |
Table 1: Initial delivery state
Signals, Interfaces and Pins
Board to Board (B2B) I/O's
The Board to Board connectors are high-speed hermaphroditic stacking strips and provide a modular interface to the SoC's PL and PS I/O's.
The connector supports single ended and differential signaling as the I/O's are usable as LVDS-pairs.
The I/O signals are routed from the SoC's PL banks as LVDS-pairs to the B2B connector.
| Bank | Type | B2B Connector | I/O signal count | LVDS-pairs count | VCCO bank voltage | Notes |
|---|---|---|---|---|---|---|
| 12 | HR | J1 | 50 | 24 | user (VCCIO_12) | supported voltages from 1.2V to 3.3V |
| 13 | HR | J1 | 50 | 24 | user (VCCIO_13) | supported voltages from 1.2V to 3.3V |
| 34 | HR | J2 | 50 | 24 | user (VCCIO_34) | supported voltages from 1.2V to 3.3V |
| 35 | HR | J2 | 50 | 24 | user (VCCIO_35) | supported voltages from 1.2V to 3.3V |
| 500 | MIO | J2 | 5 | - | 1.8V | - |
| 501 | MIO | J3 | 12 | - | 1.8V | - |
Table 2: B2B connector pin-outs of available PL and PS banks of the SoC module
For detailed information about the pin out, please refer to the Pin-out Table.
MGT lanes
The B2B connector J1 and J2 provide also access to the MGT-banks of the SoC module. There are 8 high-speed data links (Xilinx GTX transceiver) available composed as differential signaling pairs for both directions (RX/TX), means from module to base-board and vice versa.
The MGT-banks have also clock input-pins which are exposed to the B2B connector J3. Following MGT-lanes are available on the B2B connectors:
| Bank | I/O signal count | LVDS-pairs count | MGT-lanes count (RX/TX LVDS-pairs) | bank's reference clock inputs (LVDS-pairs) | Notes |
|---|---|---|---|---|---|
| Bank 111 | 20 | 10 | 4 | 1 reference clock signal (MGT_CLK3) from programmable quad PLL clock generator U16 to bank's pins AA6/AA5. 1 reference clock signal (MGT_CLK2) from B2B connector J3 (pins J3-81/J3-83) to bank's pins W6/W5. | - |
| Bank 112 | 20 | 10 | 4 | 1 reference clock signal (MGT_CLK1) from programmable quad PLL clock generator U16 to bank's pins U6/U5. 1 reference clock signal (MGT_CLK0) from B2B connector J3 (pins J3-75/J3-77) to bank's pins R6/R5. | - |
Table 3: B2B connector pin-outs of available MGT-lanes of the SoC module
Interface on B2B connectors
The B2B connector provides further interfaces like 'JTAG' and 'I²C' to the System Controller CPLD:
| Interfaces | I/O signal count | pin schematic names / B2B pins | connected with | Notes |
|---|---|---|---|---|
| JTAG | 5 | TMS, pin J1-144 TDI, pin J1-142 TDO, pin J1-145 TCK, pin J1-143 JTAG_EN, pin J1-148 | SC CPLD, bank 0 | JTAG_EN pin in B2B connector J1-148 should be kept low or grounded for normal operation! At normal operation the JTAG-signals will be forwarded to the SoC module. Else the JTAG_EN pin must be high or open to update the CPLD firmware via JTAG-interface. VCCIO: PS_3.3V |
| I²C | 2 | I2C_33_SCL, pin J2-119 I2C_33_SDA, pin J2-121 | RTC, U24 SC CPLD, U2 MAC Address EEPROM, U23 Zynq-module, U1 Quad programmable PLL clock generator, U16 | The I²C-interface of the RTC U24 (pin 12: SCL, pin 11: SDA) and the B2B-connector J2 are operating with the reference voltage PS_3.3V. Following component's I²C-interfaces are operating with the reference voltage PS_1.8V (voltage level shifting 3.3V ↔ 1.8V via I²C bus repeater U17): SC CPLD U2, bank 2, pins 16 (SDA), 17 (SCL) MAC Address EEPROM U23, pins 1 (SCL), 3 (SDA) Zynq-chip U1, bank 500 (MIO0), pins A25 (SCL), B26 (SDA) Quad programmable PLL clock generator U16: pins 12 (SCL), 19 (SDA) Component's I²C Addresses: RTC: 0x6F RTC RAM: 0x57 MAC Address EEPROM: 0x53 Quad programmable PLL clock generator: 0x70 |
| control lines | 5 | RST_IN_N, pin J2-131 | SC CPLD bank 0, pins 25; Reset Circuit U41, pin 3 | Low-active Power-On reset-pin, controls POR_B-signal (bank 500, pin C23) of Zynq-chip. |
| PS_SRST, pin J2-152 | SC CPLD bank 2, pin 12; Zynq-chip bank 501, pin A22 | Low-active system-reset pin of Zynq-chip. | ||
| BOOTMODE, pin J2-133 | Zynq-chip bank 500, pin F24 | Control line which sets in conjunction with signal 'BOOTMODE1' the boot source of the Zynq-chip. See section "Boot Modes". | ||
| PWR_PL_OK, pin J2-135 | SC CPLD bank 0, pin 27; PG-signal DCDC-converter U8, pin 9 | Indicates stable state of PL supply voltage (low-active). | ||
| PWR_PS_OK, pin J2-139 | SC CPLD bank 0, pin 28; PG-signal DCDC-converter U31, pin 2 | Indicates stable state of PS supply voltage (low-active). |
Table 4: B2B connector pin-outs of available interfaces
System Controller CPLD
Special purpose pins are connected to System Controller CPLD and have following default configuration:
| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| EN1 | Input | Power Enable | No hard wired function on PCB, when forced low pulls POR_B low to emulate power on reset. |
| PGOOD | Output | Power Good | Active high when all on-module power supplies are working properly. |
| NOSEQ | - | - | No function. |
| RESIN | Input | Reset | Active low reset, gated to POR_B. |
| JTAGEN | Input | JTAG Select | Low for normal operation. |
LEDs
| LED | Color | Connected to | Description and Notes |
|---|---|---|---|
D2 | Green | DONE | Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL is configured. This LED will not operate if the SC can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module. |
D3 | Red | SC | System main status LED. |
D4 | Green | MIO7 | User controlled, default OFF (when PS7 has not been booted). |
Default MIO Mapping
| MIO | Function | B2B Pin | Notes | MIO | Function | B2B Pin | Notes | |
|---|---|---|---|---|---|---|---|---|
| 0 | GPIO | JM1-87 | B2B | 16..27 | ETH0 | - | RGMII | |
| 1 | QSPI0 | - | SPI Flash-CS | 28..39 | USB0 | - | ULPI | |
| 2 | QSPI0 | - | SPI Flash-DQ0 | 40 | SDIO0 | JM1-27 | B2B | |
| 3 | QSPI0 | - | SPI Flash-DQ1 | 41 | SDIO0 | JM1-25 | B2B | |
| 4 | QSPI0 | - | SPI Flash-DQ2 | 42 | SDIO0 | JM1-23 | B2B | |
| 5 | QSPI0 | - | SPI Flash-DQ3 | 43 | SDIO0 | JM1-21 | B2B | |
| 6 | QSPI0 | - | SPI Flash-SCK | 44 | SDIO0 | JM1-19 | B2B | |
| 7 | GPIO | - | Green LED D4 | 45 | SDIO0 | JM1-17 | B2B | |
| 8 | QSPI0 | - | SPI Flash-SCKFB | 46 | GPIO | - | Ethernet PHY LED2 INTn Signal. | |
| 9 | JM1-91 | B2B | 47 | GPIO | - | RTC Interrupt | ||
| 10 | JM1-95 | B2B | 48 | I2C1 | - | SCL on-board I2C | ||
| 11 | JM1-93 | B2B | 49 | I2C1 | - | SDA on-board I2C | ||
| 12 | JM1-99 | B2B | 50 | GPIO | - | ETH0 Reset | ||
| 13 | JM1-97 | B2B | 51 | GPIO | - | USB Reset | ||
| 14 | UART0 | JM1-92 | B2B | 52 | ETH0 | - | MDC | |
| 15 | UART0 | JM1-85 | B2B | 53 | ETH0 | - | MDIO |
Gigabit Ethernet
On board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII Interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U9), the 125MHz output clock is connected to IN5 of the PLL chip (U10).
Ethernet PHY connection
| PHY Pin | ZYNQ PS | ZYNQ PL | Notes |
|---|---|---|---|
| MDC/MDIO | MIO52, MIO53 | - | - |
| LED0 | - | J3 | Can be routed via PL to any free PL I/O pin in B2B connector. |
| LED1 | - | K8 | Can be routed via PL to any free PL I/O pin in B2B connector. This LED is connected to PL via level-shifter implemented in system controller CPLD. |
| LED2/Interrupt | MIO46 | - | - |
| CONFIG | - | - | By default the PHY address is strapped to 0x00, alternate configuration is possible. |
| RESETn | MIO50 | - | - |
| RGMII | MIO16..MIO27 | - | - |
| SGMII | - | - | on B2B. |
| MDI | - | - | on B2B. |
USB Interface
USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V. The reference clock input of the PHY is supplied from an on-board 25 MHz oscillator (U15).
USB PHY connection
| PHY Pin | ZYNQ Pin | B2B Name | Notes |
|---|---|---|---|
| ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY. |
| REFCLK | - | - | 52MHz from on board oscillator (U15). |
| REFSEL[0..2] | - | - | Reference clock frequency select, all set to GND selects 52MHz. |
| RESETB | MIO51 | - | Active low reset. |
| CLKOUT | MIO36 | - | Connected to 1.8V, selects reference clock operation mode. |
| DP, DM | - | OTG_D_P, OTG_D_N | USB data lines. |
| CPEN | - | VBUS_V_EN | External USB power switch active high enable signal. |
| VBUS | - | USB_VBUS | Connect to USB VBUS via a series of resistors, see reference schematics. |
| ID | - | OTG_ID | For an A-Device connect to ground, for a B-Device left floating. |
The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
Boot Modes
By default the TE-0715 supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.
MODE Signal State | Boot Mode |
|---|---|
High or open | QSPI |
Low or ground | SD Card |
On-board Peripherals
Processing System (PS) Peripherals
| Name | IC | ID | PS7 | MIO | Notes |
|---|---|---|---|---|---|
| SPI Flash | S25FL256SAGBHI20 | U14 | QSPI0 | MIO1..MIO6 | |
| EEPROM I2C | 24AA025E48 | U19 | I2C1 | MIO48, MIO49 | EEPROM for MAC Address. |
| RTC | ISL2020 | U16 | I2C1 | MIO48, MIO49 | Temperature compensated RTC. |
| RTC Interrupt | ISL2020 | U16 | GPIO | MIO47 | Real Time Clock Interrupt. |
| Clock PLL | Si5338 | U10 | I2C1 | MIO48, MIO49 | Low jitter phase locked loop. |
| LED | - | D4 | GPIO | MIO7 | |
| USB | USB3320 | U6 | USB0 | MIO28..MIO39 | |
| USB Reset | - | - | GPIO | MIO51 | |
| Ethernet | 88E1512 | U7 | ETH0 | MIO16..MIO27 | |
| Ethernet Reset | - | - | GPIO | MIO50 |
Clocking
| Clock | Frequency | IC | FPGA | Notes |
|---|---|---|---|---|
PS CLK | 33.3333 MHz | U11 | PS_CLK | PS subsystem main clock. |
ETH PHY reference | 25 MHz | U9 | - | - |
USB PHY reference | 52 MHz | U15 | - | - |
PLL reference | 25 MHz | U18 | - | - |
GT REFCLK0 | - | B2B | U9/V9 | Externally supplied from baseboard. |
GT REFCLK1 | 125 MHz | U10 Si5338 | U5/V5 | Default clock is 125 MHz. |
RTC - Real Time Clock
An temperature compensated Intersil ISL12020M is used for Real Time Clock (U16). Battery voltage must be supplied to the module from the main board. Battery backed registers can be accessed over I2C bus at slave address of 0x6F. General purpose RAM is at I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device.
PLL - Phase-Locked Loop
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70.
PLL connection
| I/O | Default Frequency | Notes |
|---|---|---|
IN1/IN2 | Externally supplied | Needs decoupling on base board. |
IN3 | 25MHz | Fixed input clock. |
IN4 | - | - |
IN5/IN6 | 125MHz | Ethernet PHY output clock. |
CLK0 | - | Not used, disabled. |
CLK1 | - | Not used, disabled. |
CLK2 A/B | 125MHz | MGT reference clock 1. |
CLK3A | - | Bank 34 clock input, default disabled, User clock. |
CLK3B | - | Not used, disabled. |
MAC Address EEPROM
A Microchip 24AA025E48 EEPROM (U19) is used which contains a globally unique 48-bit node address, that is compatible with EUI-48(TM) and EUI-64(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50.
Power and Power-On Sequence
TE0715-xx-30 has several HP banks on B2B connectors. Those banks have maximum voltage tolerance of 1.8V. Please check special instructions for the baseboard to be used with TE0715-xx-30.
Power Supply
Power supply with minimum current capability of 3A for system startup is recommended.
Power Consumption
| Power Input Pin | Max Current |
|---|---|
| VIN | TBD* |
| 3.3VIN | TBD* |
* TBD - To Be Determined soon with reference design setup.
Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V supplies the power consumption (and heat dissipation) will rise due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises). Typical module power consumption is between 2-3W.
Power-On Sequence
For highest efficiency of on board DC/DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.
It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10 and 12, meaning that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS187 (for XC7Z015) or DS191 (for XC7Z030) for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0715 module.
Power Rails
Voltages on B2B Connectors | B2B JM1 Pin | B2B JM2-Pin | Input/ Output | Note |
|---|---|---|---|---|
| VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage. |
| 3.3VIN | 13, 15 | - | Input | Supply voltage. |
| VCCIO13 | 9, 11 | - | Input | High range bank voltage. |
| VCCIO34 | - | 5 | Input | TE0715-xx-15: high range bank voltage. TE0715-xx-30: high performance bank voltage. |
| VCCIO35 | - | 7, 9 | Input | TE0715-xx-15: high range bank voltage. TE0715-xx-30: high performance bank voltage. |
| VBAT_IN | 79 | - | Input | RTC battery-buffer supply voltage. |
| 3.3V | - | 10, 12 | Output | Internal 3.3V voltage level. |
| 1.8V | 39 | - | Output | Internal 1.8V voltage level. |
| DDR_PWR | - | 19 | Output | Internal 1.5V or 1.35V voltage level, depends on revision. |
| VREF_JTAG | 91 | Output | JTAG reference voltage (3.3V). |
Bank Voltages
Bank | Schematic Name | Voltage | TE0715-xx-15 | TE0715-xx-30 |
|---|---|---|---|---|
| 500 | VCCO_MIO0_500 | 3.3V | - | - |
| 501 | VCCO_MIO1_501 | 1.8V | - | - |
| 502 | VCCO_DDR_502 | 1.5V | - | - |
| 0 Config | VCCO_0 | 3.3V | - | - |
| 13 HR | VCCO_13 | User | HR: 1.2V to 3.3V | HR: 1.2V to 3.3V |
| 34 HR/HP | VCCO_34 | User | HR: 1.2V to 3.3V | HP: 1.2V to 1.8V |
| 35 HR/HP | VCCO_35 | User | HR: 1.2V to 3.3V | HP: 1.2V to 1.8V |
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes |
|---|---|---|---|---|
VIN supply voltage | -0.3 | 6.0 | V | - |
3.3VIN supply voltage | -0.4 | 3.6 | V | - |
| VBAT supply voltage | -1 | 6.0 | V | - |
| PL IO bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | - |
PL IO bank supply voltage for HP I/O banks (VCCO) | -0.5 | 2.0 | V | TE0715-xx-15 does not have HP banks. |
| I/O input voltage for HR I/O banks | -0.4 | VCCO_X+0.55 | V | - |
| I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | TE0715-xx-15 does not have HP banks. |
| GT receiver (RXP/RXN) and transmitter (TXP/TXN) | -0.5 | 1.26 | V | - |
Voltage on module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal. |
Storage temperature | -40 | +85 | °C | - |
| Storage temperature without the ISL12020MIRZ | -55 | +100 | °C | - |
Assembly variants for higher storage temperature range are available on request.
Recommended Operating Conditions
| Parameter | Min | Max | Units | Notes | Reference Document |
|---|---|---|---|---|---|
| VIN supply voltage | 2.5 | 5.5 | V | ||
| 3.3VIN supply voltage | 3.135 | 3.465 | V | ||
| VBAT_IN supply voltage | 2.7 | 5.5 | V | ||
PL I/O bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS191 | |
PL I/O bank supply voltage for HP I/O banks (VCCO) | 1.14 | 1.89 | V | TE0715-xx-15 does not have HP banks | Xilinx datasheet DS191 |
| I/O input voltage for HR I/O banks | (*) | (*) | V | (*) Check datasheet | Xilinx datasheet DS191 or DS187 |
| I/O input voltage for HP I/O banks | (*) | (*) | V | TE0715-xx-15 does not have HP banks (*) Check datasheet | Xilinx datasheet DS191 |
| Voltage on Module JTAG pins | 3.135 | 3.465 | V | VCCO_0 is 3.3 V nominal |
B2B connectors
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Technical Specifications
Absolute Maximum Ratings
Recommended Operating Conditions
Physical Dimensions
Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
Mating height with standard connectors: 4mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
All dimensions are given in millimeters.
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Weight
.. g - Plain module
.. g - Set of bolts and nuts
Revision History
Hardware Revision History
| Date | Revision | Notes | Link to PCN | Documentation Link |
|---|---|---|---|---|
| 2016-10-11 | 02 | Production release | TE0745-02 | |
| 2016-04-18 | 01 | Prototypes | TE0745-01 |
Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Document Change History
| Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-02-05 | Jan Kumann | Initial document. |
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WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
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