Table of Contents
Overview
The Trenz Electronic TEC0330 FPGA board has a PCI Express card form factor and is containing the Xilinx FPGA-module Virtex-7 XC7VX330T. This high-end FPGA-module is optimized for system performance and is used in applications with high demands on system resources.
This board is designed to fit in computing systems with PCI Express x8 slots (PCIe 2.0 or higher) and has also a SO-DIMM socket to extend the board with DDR3-RAM.
The FMC (FPGA Mezzanine Card) connector provides a high pin count (HPC) and is as an ANSI/VITA 57.1 standard a modular interface to the FPGA for mezzanine expansion cards. Further connectors provide JTAG-interfaces to the FPGA-module and to the on-board System Controller CPLD together with access to high-speed data lanes composed of differential signaling pairs.
Block Diagram
Figure 1: TEC0330-03 Block Diagram
Main Components
Figure 2: FPGA board TEC0330-03
TEC0330-03:
- PCIe x8 connector J1
- FPGA JTAG connector J9
- User button S2
- SO-DIMM socket U2
- Xilinx Virtex-7 XC7VX330T-2FFG1157C FPGA-module U1
- ANSI/VITA 57.1 compliant FMC HPC Connector J2
- SMA coaxial connector for external clock input J3
- CPLD JTAG connector J8
- I²C-connector for LT LTM4676 Step-down DC/DC regulator J10
- IDC header for access to 5 x high-speed data lanes (LVDS-pairs) J7
- 4-Wire PWM fan connector J4
- 6-pin 12V power connector J5
- Reference clock generator (RAKON P5146, U11) @10.0 MHz
- LDO DC/DC regulator (TI TPS74901RGWR, U21) @3.3V (LMK_3V3)
- 256 Mbit Quad SPI Flash Memory (Micron N25Q256A, U12)
- Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM)
- System Controller CPLD (Lattice Semiconductor MachXO2-1200HC, U5)
- Ultra low jitter clock synthesizer (TI LMK04828B, U9)
- Step-down DC/DC regulator (LT LTM4676, U4) @1.0V
- Step-down DC/DC regulator (LT LTM4676, U3) @1.5V (VCC1V5), @4.0V
- I²C Programmable Quad Clock Generator (Silicon Labs Si5338A, U13)
- 4A PowerSoC DC-DC converter (Altera EN6347QI, U20) @1.8V
- LDO DC/DC regulator (TI TPS74401RGW, U18) @1.0V (MGTAVCC_FPGA)
- LDO DC/DC regulator (TI TPS74401RGW, U17) @1.2V (MGTAVTT_FPGA)
- 4A PowerSoC DC-DC converter (Altera EN6347QI, U15) @3.3V (3V3FMC)
- 4A PowerSoC DC-DC converter (Altera EN6347QI, U7) @1.8V (FMC_VADJ)
Key Features
- Xilinx Virtex-7 FPGA module XC7VX330T-2FFG1157C (commercial temperature range)
- FPGA board designed as PCIe card is fitting in PCI Express x8 slots (PCIe 2.0 or higher)
- FMC High Pin Count (HPC) Connector
- 8 MGT-lanes available on PCIe interface
- DDR3 SO-DIMM Socket
- 256-Mbit (32-MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
- FPGA
- JTAG port (SPI indirect (Bus width x4))
- External Clock Input via SMA coaxial connector
- 28 GTH transceivers, each with up to 13.1 Gbit/s data transmission rate
- FPGA configuration through:
- JTAG-connector
- SPI Flash memory
- Programmable quad PLL clock generator
- TI LMK04828B ultra low-noise high-performance clock synthesizer (jitter cleaner)
- On-board high-efficiency DC-DC converters
- Up to 202 FPGA I/O pins available on FMC connector (up to 101 LVDS-pairs possible)
- System management and power sequencing
- AES bit-stream encryption
- eFUSE bit-stream encryption
Additional assembly options are available for cost or performance optimization upon request.
Initial Delivery State
Storage device name | Content | Notes |
---|---|---|
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor. |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | Demo design | - |
eFUSE USER | Not programmed | - |
eFUSE Security | Not programmed | - |
Table 1: Initial delivery state
Signals, Interfaces and Pins
FMC Connector
The FMC (FPGA Mezzanine Card) connector (J2) with high pin count (HPC) provides as an ANSI/VITA 57.1 standard a modular interface to the FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
The connector supports single ended (with severeal VCCIO voltages available) and differential signaling as the I/O's are usable as LVDS-pairs.
The I/O signals are routed from the FPGA banks as LVDS-pairs to the connector:
Bank | I/O Signal count | LVDS-pairs count | VCCO bank Voltage | Notes |
---|---|---|---|---|
Bank 19 | 92 | 46 | 1.8V | - |
Bank 39 | 42 | 21 | VIO_B_FMC | bank voltage VIO_B_FMC must be supplied by FMC connector pins J2-J39, J2-K40 bank's VREF-pin (VREF_B_M2C) available on FMC connector pin J2-K1 (extern reference voltage) |
Bank 37 | 34 | 17 | 1.8V | bank's VREF-pin (VREF_A_M2C) available on FMC connector pin J2-H1 (extern reference voltage) |
Bank 38 | 34 | 17 | 1.8V | bank's VREF-pin (VREF_A_M2C) available on FMC connector pin J2-H1 (extern reference voltage) |
Table 2: FMC connector pin-outs of available logic banks of the FPGA.
The FMC connector provides also access to the MGT-banks of the FPGA. There are 10 high-speed data links (Xilinx GTH transceiver) available composed as differential signaling pairs for both directions (RX/TX), means from card to (mezzanine) module and vice versa.
The MGT-banks have also clock input-pins which are exposed to the FMC connector. Following MGT-lanes are available on the FMC connector:
Bank | I/O signal count | LVDS-pairs count | MGT-lanes count (RX/TX LVDS-pairs) | bank's reference clock (LVDS-pair) | Notes |
---|---|---|---|---|---|
Bank 116 | 10 | 5 | 2 | 1 clock-signal from clock synthesizer U9 to bank's pins T6/T5 | - |
Bank 117 | 20 | 10 | 4 | 2 clock-signals from clock FMC connector 'GBTCLK0_M2C' and 'GBTCLK1_M2C' (pins J2-D4/J2-D5 and J2-B20/J2-B21) to bank's pins M6/M5 and P6/P5 | - |
Bank 118 | 20 | 10 | 4 | 1 reference clock from clock synthesizer U9 to bank's pins F6/F5 1 reference clock from programmable quad PLL clock generator U13 to bank's pins H6/H5 | - |
Table 3: FMC connector pin-outs of available MGT-lanes of the FPGA
The FMC connector provides further interfaces like 'JTAG' and 'I²C' to the System Controller CPLD:
Interfaces | I/O signal count | pin schematic names / FMC pins | connected with | Notes |
---|---|---|---|---|
JTAG | 5 | FMC_TRST, pin D34 FMC_TCK, pin D29 FMC_TMS, pin D33 FMC_TDI, pin D30 FMC_TDO, pin D31 | SC CPLD, bank 2 | VCCIO: 3V3PCI |
I²C | 2 | FMC_SCL, pin C30 FMC_SDA, pin C31 | SC CPLD, bank 2 | VCCIO: 3V3PCI I²C-lines 3V3PCI pulled-up |
control lines | 3 | FMC_PRSNT_M2C_L, pin H2 FMC_PG_C2M, pin D1 (3V3FMC pull-up) FMC_PG_M2C, pin F1 (3V3FMC pull-up) | SC CPLD, bank 1 | 'PG' = 'Power Good'-signal 'C2M' = carrier to (mezzanine) module 'M2C' = (mezzanine) module to carrier internal System Controller CPLD signal assignment: 'FEX_0_N' <= 'FMC_PG_M2C' 'FMC_PG_C2M' <= 'FMC_PRSNT_M2C_L' |
Table 4: FMC connector pin-outs of available interfaces to the System Controller CPLD
The FMC connector provides pins for reference clock input to the FPGA banks:
clock schematic name | I/O signal count | LVDS-pairs count | FMC connector pins | connected with | Notes |
---|---|---|---|---|---|
CLK0 | 2 | 1 | H4/H5 | bank 17, pins R28/R29 | - |
CLK1 | 2 | 1 | G3/G2 | bank 17, pins P29/P30 | - |
CLK2 | 2 | 1 | K4/K5 | bank 18, pins G31/G31 | - |
CLK3 | 2 | 1 | J2/J3 | bank 18, pins H29/H30 | - |
Table 5: FMC connector pin-outs for reference clock input
Several VCCIO voltages are available on the FMC connector to operate the I/O's in order of the intended purpose:
VCCIO schematic name | max current | FMC connector pins | Notes |
---|---|---|---|
12V | 1A | C35/C37 | extern supplied 12V |
3V3PCI | 20mA | D32 | supplied by PCIe interface |
3V3FMC | 3A | D36/D38/D40/C39 | supplied by DC/DC converter U15 |
VIO_B_FMC | extern supply | J39/K40 | extern supplied VCCO to HB FPGA Bank 39 |
FMC_VADJ | 4A | H40/G39/F40/E39 | fixed to 1.8V, supplied by DC/DC converter U7 |
Table 6: Available VCCIO voltages on FMC connector
PCI Express Interface
The TEC0330 FPGA board is also a PCI Express card designed to fit in computing systems with PCI Express x8 slots (PCIe 2.0 or higher) and is PCIe Gen. 2 capable.
8 MGT-lanes are routed to the PCIe interface composed of RX/TX LVDS-pairs for each lane:
Bank | I/O signal count | LVDS-pairs count | MGT-lanes count | bank's reference clock (LVDS-pair) | Notes |
---|---|---|---|---|---|
FPGA bank 114 | 16 | 8 | 4 | - | - |
FPGA bank 115 | 18 | 9 | 4 | 1 reference clock from programmable quad PLL clock generator 1 reference clock from PCIe interface J1 to bank's pins AD6/AD5 | - |
Table 7: MGT-lanes available on PCIe interface
JTAG Interfaces
JTAG interfaces are accessible on the TEC0330 board to program the FPGA-module or the System Controller CPLD:
JTAG interface | JTAG signals schematic name | JTAG connector pins | connected with |
---|---|---|---|
CPLD JTAG VCCIO: 3V3PCI Connector: J8 | CPLD_JTAG_TMS | J8-1 | SC CPLD, bank 0, pin 90 |
CPLD_JTAG_TDI | J8-2 | SC CPLD, bank 0, pin 94 | |
CPLD_JTAG_TDO | J8-3 | SC CPLD, bank 0, pin 95 | |
CPLD_JTAG_TCK | J8-4 | SC CPLD, bank 0, pin 91 | |
FPGA JTAG VCCIO: 1V8 Connector: J9 | FPTA_JTAG_TMS | J9-4 | FPGA, bank 0, pin N9 |
FPTA_JTAG_TCK | J9-6 | FPGA, bank 0, pin M8 | |
FPTA_JTAG_TDO | J9-8 | FPGA, bank 0, pin N8 | |
FPTA_JTAG_TDI | J9-10 | FPGA, bank 0, pin L8 | |
FMC JTAG VCCIO: 3.3VPCI Connector: J2 | FMC_TRST | J2-D34 | SC CPLD, bank 2, pin 36 |
FMC_TCK | J2-D29 | SC CPLD, bank 2, pin 27 | |
FMC_TMS | J2-D33 | SC CPLD, bank 2, pin 28 | |
FMC_TDI | J2-D30 | SC CPLD, bank 2, pin 31 | |
FMC_TDO | J2-D31 | SC CPLD, bank 2, pin 32 |
Table 8: JTAG Interface on TEC0330 board
SO-DIMM Socket for DDR3-RAM
The TEC0330 board can be upgraded with a DDR3 SO-DIMM (204-pin). For this purpose the board is equipped with a 204-pin SO-DIMM socket U2. The DDR3 memory interface is routed to the FPGA banks 34, 35 and 36.
The reference clock signal for the DDR3 interface is generated by the quad programmable reference clock U13 and is applied to bank 35.
There is also a I²C-interface between the System Controller CPLD and the DDR3 memory interface:
Interface signals schematic name | designated CPLD pins | DDR3 memory interface pins |
---|---|---|
DDR3_SDA | bank 2, pin 48 | pin 200 (3V3PCI pull-up) |
DDR3_SCL | bank 2, pin 49 | pin 202 (3V3PCI pull-up) |
Table 9: I²C-interface between SC CPLD and DDR3 memory
System Controller CPLD
The System Controller CPLD is the central system management unit that provides numerous interfaces between the on-board peripherals and to the FPGA-module. The signals routed to the CPLD will be linked by the logic implemented in the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. So some interfaces between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence, the proper programing of the FPGA-module and to display its programming state.
CPLD bank | CPLD bank's VCCIO |
---|---|
0 | 3V3PCI |
1 | 3V3PCI |
2 | 3V3PCI |
3 | 1V8 |
Table 10: VCCIO voltages of CPLD banks
Following table describes the interfaces and functionalities established by the CPLD, which weren't discussed elsewhere in this TRM:
CPLD functionality | interface | designated CPLD pins | pins connected with | Note |
---|---|---|---|---|
FPGA I²C connection between on-board peripherals and FPGA-module | I²C | FPGA_IIC_SDA, pin 24 FPGA_IIC_SCL, pin 25 FPGA_IIC_OE, pin 19 | FPGA bank 16, pin V29 FPGA bank 16, pin W29 FPGA bank 16, pin W26 | VCCIO: 1V8 all lines 1V8 pulled-up Following I²C-interfaces of are linked to the I²C-lines of 'FPGA_IIC' for data-transmission between the FPGA-module and on-board peripherals:
Note: 'FPGA_IIC_OE' must kept high for I²C-operation. For I²C-addresses refer to the data sheets of the components. |
user I/O's external LVDS-pairs | 10 I/O's 5 x differential signaling pairs | EX0_P ... EX4_P EX0_N ... EX4_N | IDC header J7 | pins can also be used for single-ended signaling |
user I/O's internal LVDS-pairs | 13 I/O's 6 x differential signaling pairs | FEX0_P ... FEX5_P FEX0_N ... FEX5_N FEX_DIR (single-ended I/O) | FPGA bank 18 | VCCIO: 1V8 pins can also be used for single-ended signaling FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and from clock synthesizer U9 (FCLK) internal signal assignment: 'FEX_DIR' <= 'FMC_PRSNT_M2C_L' |
FPGA programing control and state | 2 I/O's | DONE, pin 7 PROGRAM_B, pin 8 | FPGA bank 0, pin V8 FPGA bank 0, pin U8 | VCCIO: 1V8 |
I²C-interface to quad programmable PLL clock generator | I²C | PLL_SCL, pin 14 PLL_SDA, pin 15 | U13, pin 12 U13, pin 19 | VCCIO: 1V8 only 'PLL_SDA' 1V8 pulled-up |
Fan PWM control J4 | 2 I/O's | F1SENSE, pin 99 F1PWM, pin 98 | J4-3 (low-active signal) J4-4 | internal signal assignment: 'FEX_5_P' <= 'F1SENSE' 'FEX_5_N' => 'F1PWM' |
Button S2 | 1 I/O | BUTTON, pin 77 | switch S2 | functionality depends on CPLD-firmware, activating pin 'PROGRAM_B' (low-active) and 'LED1' at standard configuration |
LED1 | 1 I/O | LED1, pin 76 | LED D1 (green) | fast blinking, if FPGA not programmed internal signal assignment: 'LED1' <= 'Button S2' or 'FEX0_P' |
PCIe control line RESET_B | 1 I/O | 'PCIE_RSTB', pin 37 | PCIe connector J1-A11 (33R serial resistor) | internal signal assignment: 'FEX_4_N' <= 'PCIE_RSTB' |
Control Interface to clock synthesizer U9 (TI LMK04828B) | SPI (3 I/O's), 4 I/O's | CLK_SYNTH_SDIO, pin 75 CLK_SYNTH_SCK, pin 74 CLK_SYNTH_RESET, pin 54 CLK_SYNTH_CS, pin 53 CLK_SYNTH_SYNC, pin 52 LMK_STAT0, pin 62 LMK_STAT1, pin 63 | U9, pin 20 U9, pin 19 U9, pin 5 U9, pin 18 U9, pin 6 U9, pin 31 U9, pin 48 | 'CLK_SYNTH_SDIO' 3V3PCI pulled-up internal signal assignment: 'LMK_SCK' <= 'FEX_1_P' 'LMK_SDIO' <= 'FEX_1_N' 'LMK_CS' <= 'FEX_3_P' 'LMK_SYNC' <= 'FEX_3_N' LMK_RESET <= 'FEX_4_P' 'FEX_2_P' => 'LMK_SDIO' (FEX_2_N must be 0) 'LMK_STAT0' and 'LMK_STAT1' signals will not be evaluated. |
Control Interface to DC/DC converters U3 and U4 (both LT LTM4676) | I²C (2 I/O's), 2 I/O's | LTM_SCL, pin 67 LTM_SDA, pin 66 LTM1_ALERT, pin 65 LTM2_ALERT, pin 64 | U4, pin E6 and U3, pin E6 U4, pin D6 and U3, pin D6 U4, pin E5 U3, pin E5 | all lines 3V3 pulled-up LTM I²C-interface also accessible trough header J10 LTM1- and LTM2-Alert signals will not be evaluated. |
power-on sequence and monitoring | 6 I/O's | EN_1V8, pin 58 PG_1V8, pin 59 EN_FMC_VADJ, pin 60 PG_FMC_VADJ, pin 61 EN_3V3, pin 51 PG_3V3, pin 57 | U20, pin 27 U20, pin 28 U7, pin 27 U7, pin 28 U15, pin 27 U15, pin 28 | The effective sequencing of the supply voltages depends on the currently programmed CPLD firmware. EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up. PG-signals will not be evaluated. |
Table 11: System Controller CPLD functionalities
Clocking
The TEC0330 FPGA board has a sophisticated clock generation and conditioning system to meet the requirements of the Xilinx Virtex-7 GTH units with data transmission rates up to 13.1 Gb/s.
Clock sources
The board has the following sources to be provided with extern reference clock signals and on-board clock oscillators:
clock generator sources | Schematic Name | Frequency | clock input destination | Notes |
---|---|---|---|---|
SMA coaxial connector, J3 | CLK_SYNTH_CLKIN0_P, CLK_SYNTH_CLKIN0_N (GND) | user | clock synthesizer U9, pins 37/38 | - |
RAKON P5146LF oscillator, U11 | - | 10.0 MHz | clock synthesizer U9, pins 43/44 | - |
SiTime SiT8208 oscillator, U14 | CLK_25MHz | 25.0 MHz | quad PLL clock Generator U13, pin 3 | - |
FMC connector J2, pins H4/H5 | CLK0_P, CLK0_N | user | FPGA bank 17, pins R28/R29 | - |
FMC connector J2, pins G2/G3 | CLK1_P, CLK1_N | user | FPGA bank 17, pins P29/P30 | - |
FMC connector J2, pins K4/K5 | CLK2_P, CLK2_N | user | FPGA bank 18, pins G30/G31 | - |
FMC connector J2, pins J2/J3 | CLK3_P, CLK3_N | user | FPGA bank 18, pins H29/H30 | - |
FMC connector J2, pins D4/D5 | GBTCLK0_M2C_P, GBTCLK0_M2C_N | user | FPGA bank 117, pins M6/M5 | - |
FMC connector J2, pins B20/B21 | GBTCLK1_M2C_P, GBTCLK1_M2C_N | user | FPGA bank 117, pins P6/P5 | - |
PCIe interface J1, pins A13/A14 | PCIE_CLK_P, PCIE_CLK_N | 100 MHz (PCIe spec.) | FPGA bank 115, pins AD6/AD5 | - |
Table 12: Clock generator sources overview
Programmable PLL Clock (Phase-Locked Loop)
There is a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U13) on-board. It's output frequencies can be programmed by using the I²C-bus with address 0x70.
A 25 MHz (U14) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.
Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected between the FPGA (master) and clock generator (slave). Logic needs to be generated inside the FPGA-module to utilize I²C-bus correctly.
Si5338A (U13) input | signal schematic name | Note |
---|---|---|
IN1/IN2 | CLKIN_5338_C_P, CLKIN_5338_C_N | reference clock signal from clock synthesizer U9 (100 nF decoupling capacitors and 100Ω termination resistor) |
IN3 | clock signal from reference clock oscillator SiTime SiT8208AI (U14). | 25.0 MHz fixed frequency |
IN4/IN6 | pins put to GND | LSB (pin 'IN4') of the default I²C-adress 0x70 is zero |
IN5 | not connected | - |
Si5338A (U13) output | signal schematic name | Note |
CLK0 A/B | DDR3_CLK_P, DDR3_CLK_N | DDR3-RAM reference clock signal to FPGA bank 35 |
CLK1 A/B | MGTCLK_5338_C_P, MGTCLK_5338_C_N | reference clock signal to FPGA bank 115 MGT (100 nF decoupling capacitors and 100Ω termination resistor) |
CLK2 A/B | LMK_CLK_P, LMK_CLK_N | input clock signal to clock synthesizer U9 (100 nF decoupling capacitors) |
CLK3 A/B | MGTCLK2_5338_C_P, MGTCLK2_5338_C_N | reference clock signal to FPGA bank 118 MGT (100 nF decoupling capacitors and 100Ω termination resistor) |
Table 13: Pin description of PLL clock generator Si5338A
Ultra low-noise high-performance clock synthesizer
The TEC0330 board utilizes an ultra low jitter clock synthesizer TI LMK04828B (U9) for conditioning and generating clean clock signals which are necessary for the GTH units of the Xilinx Virtex-7 FPGA-module.
The clock synthesizer can be controlled and programmed by its SPI-interface (SPI-slave) and other control lines, which are routed to the FPGA-module (SPI-master) and by-passed trough the System Controller CPLD. See section 'System Controller CPLD' for more detailed information.
Logic needs to be generated inside the FPGA-module to utilize SPI-bus correctly.
LMK04828B (U9) input | signal schematic name | Note |
---|---|---|
Status_LD1, Status_LD2 | LMK_STAT0, LMK_STAT1 | connected to System Controller CPLD, not evaluated in current CPLD-firmware |
SPI-interface and control lines | see section 'System controller CPLD' | the clock synthesizer can be controlled and programmed by the FPGA-module via the SPI-interface and control lines, which are by-passed through the System Controller CPLD |
CLKin0, CLKin0* | CLK_SYNTH_CLKIN0_P, CLK_SYNTH_CLKIN0_N | input reference clock signal via SMA coaxial connector J3, connected to CLKin0* via serial decoupling capacitator 100nF. CLKin0 to connected to GND via serial decoupling capacitator 100nF. |
CLKin1, CLKin1* | CLK_SYNTH_CLKIN1_P, CLK_SYNTH_CLKIN1_N | input reference clock signal from quad PLL clock generator Si5338A (U13) via serial decoupling capacitator 100nF |
OSCin, OSCin* | - | signal from reference clock oscillator RAKON P51446LF, fixed to 10.0 MHz |
LMK04828B (U9) output | signal schematic name | Note |
DCLKout0, DCLKout0* | CLK_SYNTH_DCLKOUT0_P, CLK_SYNTH_DCLKOUT0_N | reference clock signal to FPGA bank 15 pins AD29/AE29 |
SDCLKout1, SDCLKout1* | CLK_SYNTH_SDCLKOUT1_P, CLK_SYNTH_SDCLKOUT1_N | reference clock signal to FPGA bank 15 pins AE31/AF31 |
DCLKout2, DCLKout2* | CLKIN_5338_P, CLKIN_5338_N | reference clock signal to quad PLL clock generator Si5338A (U13) (100 nF decoupling capacitors and 100Ω termination resistor) |
DCLKout4, DCLKout4* | CLK_SYNTH_DCLKOUT4_P, CLK_SYNTH_DCLKOUT4_N | reference clock signal to FPGA bank 115 MGT, pins T6/T5 |
SDCLKout7, SDCLKout7* | CLK_SYNTH_SDCLKOUT7_P, CLK_SYNTH_SDCLKOUT7_N | reference clock signal to FPGA bank 118 MGT, pins F6/F5 |
OSCout0, OSCout0* | CLK_SYNTH_CLKIN2_P, CLK_SYNTH_CLKIN2_N | reference clock signal to FPGA bank 18, pins J30/J31 (100 nF decoupling capacitors) |
Table 14: Pin description of clock synthesizer TI LMK04828B
32 MByte Quad SPI Flash Memory
An 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG-port (J9) by implementing the functional logic for this purpose inside the FPGA.
Power and Power-On Sequence
Power Supply
The TEC0330 FPGA board is mainly suppled by the 6-pin 12V power connector J5, a minimum current capability of 3A for system startup is recommended. The FPGA board can't be used as a stand-alone board, it works only in use of a plugged PCI Express card (2.0 or higher).
Power Consumption
Power Input | Max Current |
---|---|
12V (J5) | *t.b.d. |
3V3PCI (J1) | *t.b.d. |
Table 15: Maximum current of power supplies. *to be determined
Power-On Sequence
The on-board voltages of the TEC0330 FPGA board will be powered-up in order of a determined sequence after the external voltages '12V' on connector J5 and '3V3PCI' on connector J1 are available.
Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.
Following diagram clarifies the sequence of enabling the particular on-board voltages:
Figure 3: FPGA board TEC0330-03 Power-On sequence diagram
Bank Voltages
Bank | Schematic Name | Voltage | Range | Note |
---|---|---|---|---|
0 | 1V8 | 1.8V | HP: 1.2V to 1.8V | config bank (fixed to 1.8V) / JTAG interface |
14 | 1V8 | 1.8V | HP: 1.2V to 1.8V | QSPI flash memory interface |
15 | 1V8 | 1.8V | HP: 1.2V to 1.8V | reference clock input |
16 | 1V8 | 1.8V | HP: 1.2V to 1.8V | I²C interface of FPGA |
17 | 1V8 | 1.8V | HP: 1.2V to 1.8V | reference clock input |
18 | 1V8 | 1.8V | HP: 1.2V to 1.8V | reference clock input / I/O's to CPLD |
34 | VCC1V5 | 1.5V | HP: 1.2V to 1.8V | DDR3 memory interface |
35 | VCC1V5 | 1.5V | HP: 1.2V to 1.8V | DDR3 memory interface |
36 | VCC1V5 | 1.5V | HP: 1.2V to 1.8V | DDR3 memory interface |
114 115 116 117 118 | MGTAVCC_FPGA MGTVCCAUX_FPGA MGTAVTT_FPGA | 1.0V 1.8V 1.2V | MGT bank supply voltage MGT bank auxiallary supply voltage MGT bank termination circuits voltage | MGT banks with Xilinx GTH transceiver units |
19 | 1V8 | 1.8V | HP: 1.2V to 1.8V | bank's I/O's exposed to FMC, usable as LVDS-pairs |
37 | 1V8 | 1.8V | HP: 1.2V to 1.8V | bank's I/O's exposed to FMC, usable as LVDS-pairs |
38 | 1V8 | 1.8V | HP: 1.2V to 1.8V | bank's I/O's exposed to FMC, usable as LVDS-pairs |
39 | VIO_B_FMC | user | HP: 1.2V to 1.8V | bank's I/O's exposed to FMC, usable as LVDS-pairs |
Table 16: Range of FPGAs bank voltages
See Xilinx Virtex-7 datasheet (DS183) for the voltage ranges allowed.
Power Rails
Connector / -pin | Voltage | Direction | Note |
---|---|---|---|
J4, pin 2 | 12V (filtered) | out | 4-wire PWM fan connector suppy voltage |
J6, pin 2 | 5V (filtered) | out | Cooling fan M1 supply voltage |
J8, pin 6 | 3V3PCI | out | VCCIO CPLD-JTAG |
J9, pin 2 | 1V8 | out | VCCIO FPGA-JTAG |
J2, pin C35 / C37 | 12V | out | VCCIO FMC |
J2, pin D32 | 3V3PCI | out | VCCIO FMC |
J2, pin D36 / D38 / D39 / D40 | 3V3FMC | out | VCCIO FMC |
J2, pin H1 | VREF_A_M2C | in | VREF voltage for bank 37 / 38 |
J2, pin K1 | VREF_B_M2C | in | VREF voltage for bank 39 |
J2, pin J39 / J40 | VIO_B_FMC | in | PL I/O voltage bank 39 (VCCO) |
J2, pin H40 / G39 / F40 / E39 | FMC_VADJ | out | VCCIO FMC (fixed to 1.8V) |
J1, pin A10 / A11 / B8 | 3V3PCI | in | PCIe interface supply voltage |
J5, pin 1 / 2 / 3 | 12V | in | main power supply interface |
Table 17: Power rails of FPGA board on accessible connectors
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes | Notes |
---|---|---|---|---|---|
12V power supply voltage | 11.4 | 12.6 | V | 12V ± 5 % | ANSI/VITA 57.1 FPGA Mezzazine Card (FMC) Standard |
PL I/O voltage for HP banks | -0.55 | VCCO_X + 0.55 | V | - | Xilinx datasheet DS183 |
GTH receiver (RXP/RXN) and transmitter (TXP/TXN) | -0.5 | 1.26 | V | - | Xilinx datasheet DS183 |
Voltage on System Controller CPLD pins | -0.3 | 3.6 | V | - | MachX02 Family Data Sheet |
Storage temperature | -55 | +125 | °C | - | MachX02 Family Data Sheet |
Table 18: Absolute maximum ratings
Recommended Operating Conditions
Parameter | Min | Max | Units | Notes | Reference Document |
---|---|---|---|---|---|
12V power supply voltage | 11.4 | 12.6 | V | 12V ± 5 % | ANSI/VITA 57.1 FPGA Mezzazine Card (FMC) Standard |
PL I/O voltage for HP banks | -0.2 | VCCO_X + 0.2 | V | - | Xilinx datasheet DS183 |
GTH receiver (RXP/RXN) and transmitter (TXP/TXN) | (*) | (*) | - | - | * See data sheet DS183 |
Voltage on System Controller CPLD pins | 3.135 | 3.6 | V | - | MachX02 Family Data Sheet |
Table 19: Recommended operation conditions
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
The FPGA board's operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Physical Dimensions
- board size: 106,65mm × 167,65mm
- Mating height with standard FMC connectors: 10 mm
- PCB thickness: 1.65 mm
Figure 4: Physical dimensions of the TEC0330-03 board. All dimensions are shown in millimeters.
Weight
156 g - Plain board.
Revision History
Hardware Revision History
Date | Revision | Notes | PCN | Documentation |
---|---|---|---|---|
- | 03 | first production release | - | - |
- | 02 | Prototype | - | - |
- | 01 | Prototype | - | - |
Hardware revision number is written on the PCB board together with the model number separated by the dash.
Document Change History
Date | Revision | Contributors | Description |
---|---|---|---|
2017-03-15 | Ali Naseri | Initial TRM release |
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