Table of contents
CPLD Device: LCMX02-256HC
- FPGA UART routing
- CSI_GPIO routing
Firmware Revision and supported PCB Revision
See Document Change History
|Name / opt. VHD Name||Direction||Pin||Description|
|C_TCK / BDBUS0||in||30||UART from FTDI|
|C_TDI / BDBUS1||out||32||UART to FTDI|
|C_TDO / BDBUS2||in||1||/ currently_not_used|
|C_TMS / BDBUS3||in||29||/ currently_not_used|
|CSI_GPIO0 / CSI_IO0||out||25||drive by MIO52|
|CSI_GPIO1 / CSI_IO1||out||23||drive by MIO53|
|DONE||in||8||FPGA DONE Pin|
|JMODE||26||Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over J15 Jumper|
|MIO52||in||20||connected to CSI_GPIO0|
|MIO53||in||21||connected to CSI_GPIO1|
|MIO8||in||28||UART from Zynq|
|MIO9||out||27||UART to Zynq|
UART connection between MIO8/9 and BDBUS0/1.
CSI_GPIO0 drives by MIO52, CSI_GPIO1 drives by MIO53.
|GREEN||ON when Zynq Done pin is down else OFF|
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
|REV01||REV01, REV02, REV03||Revision 01 finished|
|REV01||REV01, REV02, REV03||Initial release|
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