TE0745 TRM

Overview

The Trenz Electronic TE0745 is an industrial-grade module integrating a Xilinx Zynq SoC(XC7Z-030, XC7Z-035 or XC7Z-045), 1 GByte DDR3/L SDRAM, 32 MByte SPI Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking strips.

Key Features

• Industrial grade Xilinx Zynq SoC (XCZ7030, XC7Z035, XC7Z045)

  • Dual-core ARM Cortex-A9 MPCore™ with CoreSight™
  • 200 FPGA PL I/Os (96 LVDS pairs possible)
  • 14 PS MIOs
• 16-bit wide 1GB DDR3L SDRAM
• 32 MByte QSPI Flash memory
• 4 or 8 GTX transceiver lanes (XC7Z030 variant has 4)
• 10/100/1000 Mbps Ethernet transceiver PHY
• EEPROM for storing Ethernet MAC Address
• Hi-speed USB 2.0 ULPI transceiver with full OTG support
• Programmable quad clock generator
• Temperature compensated RTC (real-time clock)
• Plug-on module with 3 × 160-pin high-speed hermaphroditic strips
• On-board high-efficiency DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• User LED
• Evenly-spread supply pins for good signal integrity
• Rugged for shock and high vibration

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TE0745-02 Block Diagram

Main Components

Figure 2: TE0745-02 SoC module

1. Xilinx Zynq XC7Z family SoC, U1
2. 256 Mbit Quad SPI Flash memory Micron N25Q256A, U12
3. Reference clock signal oscillator SiTime SiT8008BI @33.333333 MHz, U12
4. Reference clock signal oscillator SiTime SiT8008BI @25.000000 MHz, U9
5. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U3
6. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 Banks a 32 MWords, 16-bit word width), U3
7. TI TPS51206 DDR3 memory termination regulator with buffered reference voltage VTTREF, U18
8. Intersil ISL12020MIRZ Real-Time-Clock, U24
9. TI TCA9517 level-shifting I²C bus repeater, U17
10. Red LED, D2
    
11. Green LED, D1
12. Intelligent Memory 512 MByte DDR3L-1600 SDRAM (8 banks a 32 MWords, 16 Bit Word-Width), U5
13. Altera Enpirion EN63A0QI 12A DC-DC PowerSoC @1.0V (VCCINT), U4
    
14. TI TPS74401RGW LDO DC-DC regulator @1.2V (MGTAVTT), U8
15. TI TPS72018DRVR LDO DC-DC regulator @1.8V (MGTAUX), U6
16. TI TPS74401RGW LDO DC-DC regulator @1.0V (MGTAVCC), U11
17. Silicon Labs Si5338A I²C Programmable Quad Clock Generator, U13
18. Reference clock signal oscillator SiTime SiT8008BI @25.000 MHz, U21
19. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J3
20. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J1
21. Samtec ST5-80-1.50-L-D-P-TR 160-pin stacking strips (2 rows a 80 positions), J2
22. 256 Mbit Quad SPI Flash memory (Micron N25Q256A, U14
23. Microchip USB3320 USB transceiver PHY , U32
24. Reference clock signal oscillator SiTime SiT8008BI @52.000000 MHz, U33
25. Microchip 24AA025E48 EEPROM for MAC address, U23
    
26. Lattice Semiconductor MachXO2-256HC System Controller CPLD, U2
    

Initial Delivery State

Table 1: Initial delivery state

Signals, Interfaces and Pins

Board to Board (B2B) I/O's

The B2B connectors are high-speed hermaphroditic stacking strips providing modular interface to the SoC's PL and PS I/Os. Both single ended and differential signalling LVDS pairs are supported.

Table 2: Count, type and voltage range of SoC's PL and PS I/O banks pins available through B2B connectors.

For detailed information about the pin-out, please refer to the Pin-out Table.

MGT Lanes

The MGT bank signals of the SoC are routed to the B2B connectors J1 and J3. There are 8 high-speed bi-directional data lanes (Xilinx GTX transceivers) available composed as differential signaling pairs for both directions (RX/TX). On B2B connector J3 there are also clock input pins for MGT transceivers.

Following MGT lanes are available on the B2B connectors:

Table 3: SoC's MGT lanes connections to the B2B connectors

JTAG Interface

JTAG access is provided through the SoC's PS configuration bank 0 and available on B2B connector J1.

Table 4: JTAG interface signals

System Controller I/O Pins

Following special purpose pins are connected to System Controller CPLD:

Table 5: System Controller CPLD special purpose I/O pins

On-board LEDs

Table 6: LEDs of the module

Clocking

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Table 7: Clock sources overview

Default MIO Mapping

The configuration of the I/O's MIO12 - MIO15 and MIO40 - MIO51 are depending on the base-board peripherals connected to this pins.

Table 8: Default MIO Mapping

Gigabit Ethernet Interface

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signalling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U9). The 125MHz PHY output clock (PHY_CLK125M) is routed to the B2B connector J2 pin 150.

Table 9: Ethernet PHY interface connections

USB Interface

USB PHY is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 25.000000 MHz oscillator (U15).

Table 10: USB PHY interface connections

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

The I²C interface on the B2B connector J2 pins 119 (I2C_33_SCL) and 121 (I2C_33_SDA) have PS_3.3V as a reference voltage.

Except the RTC (U24), all remaining I²C slave devices are operating with the reference voltage PS_1.8V via voltage level translating (3.3V ↔ 1.8V) I²C bus repeater (U17).

 I2C addresses for on-board devices are listed in the table below:

Table 11:  Module's I²C-interfaces overview

Boot Process

TE0745 module supports different boot modes which are configurable by the control line 'BOOTMODE' and 'BOOTMODE_1'. The line 'BOOTMODE' is available on B2B connector pin J2-133, the line 'BOOTMODE_1' is connected to the System Controller CPLD on bank 1, pin 21.

The current boot mode will be set by the MIO pins MIO3...MIO5. The control line 'BOOTMODE' is connected to the 'MIO4' pin, 'BOOTMODE_1' to 'MIO5'.

Following table describes how to set the control lines to configure the desired boot mode:

Table 12: Selectable boot modes

On-board Peripherals

Flash

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL12020M is used as Real Time Clock (U24). Battery voltage must be supplied to the clock from the base board via pin 'VBAT_IN' (J1-146). Battery backed registers can be accessed over I²C bus at slave address 0x6F. General purpose RAM of the RTC can be accessed at ^I2C slave address 0x57. RTC IC is supported by Linux so it can be used as hwclock device. The interrupt line 'RTC_INT' of the RTC is connected to System Controller CPLD bank 3 pin 4.

Programmable PLL Clock (Phase-Locked Loop)

There is a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U16) on-board. It's output frequencies can be programmed by using the I²C-bus with address 0x70.

A 25 MHz (U21) oscillator is connected to pin 3 (IN3) and is used to generate the output clocks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C-bus connected between the Zynq module (master) and reference clock signal generator (slave).

Table 13: Pin description of PLL clock generator Si5338A

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

Table 14: Maximum current of power supplies. *to be determined soon with reference design setup.

For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power-On Sequence

The on-board voltages of the TE0745 SoC module will be powered-up in order of a determined sequence after the external voltages 'PL_VIN', 'PS_VIN' and 'PS_3.3V' are available.

Core voltages and main supply voltages have to reach stable state and their "Power Good"-signals have to be asserted before other voltages like PL bank's I/O voltages can be powered up.

It is important that all baseboard I/Os are 3-stated at power-on until the "Power Good"-signals 'PWR_PS_OK' (J2-139) and 'PWR_PL_OK' (J2-135) are high, meaning that all on-module voltages have become stable and module is properly powered up.

Following diagram clarifies the sequence of enabling the particular on-board voltages:

Figure 3: Power-up sequence diagram

See Xilinx datasheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0745 module.

Power Rails

Table 15: Power rails of the SoC module on accessible connectors

Bank Voltages

Table 16: Range of SoC module's bank voltages

B2B connectors

Variants Currently In Production

Table 17: Differences between variants of Module TE0808-04

Technical Specification

Absolute Maximum Ratings

Recommended Operating Conditions

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 52 mm × 76 mm.  Please download the assembly diagram for exact numbers

• Mating height with standard connectors: 4mm

• PCB thickness: 1.6mm

• Highest part on PCB: approx. 3mm. Please download the step model for exact numbers

All dimensions are given in millimeters.

Figure 4: Physical dimensions of the TE0745 SoC module

Weight

24 g - Plain module

Revision History

Hardware Revision History

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Figure 5: TE0745 module revision number

Document Change History 

Date	Revision	Contributors	Description
2017-03-31		Ali Naseri, Jan Kumann	First TRM release.
2017-02-05	V1	Jan Kumann	Initial document.

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