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Table of contents

Overview

Firmware for PCB CPLD with designator U27. CPLD Device in Chain: LCMX02-7000HC

Feature Summary

  • Power Management
  • Reset Management
  • Boot Mode
  • FAN Control
  • LED Control
  • FMC JTAG
  • PJTAG

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinDescriptionSchematic Sheet
3V3SB B16CPLD Programm Pin connected with pullupSC1
3V3SB B20CPLD initn Pin connected with pullupSC1
3V3SB C29CPLD Done Pin connected with pullupSC1
A_LA06_SC_N C22 / currently_not_usedSC2
A_LA06_SC_P B22 / currently_not_usedSC2
A_LA07_SC_N F20 / currently_not_usedSC2
A_LA07_SC_P E22 / currently_not_usedSC2
A_LA08_SC_N E21 / currently_not_usedSC2
A_LA08_SC_P D22 / currently_not_usedSC2
A_LA09_SC_N G22 / currently_not_usedSC2
A_LA09_SC_P G21 / currently_not_usedSC2
A_LA10_SC_N G17 / currently_not_usedSC2
A_LA10_SC_P H16 / currently_not_usedSC2
A_LA11_SC_N K22 / currently_not_usedSC2
A_LA11_SC_P K21 / currently_not_usedSC2
A_LA12_SC_N H20 / currently_not_usedSC2
A_LA12_SC_P H21 / currently_not_usedSC2
A_LA13_SC_N L22 / currently_not_usedSC2
A_LA13_SC_P L21 / currently_not_usedSC2
A_LA14_SC_N G16 / currently_not_usedSC2
A_LA14_SC_P F18 / currently_not_usedSC2
A_LA15_SC_N D19 / currently_not_usedSC2
A_LA15_SC_P C21 / currently_not_usedSC2
A_LA16_SC_N M21 / currently_not_usedSC2
A_LA16_SC_P M22 / currently_not_usedSC2
A_LA17_SC_N N21 / currently_not_usedSC2
A_LA17_SC_P N22 / currently_not_usedSC2
A_LA18_SC_N G19 / currently_not_usedSC2
A_LA18_SC_P F19 / currently_not_usedSC2
A_LA19_SC_N E19 / currently_not_usedSC2
A_LA19_SC_P D20 / currently_not_usedSC2
A_LA20_SC_N E20 / currently_not_usedSC2
A_LA20_SC_P D21 / currently_not_usedSC2
A_LA21_SC_N J17 / currently_not_usedSC2
A_LA21_SC_P J16 / currently_not_usedSC2
A_LA22_SC_N J19 / currently_not_usedSC2
A_LA22_SC_P J18 / currently_not_usedSC2
A_LA23_SC_N G18 / currently_not_usedSC2
A_LA23_SC_P H17 / currently_not_usedSC2
A_LA24_SC_N R22 / currently_not_usedSC2
A_LA24_SC_P P20 / currently_not_usedSC2
A_LA25_SC_N K16 / currently_not_usedSC2
A_LA25_SC_P K17 / currently_not_usedSC2
A_LA26_SC_N K18 / currently_not_usedSC2
A_LA26_SC_P L20 / currently_not_usedSC2
A_LA27_SC_N K20 / currently_not_usedSC2
A_LA27_SC_P J21 / currently_not_usedSC2
A_LA28_SC_N U22 / currently_not_usedSC2
A_LA28_SC_P T20 / currently_not_usedSC2
A_LA29_SC_N T22 / currently_not_usedSC2
A_LA29_SC_P T21 / currently_not_usedSC2
A_LA30_SC_N W22 / currently_not_usedSC2
A_LA30_SC_P V21 / currently_not_usedSC2
A_LA31_SC_N V22 / currently_not_usedSC2
A_LA31_SC_P U20 / currently_not_usedSC2
A_LA32_SC_N Y20 / currently_not_usedSC2
A_LA32_SC_P Y21 / currently_not_usedSC2
A_LA33_SC_N AA22 / currently_not_usedSC2
A_LA33_SC_P Y22 / currently_not_usedSC2
B64_T1outD3reserved for RGPIO  / currently_not_implementedSC2
B64_T2inC3reserved for RGPIO / currently_not_implementedSC2
B64_T3inB1reserved for RGPIO / currently_not_implementedSC2
B65_T1 C2 / currently_not_usedSC2
B65_T2 E4 / currently_not_usedSC2
B65_T3 C1 / currently_not_usedSC2
B66_T1inD1FPGA / dp_aux_data_outSC2
B66_T2inF4FPGA / dp_aux_data_oe_nSC2
B66_T3outF3FPGA / dp_aux_data_SC2
B67_T1outF1FPGA / dp_hot_plug_detectSC2
B67_T2inG3FPGA /  LED SC2
B67_T3inH4FPGA / LED SC2
C_TCKinA8JTAG  CPLD XMODSC1
C_TDIinC7

JTAG CPLD XMOD

 
SC1
C_TDOoutA6JTAG CPLD XMODSC1
C_TMSintC9JTAG CPLD XMODSC1
CAN_FAULT D15 / currently_not_usedSC1
CAN_RX B15 / currently_not_usedSC1
CAN_S C15 / currently_not_usedSC1
CAN_TX C16 / currently_not_usedSC1
CLK_SCinAA9external User CLK 25MHz (oscillator is assembly option)SC1
DDR_ENoutC6Power 7ASC1
DDR_PGinB8Power 7A SC1
DONEinG4PS Config SC2
DP_AUX_DEoutAB13DP SC1
DP_AUX_RXinAB12DPSC1
DP_AUX_TXoutAA14DP SC1
DP_ENoutM4Power 8SC2
DP_TX_HPDinAA15DP SC1
EN_12VoutC10Power 1 SC1
EN_3.3V / EN_3P3VoutY8Power 2 SC1
EN_A_3V3outY18Power 8 FMCSC1
EN_AF_1V8outW19Power 8 FMCSC1
EN_B_3V3outG11Power 8 FMC SC1
EN_BC_1V8outA3Power 8 FMCSC1
EN_C_3V3outE11Power 8 FMCSC1
EN_D_3V3outF8Power 8 FMCSC1
EN_DE_1V8outC5Power 8 FMCSC1
EN_E_3V3outE8Power 8 FMCSC1
EN_F_3V3outY10Power 8 FMC SC1
EN_GT_LoutA7Power 4B,CSC1
EN_GT_RoutB7Power 4B,CSC1
EN_SFP_SSDoutW8Power 8SC1
EN_VCCINToutB9Power 1 SC1
ERR_OUTinH1PS Config SC2
ERR_STATUSinJ2PS Config  SC2
ETH_RSToutL6Reset SC2
F_LA06_SC_N M19 / currently_not_usedSC2
F_LA06_SC_P M18 / currently_not_usedSC2
F_LA07_SC_N P21 / currently_not_usedSC2
F_LA07_SC_P N20 / currently_not_usedSC2
F_LA08_SC_N N18 / currently_not_usedSC2
F_LA08_SC_P M20 / currently_not_usedSC2
F_LA09_SC_N R18 / currently_not_usedSC2
F_LA09_SC_P R19 / currently_not_usedSC2
F_LA10_SC_N R20 / currently_not_usedSC2
F_LA10_SC_P R21 / currently_not_usedSC2
F_LA11_SC_N U19 / currently_not_usedSC2
F_LA11_SC_P T19 / currently_not_usedSC2
F_LA12_SC_N P18 / currently_not_usedSC2
F_LA12_SC_P P19 / currently_not_usedSC2
F_LA13_SC_N U17 / currently_not_usedSC2
F_LA13_SC_P U18 / currently_not_usedSC2
F_LA14_SC_N R17 / currently_not_usedSC2
F_LA14_SC_P T18 / currently_not_usedSC2
F_LA15_SC_N R16 / currently_not_usedSC2
F_LA15_SC_P T17 / currently_not_usedSC2
F_LA16_SC_N V19 / currently_not_usedSC2
F_LA16_SC_P W20 / currently_not_usedSC2
F_LA17_SC_N N16 / currently_not_usedSC2
F_LA17_SC_P N17 / currently_not_usedSC2
F_LA18_SC_N L16 / currently_not_usedSC2
F_LA18_SC_P L17 / currently_not_usedSC2
F_LA19_SC_N M16 / currently_not_usedSC2
F_LA19_SC_P M17 / currently_not_usedSC2
F_LA20_SC_N N6 / currently_not_usedSC2
F_LA20_SC_P N7 / currently_not_usedSC2
F_LA21_SC_N T6 / currently_not_usedSC2
F_LA21_SC_P R7 / currently_not_usedSC2
F_LA22_SC_N T5 / currently_not_usedSC2
F_LA22_SC_P R6 / currently_not_usedSC2
F_LA23_SC_N P6 / currently_not_usedSC2
F_LA23_SC_P P7 / currently_not_usedSC2
F_LA24_SC_N W3 / currently_not_usedSC2
F_LA24_SC_P V4 / currently_not_usedSC2
F_LA25_SC_N Y2 / currently_not_usedSC2
F_LA25_SC_P W4 / currently_not_usedSC2
F_LA26_SC_N U4 / currently_not_usedSC2
F_LA26_SC_P T4 / currently_not_usedSC2
F_LA27_SC_N U5 / currently_not_usedSC2
F_LA27_SC_P T7 / currently_not_usedSC2
F_LA28_SC_N V2 / currently_not_usedSC2
F_LA28_SC_P W1 / currently_not_usedSC2
F_LA29_SC_N AA1 / currently_not_usedSC2
F_LA29_SC_P Y1 / currently_not_usedSC2
F_LA30_SC_N V1 / currently_not_usedSC2
F_LA30_SC_P U3 / currently_not_usedSC2
F_LA31_SC_N V3 / currently_not_usedSC2
F_LA31_SC_P W2 / currently_not_usedSC2
F_LA32_SC_N M3 / currently_not_usedSC2
F_LA32_SC_P N5 / currently_not_usedSC2
F_LA33_SC_N R2 / currently_not_usedSC2
F_LA33_SC_P R3 / currently_not_usedSC2
F1_ENoutC8FAN SC1
F1PWMoutE10FANSC1
F1SENSEinD11FAN SC1
F2_ENoutB4FANSC1
F2PWMoutD9FANSC1
F2SENSEinG12FANSC1
F3_ENoutA12FANSC1
F3PWMoutB13FANSC1
F3SENSEinA13FANSC1
FAN_A_ENoutY19FANSC1
FAN_B_ENoutA2FAN SC1
FAN_C_ENoutB3FANSC1
FAN_D_ENoutD7FANSC1
FAN_E_ENoutD6FANSC1
FAN_F_ENoutW18FANSC1
FMC12V_ENoutAA8Power 8 FMCSC1
FMCA_PG_C2MinoutE16Power 8 FMCSC1
FMCA_PG_M2CinF17Power 8 FMCSC1
FMCA_PRSNTinF16Power 8 FMCSC1
FMCA_TCKoutT16JTAGSC1
FMCA_TDIoutU15JTAGSC1
FMCA_TDOinU16JTAGSC1
FMCA_TMSoutV17JTAGSC1
FMCAF_12V_PGinW9Power 8 FMCSC1
FMCB_PG_C2MinoutC4Power 8 FMCSC1
FMCB_PG_M2CinD5Power 8 FMCSC1
FMCB_PRSNTinD4Power 8 FMCSC1
FMCB_TCKoutE6JTAG SC1
FMCB_TDIoutD8JTAGSC1
FMCB_TDOinE9JTAG SC1
FMCB_TMSoutF10JTAGSC1
FMCC_PG_C2MinoutU6Power 8 FMCSC1
FMCC_PG_M2CinV6Power 8 FMC SC1
FMCC_PRSNTinW5Power 8 FMCSC1
FMCC_TCKoutW6JTAGSC1
FMCC_TDIoutY4JTAGSC1
FMCC_TDOinY5JTAGSC1
FMCC_TMSoutAA3JTAGSC1
FMCD_PG_C2MinoutG8Power 8 FMCSC1
FMCD_PG_M2CinG10Power 8 FMC SC1
FMCD_PRSNTinAA4Power 8 FMCSC1
FMCD_TCKoutT12JTAGSC1
FMCD_TDIoutU8JTAGSC1
FMCD_TDOinV9JTAGSC1
FMCD_TMSoutU10JTAGSC1
FMCE_PG_C2MinoutAB3Power 8 FMC SC1
FMCE_PG_M2CinAB2Power 8 FMC SC1
FMCE_PRSNTinAB5Power 8 FMCSC1
FMCE_TCKoutY6JTAGSC1
FMCE_TDIoutAB6JTAGSC1
FMCE_TDOinAA7JTAGSC1
FMCE_TMSoutAB7JTAGSC1
FMCF_PG_C2MinoutAB20Power 8 FMC SC1
FMCF_PG_M2CinAB21Power 8 FMCSC1
FMCF_PRSNTinAA19Power 8 FMCSC1
FMCF_TCKoutW11JTAGSC1
FMCF_TDIoutV11JTAGSC1
FMCF_TDOinAB10JTAGSC1
FMCF_TMSoutAA10JTAGSC1
I2C_RSToutL2ResetSC2
INIT_BinJ3PS ConfigSC2
JTAGENBinA16JTAG /  Enable to get access to CPLD over JTAG. Pin is not accessible on CPLD. Is set by DIP-Switch S3-2SC1
LED_1A Y12 / currently_not_usedSC1
LED_2A Y13 / currently_not_usedSC1
LED_2B Y14 / currently_not_usedSC1
LED1outU12USR (D13 green) SC1
LED2outV12USR (D14 green) SC1
LED3outW12USR (D15 green) SC1
LED4outV13USR (D16 red)SC1
MEM_SCLinW16I2CSC1
MEM_SDAinoutV16I2CSC1
MIO24 F5MIO  / currently_not_usedSC2
MIO25 G5MIO  / currently_not_usedSC2
MIO26outG15MIO / PJTAG TCKSC1
MIO27outE12MIO / PJTAG TDISC1
MIO28inE15MIO / PJTAG TDOSC1
MIO29outC11MIO / PJTAG TMSSC1
MIO30outC13MIO / Status LEDSC1
MIO31inB12MIO  / currently_not_usedSC1
MIO32 B11MIO  / currently_not_usedSC1
MIO33inU7MIO / PCIe ResetSC1
MIO34 D12MIO  / currently_not_usedSC1
MIO35 F15MIO  / currently_not_usedSC1
MIO36 G7MIO  / currently_not_usedSC1
MIO37 D14MIO  / currently_not_usedSC1
MIO40 F12MIO  / currently_not_usedSC1
MIO41 T8MIO  / currently_not_usedSC1
MIO42outB14MIO / UART RXSC1
MIO43inE7MIO / UART TXSC1
MIO44outE14MIO / SD-WPSC1
MIO45outA20MIO / SD-CPSC1
MIO6inF6MIO / QSPI FB CLK from ZynqMPSC2
MODE0outH3PS Config Boot Mode SC2
MODE1outH2PS Config Boot Mode SC2
MODE2outG2PS Config Boot Mode SC2
MODE3outG1PS Config  Boot Mode SC2
MRoutL7PS Config (PS_POR_B)  ResetSC2
NCoutAA20used as dummi output pin / Not connectedSC1
NC T15Not connectedSC1
NC W17Not connectedSC1
NC V15Not connectedSC1
NC W15Not connectedSC1
NC V14Not connectedSC1
NC W14Not connectedSC1
NC U13Not connectedSC1
NC T13Not connectedSC1
NC AB16Not connectedSC1
NC Y3Not connectedSC1
NC A21Not connectedSC1
NC G6Not connectedSC2
NC N1Not connectedSC2
NC N2Not connectedSC2
NC M1Not connectedSC2
NC N3Not connectedSC2
NC P2Not connectedSC2
NC M7Not connectedSC2
NC M6Not connectedSC2
NC P3Not connectedSC2
NC R1Not connectedSC2
NC M5Not connectedSC2
NC H5Not connectedSC2
NC J5Not connectedSC2
NC J4Not connectedSC2
NC K5Not connectedSC2
NC L3Not connectedSC2
PG_12VinA11Power 1 SC1
PG_FPDinA10Power 2SC1
PG_GT_LinK3Power 5BCSC2
PG_GT_RinF11Power 5BCSC1
PG_PSGTinA5Power 6A SC1
PHY_CLK125MinK2CLKSC2
PHY_LED0 L5 / currently_not_usedSC2
PHY_LED1 L1 / currently_not_usedSC2
PHY_LED2 K1 / currently_not_usedSC2
PLL_RSToutL4Reset SC2
PROG_BoutE2 PS Config (opt. PL Reset)SC2
PSGT_ENoutB10Power 4ASC1
SC_SW1inE17USR S3-3 / Set Boot ModeSC1
SC_SW2inD16USR S3-4 / Set Boot Mode SC1
SD_CDinT11SD CDSC1
SD_ENoutU11Power 8SC1
SD_WPinT10SD WPSC1
SFP_LED1 AB17 / currently_not_usedSC1
SFP_LED2 AB18 / currently_not_usedSC1
SFP_LED3 AA16 / currently_not_usedSC1
SFP_LED4 AB15 / currently_not_usedSC1
SFP0_LOS V8 / currently_not_usedSC1
SFP0_TX_DISoutY7SFPSC1
SFP1_LOS W7 / currently_not_usedSC1
SFP1_TX_DIS V7SFPSC1
SI5345_CLK E1 / currently_not_usedSC2
SSD1_LED AA13 / currently_not_usedSC1
SSD1_PERSTNoutAA11SSD Reset SC1
SSD1_SLEEP AA12 / currently_not_usedSC1
SSD1_WAKEoutAB11SSDSC1
U_SW1inD18USR (S4-1) / currently_not_usedSC1
U_SW2inD17USR (S4-2) / currently_not_usedSC1
U_SW3inC19USR (S4-3)/ currently_not_usedSC1
U_SW4inC18USR (S4-4) / currently_not_usedSC1
USB0_RSToutM2Reset SC2
USBH_MODE0outY17USBSC1
USBH_MODE1outY16USBSC1
USBH_RSToutY15Reset SC1
USR_BUT1inF13USR (S1)  SC1
USR_BUT2inG13USR (S2) / Power Reset SC1
XMOD1_A B19XMOD J35 / currently_not_usedSC1
XMOD1_BoutA17XMOD J35 LED / Attention this is connected to XMOD1_E SC1
XMOD1_E C17XMOD J35 / Attention this is connected to XMOD1_B  / currently_not_usedSC1
XMOD1_GinA18XMOD  J35 Button  SC1
XMOD2_AoutK7UART RXD (XMOD J24) SC2
XMOD2_BinK6UART TX  (XMOD J24) SC2
XMOD2_EoutH7XMOD J24 LED / Boot ModeSC2
XMOD2_GinH6XMOD J24 Button / PS Reset SC2

 

Functional Description

JTAG

JTAG access over CPLD XMOD J35.

Set DIP-Switch S3-2 to ON to get CPLD into JTAG Chain. This is only needed for CPLD update. Otherwise JTAG is routed thought FMCs or to PJTAG dependign on boot mode. JTAG is connected into cascade from FMC A to F, if module is detected, otherwise corresponding connector is left out.

Boot ModeDescription
PJTAG0PJTAG MIOs are connected to JTAG chain
all otherFMC IOs are connected to JTAG chain

Note: FPGA/SoC JTAG access is available directly over second XMOD.

Power

Power is controlled by different state machines and can be restart over S2 Button. Main Power sequence must be finished successfully before other power management units starts. Power Management can be checked over status LEDs, see LED section.

Main Power:

StateConditions for next stateDescription
1:IDLEPG_12V is ready

Start with this state on power up or Power Reset

  • EN12V is enabled, EN_VCCINT, EN_3P3V, DDR_EN are disabled
2:PER1_ENPG_FPD is ready
  • EN12V, EN_VCCINT, EN_3P3V are enabled, DDR_EN is is disabled
3:PER2_ENDDR_PG is ready
  • EN12V, EN_VCCINT, EN_3P3V DDR_EN are enabled 
4:RDYDDR_PG or PG_FPD or PG_12V failedNormal state if power sequence was ok.
5:ERROR---Only set, if a error occurs after successfully power up. Manually reset is needed.

MGT Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • PSGT_EN, EN_GT_L, EN_GT_R are disabled
2:PER1_ENPG_PSGT, PG_GT_L, PG_GT_R are ready
  • SGT_EN, EN_GT_L, EN_GT_R are enabled
3:RDYPG_PSGT or  PG_GT_L or  PG_GT_R failedNormal state if power sequence was ok.
4:ERROR---Only set if a error occurs after successfully power up. Manually reset is needed.

Periphery Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • DP_EN, EN_SFP_SSD, SD_EN are disabled
2:PER1_ENNo check possible, next state is RDY
  • DP_EN, EN_SFP_SSD, SD_EN are enabled
3:RDYNo check possibleNormal state if power sequence was ok.
4:ERROR---This state should never occurs.

FMC A and F Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • FMC12V_EN, EN_AF_1V8, EN_A_3V3, EN_F_3V3, FMCF_PG_C2M, FMCA_PG_C2M are disabled
2:PER1_ENFMCAF_12V_PG, FMCF_PG_C2M, FMCA_PG_C2M are ready
  • FMC12V_EN, EN_AF_1V8, EN_A_3V3, EN_F_3V3, FMCF_PG_C2M, FMCA_PG_C2M are enabled
3:RDYFMCAF_12V_PG or FMCF_PG_C2M or FMCA_PG_C2M failedNormal state if power sequence was ok.
4:ERROR---Only set if a error occurs after successfully power up. Manually reset is needed.

* FMCF_PG_C2M, FMCA_PG_C2M are bidirectional.  External Pull up is used to check power fails.

FMC B,C,D,E Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • EN_BC_1V8, EN_DE_1V8, EN_B_3V3, EN_C_3V3, EN_D_3V3, EN_E_3V3, FMCB_PG_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are disabled
2:PER1_ENFMCB_PG_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are ready
  • EN_BC_1V8, EN_DE_1V8, EN_B_3V3, EN_C_3V3, EN_D_3V3, EN_E_3V3, FMCB_PG_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are enabled

3:RDYFMCB_PG_C2M or FMCC_PG_C2M or FMCD_PG_C2M or FMCE_PG_C2M failedNormal state if power sequence was ok.
4:ERROR---Only set if a error occurs after successfully power up. Manually reset is needed.

FMCF_PB_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are bidirectional.  External Pull up is used to check power fails. 12V is sourced  and controlled by main power.

 

Reset

ButtonDescription
S2Main Power Reset Button. Restart power management.
FPGA XMODPS MR  Reset Button. Restart PS (PS_POR_B)
  • Buttons are debounced.

For all other resets, see component sections.

Boot Mode

S3-3 (SC_SW1)S3-4 (SC_SW2)Description
OFFOFFSD1 Boot Mode (SD-Card on J11)
OFFONPJTAG0
ONOFFQSPI32
ONONJTAG

 

Display Port

OutputInput
DP_AUX_TXB66_T1
DP_AUX_DEnot B66_T2
B66_T3DP_AUX_RX
B67_T1DP_TX_HPD

SD

SD_EN is controlled by power management.

SD_CD is connected to MIO45.

SD_WP is connected to MIO44.

SFP

Transmit for all SFP is enabled.

USB

USB Mode pins constant "11" (default boot mode).

USB0_RST is controlled by power management.

USBH_RST is controlled by power management.

SSD

SSD1_WAKE is "0".

SSD1_PERSTn is controlled by power management and MIO33.

I2C

I2C_RST is controlled by power management.

FAN

FAN1 to FAN3 speed can be controlled via I2C Bus. FMC FANs can be disabled over I2C Bus and only run, if FMCx_PRESNT is available.

I2C Baseaddress: 0x74. I2C with 8Bit Register Address with 8Bit Data. I2C CLK currently 100 MHz supported.

Write Access:

Register AddressNameDescription
0FAN CTRL

Enable FAN, Bit 0-2 Fan1 to Fan2, Bit 3 FMC B, Bit 4 FMC C , Bit 5 FMC D , Bit 6 FMC E, Bit 7 FMC A and F. Default all enabled (1)

1FAN1 PWMFAN1 PWM (0%-100%, Default 30%)
2FAN2 PWMFAN2 PWM (0%-100%, Default 30%)
3FAN3 PWMFAN3 PWM (0%-100%, Default 30%)

Read Access:

Register AddressNameDescription
0FAN CTRLFAN Control register
1FAN1 RPSFAN1 Revolutions per second
2FAN2 RPSFAN2 Revolutions per second
3FAN3 RPSFAN3 Revolutions per second

 

FMC

FMC present (FMCx_PRESNT) signals are used for board detect and enables.

FMC JTAG: See JTAG section

FAN : See FAN section

 

UART

UART is connected to FPGA XMOOD on J24. XMOD UART RXD output is connected to MIO42. MIO43 is connected to XMOD UART TX input.

USR Buttons and Switches

---

LED

LEDDescription
LED4 (D16 red)

User FPGA IO B67_T3

LED3 (D15 green)User FPGA IO B67_T2
LED2 (D14 green)

PS Status. Status depends on blink sequence and priority.

  1. ********    : Reset button is pressed
  2. *****ooo   : Init_B failed
  3. ****oooo   : PS_Error_Status and PS_Error failed
  4. ***ooooo   : PS_Error_Status failed
  5. **oooooo  : PS_Error failed
  6. *ooooooo  : Done is low-> SoC PL not programmed
  7. LED OFF or ON :  user defined from MIO30
LED4 (D13 green)Power LED. Status depends on blink sequence and priority.
  1. LED ON  : Power button is pressed
  2. ********    : Main power up failed
  3. *****ooo   : Main power error after successfully startup
  4. *****ooo   : MGT or Periphery power up failed
  5. ***ooooo  : MGT or Periphery power error after successfully startup
  6. **oooooo  : FMC power up failed
  7. *ooooooo : FMC power error after successfully startup
  8. LED OFF : Power good
FPGA XMOD (J24-XMOD2)

Boot Mode. Status depends on blink sequence and priority.

  1. LED ON  : JTAG
  2. ********    : Error unknown state
  3. *****ooo   : not used
  4. *****ooo   : not used
  5. ***ooooo  : not used
  6. **oooooo  : QSPI
  7. *ooooooo : PJTAG_0
  8. LED OFF : SD1
CPLD XMOD (J35-XMOD1)
  1. ********    : one or more of FMCx_PG_M2C of connected FMC are not ready
  2. LED OFF : all connected FMCx_PG_M2C are ready

 

Appx. A: Change History and Legal Notices

Revision Changes

CPLD REV01 to REV02

  • Correction of FAN_A_EN and FAN_AF_EN Location constrains

  • Add Pullup attribute to FMCX_PRSNT signals

  • I2C Enable mapping is changed

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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REV02REV02

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Revision 02 working in process
2017-08-16v.21REV01REV02John HartfielRevision 01 finished
2017-07-25v.1REV01REV02

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Initial release
 All  

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Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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