TE0741 TRM

Overview

Trenz Electronic TE0741 is an industrial-grade FPGA module integrating a Xilinx Kintex-7 FPGA, 32 MByte SPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips.

The TE0741 module is available in four different logic densities (70T, 160T, 325T and 410T). The 70T and 160T devices can be programmed with the free Xilinx Vivado WebPACK software. Further information about the Kintex-7 FPGA can be found in the Xilinx document 7 Series FPGA's Overview (DS180).

Key Features

• Industrial-grade Xilinx Kintex-7 FPGA module (70T*, 160T*, 325T, 410T)
  * Devices supported by the free Xilinx Vivado WebPACK software.
• 256-Mbit (32-MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
  • FPGA
  • JTAG port (SPI indirect (Bus width x4))
• 8 GTX transceivers
• FPGA configuration through:
  • JTAG (B2B connector)
  • SPI Flash memory
• 25 MHz low jitter oscillator with shutdown control
• Programmable quad PLL clock generator
• On-board high-efficiency DC-DC converters
  • GTX voltage regulators with control enable
  • Core voltage regulator: 20A (2 x Enpirion DC-DC regulators with load-sharing)
  • Supply voltages: either 3.3V or 3.3V and 5V
• Plug-on module with two 100-pin and one 60-pin high-speed hermaphroditic stacking strips
• Up to 144 (94 for 70T) FPGA I/O pins are available on B2B strips (up to 65 LVDS pairs possible)
• 2 user LED's, 1x DONE FPGA pin LED, 1 System Controller status LED
• System management and power sequencing
• AES bit-stream encryption
• eFUSE bit-stream encryption
• Evenly spread supply pins for good signal integrity

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TE0741 block diagram.

Main Components

Figure 2.1: TE0741--03-410-2CF module.

Figure 2.2: TE0741-03-160-2C1 module.

1. Xilinx Kintex-7 FPGA, U1
2. Green LED (DONE), D3
3. Red LED (LED1), D2
4. Green LED (LED2), D1
5. EN63A0QI Voltage Regulator 1.0V (Master), U14
6. EN63A0QI Voltage Regulator 1.0V (Slave), U15
7. Green LED (C_LED), D4

8. Voltage detector, U11

9. Serial number (traceability) pad
10. I²C-programmable any-frequency, any-output quad clock generator, U2
11. Low-power programmable oscillator @ 25.000000 MHz, U3
12. Samtec Razor Beam™ LSHM-150 B2B connector, JM2 
13. 32 MByte quad SPI Flash memory, U4
14. Samtec Razor Beam™ LSHM-130 B2B connector, JM3 
15. 3A PFET load switch with configurable slew rate (3.3V), Q1
    
16. Samtec Razor Beam™ LSHM-150 B2B connector, JM1 
17. System Controller CPLD, U7
18. EP53F8QI Voltage Regulator (1.2V_MGT), U6
19. EP53F8QI Voltage Regulator (1.8V), U8
20. EP53F8QI Voltage Regulator (1V_MGT), U16

Initial Delivery State

Table 1: Initial delivery state.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Overview of the I/O signal banks connected to the B2B connectors:

Table 2: Available I/O signal banks connected to the B2B connectors.

Please use Master Pin-out Table table as primary reference for the pin mapping information.

JTAG Interface

JTAG access to the Xilinx Kintex-7 and to the System Controller CPLD is provided through B2B connector JM2.

Table 3: Pin-mapping of JTAG Interface on B2B connector.

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Table 4: Pin-description of System Controller CPLD.

On-board LEDs

There are four LED's available on TE0741 SoM. Two status LED's (D3 and D4) and two user configurable LED's (D1 and D2).

Table 5: Description of the on board LED's.

Note: if FPGA logic toggles DONE pin (to control D3) then D4 will toggle at random, as changing value on DONE will change the blink frequency of D4.

Clocking

To enable the PLL (phase-locked loop) clock generator Si5338A (U2), CLK_EN-signal (bank 14, pin C26) must be set to high, to activate the 25 MHz reference clock SiT8208AI (U3). The GTX reference clocks 0 and 2 have to be provided by the user on B2B connector JM3.

Table 6: Clocks overview.

On-board Peripherals

Programmable PLL Clock (Phase-Locked Loop)

There is a Silicon Labs I2C programmable clock generator Si5338A (U2) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70 or 0x71 (PLL_IN4 (LSB of I2C-Address) must be set for address 0x71).

A 25 MHz oscillator is connected to pin IN3 and is used to generate the output clocks. The oscillator has its enable pin connected to an FPGA pin (CLK_EN). Driving the FPGA pin low will disable the oscillator output, setting it high will enable it. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTX banks. It is possible to use the clocks connected to the GTX bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.

The default frequency of each clock at start up is detailed in the table 7.

Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). Logic needs to be generated inside the FPGA to utilize I2C bus correctly.

Figure 3: Clocking block diagram.

Table 7: Pin description of Si5338A PLL clock generator.

32 MByte Quad SPI Flash Memory

An SPI flash memory S25FL256SAGBHI20 (U4) is provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

GTX Transceivers

The Kintex-7 device that is used on the TE0741 board has 8 GTX transceivers. All 8 are wired directly to connectors JM1 and JM3. There are also 4 clocks that are associated with the transceivers. Two of the clocks are connected directly to JM3, whilst the other two are derived from the clock generator. As there is no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

To enable the voltage supply for the GTX transceivers, namely the Enpirion EP53F8QI voltage regulators U6 and U16, which serve the voltages MGTAVCC (1.0 V) and MGTAVTT (1.2 V), the signal EN_MGT (bank 14, pin H22) have to be set high. The voltage regulators will indicate "Power OK" with signals PG_MGT_1V and PG_MGT_1V2, when reaching stable state.

Figure 4: GTX transceiver block diagram.

System Controller CPLD

The System Controller CPLD is used to coordinate the configuration of the FPGA. The FPGA is held in reset (by driving the PROG_B signal) until the power supplies have sequenced. Setting input signal RESIN low will also reset the FPGA. This signal can be driven from the user’s PCB via the board connector.

User can create its own System Controller CPLD design using the Lattice Diamond software and program it into the device using the JTAG interface. The JTAGMODE signal should be set to 3.3V to enable programming mode, for normal module operation it should be set to 0V.

Green LED D4 (C_LED) connected to the System Controller CPLD is to indicate the status of the module.

Figure 5: System Controller CPLD block diagram.

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

Table 8: Maximum current of power supplies.

* TBD - To Be Determined.

Lowest power consumption is achieved when powering the module from single 3.3V supply. When using split 3.3V/5V power supplies, the power consumption (and heat dissipation) will rise, this is due to the DC-DC converter efficiency (it decreases when VIN/VOUT ratio rises).

Power-On Sequence

For highest efficiency of on board DC-DC regulators, it is recommended to use same 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

It is important that all baseboard I/Os are 3-stated at power-on until System Controller sets PGOOD signal high (B2B connector JM1, pin 30), or 3.3V is present on B2B connector JM2 pins 10,12 or 91, meaning that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS182 for additional information. User should also check related baseboard documentation when choosing baseboard design for TE0741 module.

The FPGA 1.0V supply is derived from two regulators operating in a parallel allowing higher load currents. To start the power-on sequence, pin EN1 (JM1-28, enable 1.0V voltage regulators) is by default high. By driving EN1 pin low on base-board the power-on sequence will not start until the EN1 pin is released to high.

Power Rails

Table 9: Power rails of SoM on B2B connectors.

Bank Voltages

Table 10: Range of FPGAs bank voltages.

See Xilinx Kintex-7 datasheet DS182 for the voltage ranges allowed.

Board to Board Connectors

Variants Currently In Production

Table 11: Module TE0741-03 variants.

Technical Specifications

Absolute Maximum Ratings

Table 12: Absolute maximum ratings.

Recommended Operating Conditions

Table 13: Recommended operation conditions.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm
• Mating height with standard connectors: 8mm
• PCB thickness: 1.6mm

Figure 6: Physical dimensions of the TE0741 module. All dimensions are shown in millimeters.

Weight

19 g - Plain module.

8.8 g - Set of nuts and bolts.

Revision History

Hardware Revision History

Hardware revision number is written on the PCB board together with the module model number separated by the dash.

Figure 7: TE0741 PCB revision number.

Document Change History

Date	Revision	Contributors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3589#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]		Jan Kumann	New power-on diagram. Few improvements. Template revision added.
2017-07-20	v.57	John Hartfiel	Correction: PLL  default output CLKs.
2017-06-07	v.55	Jan Kumann	Minor formatting
2017-06-02	v.50	Jan Kumann	REV03 specific update.
2017-01-22	v.42	Jan Kumann	New block diagram added.
2017-01-13	v.38	Jan Kumann	New product images and physical dimension drawings. Formatting improvements and small corrections.
2017-01-12	v.21	John Hartfiel	Correction: B2B  and FPGA bank location.
2016-12-14	v.19	Ali Naseri	TRM revision.
2013-12-02	v.1	Antti Lukats, Jon Bean	Initial version.

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