Table of Contents
Overview
The Trenz Electronic TE0723 is a Arduino compatible FPGA module based on the Xilinx Zynq XC7Z010 SoC.
Key Features
- Xilinx Zynq XC7Z010 SoC
- Dual ARM Cortex A9
- 512 MByte DDR3L SDRAM
- 16 MByte quad SPI Flash memory
- Hi-speed USB2.0 ULPI transceiver
- 23 FPGA I/O's available on board-to-board connectors
- Micro SD Card socket with card detect signal
- Micro USB OTG
- On-board USB JTAG and UART
- RGB LED (connected to PL I/O)
- "Done" LED (inverted polarity)
- CERN Open Hardware Licence 1.2
Additional assembly options are available for cost or performance optimization upon request.
Block Diagram
Figure 1: TE0723 block diagram
Main Components
Figure 2: Main components of the TE0723 module
- Xilinx Zynq XC7Z010 SoC, U1
- 4 Gbit DDR3L 256M x 16 SDRAM, U2
- 16 MByte quad SPI Flash memory, U5
High-speed CMOS logic analog multiplexer/demultiplexer, U10
- 1 MHz low-power operational amplifier, U11
- Dual high-speed USB to multipurpose UART/FIFO, U3
- 0.5A dual-channel current-limited power switch, U21
- Low-power programmable oscillator @ 12.000000 MHz, U7
- 2-Kbit Microwire compatible serial EEPROM, U6
- 10-pin header, J1
- 8-pin header, J2
- 10-pin header, J3
- Analog input header, J4
- 2 x 4-pin header, J5
- PMod 2x6 interface header, J6
- USB host mode jumper, J7
- Micro USB 2.0 Type-B receptacle, J8
- Micro USB 2.0 Type-B receptacle, J9
- Micro SD card connector with detect signal, J10
- Analog input select jumper, J11
- 5V supply power input, J12
- Reset switch, S1
- Red LED, D2
- Green LED, D6
- Green LED, D7
- Ultra-low supply-current voltage monitor, U23
1A PowerSoC DC-DC converter (3.3 V), U20
- 1A PowerSoC DC-DC converter (1.8 V, U19
- 1A PowerSoC DC-DC converter (1.35 V), U16
- Hi-speed USB 2.0 ULPI transceiver, U18
- Low-power programmable oscillator @ 52.000000 MHz, U14
- 1A PowerSoC DC-DC converter (1.0 V), U17
- JTAG interface testpoints, TP1-TP4
Initial Delivery State
Storage device name | IC | Content | Notes |
|---|---|---|---|
Quad SPI Flash | U5 | Empty | - |
| Configuration EEPROM | U6 | Empty | - |
Table 1: Initial delivery state of programmable devices on the module
Boot Process
The 7 boot mode strapping pins (MIO2 ... MIO8) of the Xiliny Zynq Z-7010 device are hardware programmed on the board. They are evaluated by the Zynq device soon after the 'POR_B'.signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).
The TE0723 Zynq board is hardware programmed to boot initially from the on-board QSPI Flash memory U5. The JTAG interface of the module is provided for storing the data to the QSPI Flash memory through the Zynq device.
Signals, Interfaces and Pins
I/O Signals
Overview of the Zynq SoC PS/PL banks I/O signals connected to the external connectors:
| Bank | Type | Connector | I/O Signal Count | Voltage | Notes |
|---|---|---|---|---|---|
| 34 | HR | J1 | 8 | 3.3V | Signal Schematic names: 'SCL', 'SDA', 'D8' ... 'D13' |
| 34 | HR | J2 | 8 | 3.3V | Signal Schematic names: 'RXD', 'TXD', 'D2' ... 'D7' |
| 34 | HR | J6 | 8 | 3.3V | Signal Schematic names: 'PIO01' ... 'PIO08' |
| 35 | HR | J4 | 6 | 3.3V | Signal Schematic names: 'AIN0' ... 'AIN5' |
| 35 | HR | J5 | 1 | 3.3V | Connector dedicated to ESP8266 module |
| 500 | MIO | J10 | 7 | 3.3V | SDIO interface to SD Card socket |
| 501 | MIO | J5 | 4 | 3.3V | Connector dedicated to ESP8266 module |
Table 2: Overview of the Zynq SoC's PS/PL banks I/O signals
Zynq SoC I/O Banks
| Bank | Type | VCCIO | I/O Signal Count | Available on Connectors | Notes |
|---|---|---|---|---|---|
| 34 | HR | 3.3V | 44 | 24 | 8 user I/O's on Pmod connector J6, female pin header J1 and J2 each. |
| 35 | HR | 3.3V | 8 | 7 | 6 user I/O's on female pin header J4, 1 user I/O on female pin header J5. |
| 500 | PS MIO | 3.3V | 15 | 0 | 6 MIO-pins used for QSPI flash memory interface, 7 MIO-pins used for SD Card interface, 1 MIO-pin connected to red LED D2. |
| 501 | PS MIO | 3.3V | 16 | 4 | 12 MIO-pins used for USB ULPI interface, 4 MIO-pins used for ESP8266 interface header J5. |
| 0 | Config | 3.3V | 5 | 0 | 4 I/O's are dedicated to JTAG interface, 'PROG_B'-signal is connected to voltage monitor circuit 23. |
Table 3: General overview of Zynq SoC PL/PS I/O banks
JTAG Interface
JTAG access to the Xilinx Zynq XC7Z010 SoC is provided through FTDI USB/UART FIFO bridge connected to the Micro USB2 connector J9.
Quad SPI Interface
Quad SPI Flash (U5) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.
| Zynq SoC's Pin | Signal Name | U5 Pin |
|---|---|---|
| Bank 500, pin MIO1 | SPI0_CS | 1 |
| Bank 500, pin MIO2 | SPI0_DQ0/MIO2 | 5 |
| Bank 500, pin MIO3 | SPI0_DQ1/MIO3 | 2 |
| Bank 500, pin MIO4 | SPI0_DQ2/MIO4 | 3 |
| Bank 500, pin MIO5 | SPI0_DQ3/MIO5 | 7 |
| Bank 500, pin MIO6 | SPI0_SCK | 6 |
Table 4: Quad SPI interface signals and connections
SD Card Interface
TE0723 module has on-board 3.3V SD Card socket (J10) with card detect switch wired to the SoC PS MIO bank 500.
| Zynq SoC's Pin | Connected To | Signal Name |
|---|---|---|
| Bank 500, pin MIO0 | J10-9 | Card detect switch |
| Bank 500, pin MIO10 | J10-7 | DAT0 |
| Bank 500, pin MIO11 | J10-3 | CMD |
| Bank 500, pin MIO12 | J10-5 | CLK |
| Bank 500, pin MIO13 | J10-8 | DAT1 |
| Bank 500, pin MIO14 | J10-1 | DAT3 |
| Bank 500, pin MIO15 | J10-2 | CD/DAT3 |
Table 4: SD card socket signals
USB Interface
| Zynq SoC's Pin | Connected To | Signal Name |
|---|---|---|
| Bank 501, pin MIO28 | U18-7 | OTG-DATA4 |
| Bank 501, pin MIO29 | U18-31 | OTG-DIR |
| Bank 501, pin MIO30 | U18-29 | OTG-STP |
| Bank 501, pin MIO31 | U18-2 | OTG-NXT |
| Bank 501, pin MIO32 | U18-3 | OTG-DATA0 |
| Bank 501, pin MIO33 | U18-4 | OTG-DATA1 |
| Bank 501, pin MIO34 | U18-5 | OTG-DATA2 |
| Bank 501, pin MIO35 | U18-6 | OTG-DATA3 |
| Bank 501, pin MIO36 | U18-1 | OTG-CLK |
| Bank 501, pin MIO37 | U18-9 | OTG-DATA5 |
| Bank 501, pin MIO38 | U18-10 | OTG-DATA6 |
| Bank 501, pin MIO39 | U18-13 | OTG-DATA7 |
Table 5: USB interface.
ESP Wi-Fi Interface
Interface for the ESP8266 Wi-Fi module is provided through connector J5.
| Zynq SoC's Pin | Connected To | Signal Name |
|---|---|---|
| Bank 501, pin MIO48 | J5-2 | ESP_TXD |
| Bank 501, pin MIO49 | J5-7 | ESP_RXD |
| Bank 501, pin MIO52 | J5-6 | MOD_RST |
| Bank 501, pin MIO53 | J5-3 | ESP_GPIO0 |
| Bank 35, pin G15 | J5-5 | ESP_GPIO2 |
Table 6: ESP8266 Wi-Fi module interface.
I2C Interface
I2C interface pins SCL and SDA from the Zynq SoC PL bank 34 are connected to the connector J1. There are no on-board I2C slave devices.
| Zynq SoC's Pin | Connected To | Signal Name |
|---|---|---|
| R13 | J1-9 | SDA |
| P13 | J1-10 | SCL |
Table 7: Zynq SoC I2C interface.
On-board Peripherals
DDR Memory
TE0723 module has up to 512-MBytes of DDR3L SDRAM arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM. Different memory sizes are available optionally.
Quad SPI Flash Memory
On-board quad SPI Flash memory S25FL127S (U5) is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application storage. All four SPI data lines are connected to the Zynq SoC's PS, allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the bus width and clock frequency used.
Dual High-speed USB to Multipurpose UART/FIFO
FT2232H... U3.
High-speed USB ULPI PHY
Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq SoC's PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 3.3V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).
Microwire Serial EEPROM
There is a 2-Kbit (128 x 16-bit organization) Microwire compatible serial EEPROM 93AA56B (U6) connected to the FTDI FT2232H dual high-speed USB to multipurpose UART/FIFO (U3). This external EEPROM allows each of the FTDI FT2232H chip’s channels to be independently configured as a serial UART (RS232 mode), parallel FIFO (245) mode or fast serial (optical isolation). The external EEPROM can also be used to customize the USB VID, PID, serial number, product description strings and power descriptor value of the FT2232H for OEM applications. Other parameters controlled by the EEPROM include remote wake up, soft pull down on power-off and I/O pin drive strength.
High-Speed Analog Multiplexer
TE0723 module has a on-board TI CD74HC4051 high-speed CMOS logic analog multiplexer (U10) with 8 analog inputs from connectors J4 and J11, and single analog output connected to the operational amplifier (see next section).
Low-power Operational Amplifier
8-input analog multiplexer output is connected to the on-board Microchip Technology MCP6001 operational amplifier (U11). Amplifier output is connected to the Zynq SoC's PS bank 0, XADC dedicated differential analog input pins VP_0 and VN_0.
Oscillators
The module has following reference clock signals provided by on-board oscillators:
| Source | Signal | Frequency | Destination | Pin Name | Notes |
|---|---|---|---|---|---|
| U14 | PS_CLK | 52.000000 MHz | U1 | PS_CLK_500 | Zynq SoC PS subsystem main clock. |
| U14 | OTG-RCLK | 52.000000 MHz | U18 | REFCLK | USB3320C PHY reference clock. |
| U7 | OSCI | 12.000000 MHz | U3 | OSCI | FT2232H oscillator input. |
Table 8: Reference clock signals.
On-board LEDs
There are three LEDs on-board TE0723:
| LED | Color | Connected To | Description and Notes |
|---|---|---|---|
| D2 | Red | MIO9, U1 | User LED. |
| D6 | Green | U1, bank 34 pin G14 | FPGA_LED |
| D7 | Green | 3.3V | PWR_LED, power-on LED. |
Table 9: On-board LEDs.
Power and Power-On Sequence
Power Supply
5V power can be supplied by the external power supply through connector J12 or via USB connection to the host system through USB connector J8 or J9. Minimum current capability of 1A for external power supply is recommended.
Power Consumption
Power consumption is to be determined by the user and depends on SoC's FPGA design and connected hardware.
Power-On Sequence
There is no specific power-on sequence, system will power-up automatically when 5V is present either through J8, J9 or J12.
Variants Currently in Production
| Module Variant | Xilinx Zynq SoC | DDR3L SDRAM | ARM Cores | PL Cells | LUTs | Flip-Flops | Block RAM | DSP Slices |
|---|---|---|---|---|---|---|---|---|
| TE0723-02 | XC7Z010-1CLG225C | 128 MBytes | Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 |
| TE0723-03M | XC7Z010-1CLG225C | 512 MBytes | Dual-core | 28K | 17,6K | 35,2K | 2.1 MBytes | 80 |
| TE0723-03-07S-1C | XC7Z007S-1CLG225C | 512 MBytes | Single-core | 23K | 14,4K | 28,8K | 1.8 MBytes | 66 |
Table 10: Module variants.
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
VIN supply voltage | -0.5 | 3.6 | V | Xilinx datasheet DS187. |
Storage temperature | -40 | +85 | °C |
Table 11: TE0723 module absolute maximum ratings.
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
| Supply voltage | 1.14 | 3.465 | V | Xilinx datasheet DS187. |
Table 12: TE0723 module recommended operating conditions.
Assembly variants for higher storage temperature range are available on request.
Physical Dimensions
Module size: 68.58 mm × 53.34 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1.6 mm.
Highest part on PCB: approx. 4 mm. Please download the step model for exact numbers.
Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.
Figure 3: TE0723 module physical dimensions.
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Revision History
Hardware Revision History
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| 2016-07-15 | 03 | Click to see PCN. | TE0723-03 | |
2015-11-06 | 02 | TE0723-02 | ||
01 |
|
Table 13: TE0723 hardware revision history.
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Document Change History
Date | Revision | Contributors | Description |
|---|---|---|---|
Jan Kumann | Initial document. |
Table 14: Document change history.
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