TEM0002

Overview

The Trenz Electronic TEM0002-01 SmartBerry with Raspberry Pi form factor, is an industrial-grade module based on Microsemi SmartFusion2 SoC (System on a Chip). The Module has 128MB DDR3 SDRAM, a Gigabit Ethernet PHY, four PMODs, a GPIO Pin header compatible to the Raspberry Pi pinout and a Micro USB to UART interface. SmartFusion2 combines a 166 MHz Cortex-M3 core with 256 KByte Flash, 80 KByte SRAM  and a 12 kLUT FPGA core logic.

Key Features

• Microsemi SmartFusion2 SoC FPGA (M2S010)
• 128 MByte DDR3 SDRAM
• On board power converters for all needed voltages
• 40 pin header (compatible to Raspberry Pi pinout)
• 4 x 12 pin PMODs
• Gigabit Ethernet PHY with RGMII interface
• JTAG and UART via Micro USB
• 3 pin header for Live Probes
• 2 x User Button
• 2 x status LED
• 1 x  RGB LED
  
  

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TEM0002-01 block diagram.

Main Components

Figure 2: TEM0002-01 main components.

1. Microsemi SmartFusion2 SoC FPGA, U2
2. USB to UART/FIFO (FTDI FT2232H), U3
3. Gigabit ETH connector, J2
4. 4x  2x6 pin PMOD, P1, P2, P3, P4
   
5. GPIO pin header compatible to Raspberry Pi, J8
6. Micro USB 2.0, J1
7. EEPROM 4KBIT (M93C66-R), U6
8. 2x User Button, S4, S5
9. RGB LED, D3
10. LED red, D1 and green, D2
11. Live Probe pins, J4
12. Reset jumper, J13
13. JTAG select jumper, J6
14. Board power header, J5
15. 1Gb DDR3/L SDRAM, U5
16. MicroSD memory card connector, J3
17. Gigabit Ethernet PHY, U1

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module.

Boot Process

The SmartBerry supports

Signals, Interfaces and Pins

I/Os

I/O signals provided on the Rasperry Pi compatible header are connected to bank 2 of the Microsemi SoC.

Table 2: General overview of I/O signals connected to the SoC.

Further I/Os are provided via the PMOD connectors descriebed below.

PMODs

The module provides four 2x6 female PMOD connectors. Two of the headers (P2 and P3) are arranged to use as dual 12 pin PMOD. According to the standard on all four headers Pin 5 and 11 are connected to ground, 6 and 12 to 3.3V.

JTAG Interface

JTAG access to the SoC components is provided through the micro usb connector via the FTDI usb to UART bridge. Depending on the jumper J6 the JTAGSEL signal SW3 switches the JTAG interface to either the FPGA fabric TAP (OPEN, high) or the Cortex-M3 JTAG debug interface (CLOSED, low). JTAG signals are powered by 3.3V.

Table 5: JTAG interface signals.

SD Card Interface

The SD Card interface is connected to Bank 2 of the SoC

Table 6: SD Card interface signals and connections.

Ethernet Interface

Table 7: Ethernet PHY signals and connections.

I2C Interface

There are no on-board I²C devices.  For Raspberry Pi compability the device detection I²C bus is routed from the header J8-27/28 to Bank 1 U2-A20/A19 (SDA/SCL). 

Table 8: I²C slave device addresses.

On-board Peripherals

DDR Memory

TEM0002 has 1Gb industrial grade DDR3 SDRAM (U5). A 16-bit wide memory bus providing total of 128 MBytes of on-board RAM. Specification is 800 MHz clocking resulting in 1600 Mb/s data rate and timings  of 11-11-11 (CL-T_RCD-T_RP).

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (J2) is provided by  Microsemi VSC8531 chip (U1). The Ethernet PHY RGMII interface is connected to Bank 6 of the Microsemi SOC. I/O voltage is fixed at 1.5V. The reference clock input of the PHY is supplied from an external 25.000000 MHz oscillator (U11).

Oscillators

The module has following reference clock signals provided by on-board oscillators:

Table 9: Reference clock signals.

In REV02, Y1 will be replaced by a 12 MHz crystal.

On-board LEDs

Table 10: On-board LEDs.

Power and Power-On Sequence

There is no specific power on Sequence. Just supply with 5V via the micro USB J1 or the J5 PWR_IN with current rating sufficient for your Design.

Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Table 11: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

Figure 3: Module power distribution diagram.

Power Rails

Table 12: Module power rails.

Bank Voltages

Table 13:  I/O bank voltages.

Board to Board Connectors

Variants Currently In Production

NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.

Table : Module variants.

Technical Specifications

Absolute Maximum Ratings

Table : Module absolute maximum ratings.

Recommended Operating Conditions

Table : Module recommended operating conditions.

Operating Temperature Ranges

Industrial grade: 0°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 85 mm × 56 mm.  Please download the assembly diagram for exact numbers.

• PCB thickness: 1.55 mm.

• Highest part on PCB: top approx. 13.3 mm (Ethernet), bottom 1.57mm (SD-Card)Please download the step model for exact numbers.

All dimensions are given in millimeters.

Figure : Module physical dimensions drawing.

Revision History

Hardware Revision History

Table : Module hardware revision history.

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Figure : Module hardware revision number.

Document Change History

Date	Revision	Contributors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy241.$Proxy3496#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]		Martin Rohrmüller	Under construction.
2017-05-30	v.1	Jan Kumann	Initial document.
	all	Jan Kumann, John Hartfiel

Table : Document change history.

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