Table of contents
Overview
Key Features
- EDDP with TE0706
- ...
Revision History
| Date | Vivado | Project Built | Authors | Description |
|---|---|---|---|---|
| 2018-01-31 | 2017.1 | initial release |
Release Notes and Know Issues
| Issues | Description | Workaround | To be fixed version |
|---|---|---|---|
| No known issues | --- | --- | --- |
Requirements
Software
| Software | Version | Note |
|---|---|---|
| PetaLinux | 2017.1 | needed |
| SDx | 2017.1 | needed |
Hardware
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
| Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
|---|---|---|---|---|---|---|
| TE0720-03-2IF | TE0720_2IF | REV03 | 1 GB | 32 | ||
| TE0720-03-l1if | TE0720_L1IF | REV03 | 512MB (L) | 32 | ||
| TE0720-03-1CF | TE0720_1CF | REV03 | 1 GB | 32 | ||
| TE0720-03-2EF | TE0720_2EF | REV03 | 1 GB | 32 | ||
| TE0720-03-07S | TE0720_07S | REV03 | 1 GB (L) | 32 |
Design supports following carriers:
| Carrier Model | Notes |
|---|---|
| TE0706-2 |
Additional HW Requirements:
Content
For general structure and of the reference design, see Project Delivery
Design Sources
| Type | Location | Notes |
|---|---|---|
| Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
| SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
| PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
| SDSoC | <design name>/../SDSoC_PFM | SDSoC Platform will be generated by TE Scripts or as separate download |
Additional Sources
| Type | Location | Notes |
|---|---|---|
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Hardware Setup
On TE0706-02 carrier board, use jumpers J10, J11 and J12 to select 3.3V:
Jumper Settings J10 Short 2-3 J11 Short 2-3 J12 Short 2-3 On TE0706-02 carrier board, set switch S1 to:
Switch Settings S1_1 OFF S1_2 OFF S1_3 OFF S1_4 ON On TE0790-02 XMOD FTDI JTAG Adapter of the TE0706-02 board, set switch S2 to:
Switch Settings S2_1 ON S2_2 OFF S2_3 ON S2_4 OFF IMPORTANT
Before connecting to TEC0053-04 by PMOD 12pin cables, power on the TE0706-02 (NOTE: 5V!) and measure presence of 3.3V voltage on the TE0706-02 connector J5 pins: J5:5, J5:6, J5:45, J5:46.
Connection of motor rotation encoder
Motor rotation encoder is connected to the TEC0053-04 - EDPS Power Stage Pmod 6 pin cable connector kit. See the orientation and position of the 5 wire connection. There are 6 pins on the TEC0053-04 board. There are only 5 pins on the motor encoder. Pin 1 connects to pin 1. 6-th wire is unconnected on the motor encoder side.
3-phase of the motor phase wires are connected to the TEC0053-04 Power Stage points A, B, C: A: green wire; B: red wire; C: black wire.
All other motor wires are unused.
The TEC0053-04 - EDPS Power Stage can be powered by 12 V from the power supply by separate wire connecting of the point labled “PWR” (see above) with the fused point labeled “+DC” (see the first picture).Connect TE0706 with TEC0053-04 by two PMOD 12-pin cables.
Description of connections of TE0706 with TEC0053-04# First 12 pin PMOD cable # Connections of TEC0053 J17 with TE0706-02 J5 # TEC0053 # TE0706-02 # GND # J17:25 # J5:50 set_property PACKAGE_PIN G20 [get_ports {SCLK}]; # J17:23 # J5:48 # 3,3V # J17:21 # J5:46 set_property PACKAGE_PIN E21 [get_ports {SDI1}]; # J17:19 # J5:44 set_property PACKAGE_PIN B19 [get_ports {SDI2}]; # J17:17 # J5:42 set_property PACKAGE_PIN D20 [get_ports {SDI3}]; # J17:15 # J5:40 # GND # J17:26 # J5:49 set_property PACKAGE_PIN G21 [get_ports {SDV}]; # J17:24 # J5:47 # 3,3V # J17:22 # J5:45 set_property PACKAGE_PIN D21 [get_ports {ENC_A}]; # J17:20 # J5:43 set_property PACKAGE_PIN B20 [get_ports {ENC_B}]; # J17:18 # J5:41 set_property PACKAGE_PIN C20 [get_ports {ENC_I}]; # J17:16 # J5:39 # All signals connected by the first PMOD cable cable belong to TE0720 Zynq Bank 35. # Second 12 pin PMOD cable # Connections of TEC0053 J17 with TE0706-02 J5 # TEC0053 # TE0706-02 # GND # J17:1 # J5:2 # Not used in the design # J17:3 # J5:4 # 3,3V # J17:5 # J5:6 set_property PACKAGE_PIN W17 [get_ports {GH[2]}]; # J17:7 # J5:8 set_property PACKAGE_PIN W20 [get_ports {GH[1]}]; # J17:9 # J5:10 set_property PACKAGE_PIN AA16 [get_ports {GH[0]}]; # J17:11 # J5:12 # GND # J17:2 # J5:1 # Not used in the design # J17:4 # J5:3 # 3,3V # J17:6 # J5:5 set_property PACKAGE_PIN W18 [get_ports {GL[2]}]; # J17:8 # J5:7 set_property PACKAGE_PIN W21 [get_ports {GL[1]}]; # J17:10 # J5:9 set_property PACKAGE_PIN AB16 [get_ports {GL[0]}]; # J17:12 # J5:11 #All signals connected by the second PMOD cable belong to TE0720 Zynq Bank 33. # Second PMOD Cable 12-pin contains these two wires unconnected to the SDSoC design: # Unused connections of TEC0053 J17 with TE0706-02 J5 # TEC0053 # TE0706-02 #set_property PACKAGE_PIN W16 [get_ports {gpio_0_tri_io[1]}]; # J17:3 # J5:4 #set_property PACKAGE_PIN Y16 [get_ports {gpio_0_tri_io[0]}]; # J17:4 #J5:3
TE0706-02 carrier board has highlighted position of two 12 pin PMOD cables. Please take care, when connecting both cables to respect pin connections as listed above.
TEC0053-04 power stage board has highlighted position of two 12 pin PMOD cables.IMPORTANT
Wrong placement of the PMOD 12pin connects might result in a damaged electronic.
Design Setup
Launch
References
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
| Date | Document Revision | Authors | Description |
|---|---|---|---|
| |||
| 2018-08-15 | v.1 |
| |
| All |
Legal Notices
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