TEC0850 TRM

Overview

The Trenz Electronic TEC0850 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+ MPSoC, with 64-bit wide SODIMM DDR4 SDRAM, max. Dual 512 MByte Flash memory for configuration and operation. 24 Gigabit transceivers on PL side and 4 PS side. Powerful switch-mode power supplies for all onboard voltages. A large number of configurable I/Os. 3U form factor.

Board Component Descriptions

Zynq UltraScale XCZU15EG MPSoC

The TEC0850 board is populated with the Zynq UltraScale+ XCZU15EG-1FFVB1156E MPSoC.

I/O Interfaces

Main IO interfaces are shown on the image below.

PS MIO Configuration

MIO	Interface
MIO 0...12	QSPI Flash Memory
MIO 20...21	I2C 1
MIO 22...23	UART 0
MIO 26...37	GEM 0
MIO 46...51	SD 1
MIO 52...63	USB 0
MIO 64...75	USB 1
MIO 76...77	MDIO 0

DDR4 SODIMM Socket

The Zynq UltraScale+ DDRC hard memory controller is wired to the DDR4 SODIMM Socket U3.

Quad-SPI Flash Memory

Board has two N25Q512A11G1240E connected in a dual parallel mode.

I2C

The onboard I2C bus is connected to MIO 20...21 pins. Devices on the bus shown in the table below.

I2C address	Chip	Description
0x50	U63 24AA128T-I/ST	128K Serial EEPROM
0x53	U64 24AA025E48T-I/OT	2K Serial EEPROM with EUI-48™ or EUI-64™ Node Identity
0x69	U14 Si5345	Clock generator and distributor

UART and JTAG

Board has USB-UART bridge based on FTDI FT2232 chip. Use of this feature requires that USB driver is installed on your host PC. UART0 with MIO 22 .. 23 should be selected in "Zynq UltraScale+ MPSoC" configuration.

The Digilent plug-in software and cable drivers must be installed on your machine for you to be able to use JTAG interface.

Ethernet

Board has Marvell Alaska 88E1512 Ethernet PHY which use MDIO address 1.

SD

There are some limitations to use SD card Interface in Linux.

Zynq UltraScale+ SD controller is working only in the 3.3V mode as it connected to SD card socket using 1.8V to 3.3V level shifter U10.
Micro SD card socket has no "Write Protect" switch.

To force Linux driver not to use this features add following instructions to device tree file.

&sdhci1 {

no-1-8-v;
disable-wp;
};

USB

Board has 3 USB interfaces.

Front panel Micro-USB Interface

This interface provides access to UART and JTAG functions via FTDI FT2232 chip.

Front panel USB-C Interface

This interface connected to USB FIFO bridge chip FT601Q. 32-bit FIFO bridge provides a simple high-speed interface to Zynq UltraScale+ PL.

Backplane USB Interface

Zynq UltraScale+ USB controller connected to backplane connector J1C via USB PHY chip U11.

DACs

Board has 4 8-bit parallel Texas Instruments THS5641 DACs with up to 100 MSPS Update Rate.

MGT

The TEC0850 board has 30 MGT lines routed to backplane connectors.

Bank	Connector	Lanes
PL 128	J4G and J4H	4
PL 129	J5A and J5B	4
PL 130	J5C and J5D	4
PL 230	J4G and J4H	4
PL 229	J5A and J5B	4
PL 228	J5C and J5D	4
PS 505	J1A	4

MGT reference clocks are connected to banks 129, 229 and 505. Banks 128 and 130 should share clock from bank 129, banks 230 and 228 from bank 229.

DIP-Switches

S1

Switch	Description
1	Boot Mode 0
2	Boot Mode 1
3	Boot Mode 2
4	Boot Mode 3

See Zynq UltraScale+ Device Technical Reference Manual page 236 for full boot modes description. Most common modes are

Boot Mode	SW1:4	SW1:3	SW1:2	SW1:1
JTAG Boot Mode	ON	ON	ON	ON
Quad-SPI	ON	ON	ON	OFF
SD Card	ON	ON	OFF	OFF

S2

Switch	Description
1	SC JTAGEN
2	EEPROM WP (Write protect)
3	FPGA PUDC
4	SC Switch (Reserved for future use)

LEDs

LED	Signal	Chip	Pin	Description
Front panel LED 1 (Red)	LED_FP_1	FPGA U1	AF15	PL User defined LED
Front panel LED 2 (Green)	LED_FP_2	FPGA U1	AG15	PL User defined LED
Front panel LED 3 (Green)	LED_FP_3	FPGA U1	AE15	PL User defined LED
Front panel LED 4 (Green)	LED_FP_4	SC U18	M4	Power Good

Trenz Electronic Documentation