Table of contents
CPLD Access
Set B2B Pin JM1-89 (JTAGEN) to VDD (3.3V)
With TE0701:
- not possible on TE0701-01 up to TE0701-06
With TE0703 and TE0703 default CPLD firmware:
- Connect MiniUSB cable to J4
- Set DIP Switch S2-2 to OFF and S2-3 to ON position, see TE0703 CPLD - CC703S#CC703S-JTAG
- Power ON the board
- Run "Lattice Diamond Programmer"
Select "Create new project from JTAG chain" and press "OK"
With TE0705:
- Connect MiniUSB cable to J7
- Set DIP Switch S3-ENJTAG, S3-M1 and S3-M2 to ON position, see TE0705 CPLD#JTAG
- Power ON the board
- Run "Lattice Diamond Programmer"
Select "Create new project from JTAG chain" and press "OK"
With TE0706:
- Connect MiniUSB cable to XMOD
- Set DIP Switch S1-2 to OFF position, see TE0706 TRM#4-bitDIP-switch
- Power ON the board
- Run "Lattice Diamond Programmer"
Select "Create new project from JTAG chain" and press "OK"
Available CPLD Firmware
- TE0820 CPLD - Firmware description with different Variants for PCB REV03 and newer
- QSPI / SD Boot Modi - Default delivered, QSPI or SD Boot Mode is selectable (Special FSBL for QSPI Programming with Boot Mode /= JTAG will be provided for Vivado 2017.4 Reference Design and newer).
- QSPI / JTAG Boot Modi - Use QSPI or JTAG Boot Mode is selectable
- JTAG / SD Boot Modi - SD or JTAG Boot Mode is selectable
- JTAG / QSPI / SD Boot Modi - QSPI, SD or JTAG Boot Mode is selectable (CPLD Pin 23 (NOSEQ) is used as second Boot Mode pin to select JTAG Boot Mode). Attention: This need 7 Series 4x5 Carrier CPLD Firmware update.
- TE0820-REV01_REV02 CPLD - Firmware description with different Variants
- QSPI / SD Boot Modi - Default delivered, QSPI or SD Boot Mode is selectable (Special FSBL for QSPI Programming with Boot Mode /= JTAG will be provided for Vivado 2017.4 Reference Design and newer).
- QSPI / JTAG Boot Modi - Use QSPI or JTAG Boot Mode is selectable
- JTAG / SD Boot Modi - SD or JTAG Boot Mode is selectable
- JTAG / QSPI / SD Boot Modi - QSPI, SD or JTAG Boot Mode is selectable (CPLD Pin 23 (NOSEQ) is used as second Boot Mode pin to select JTAG Boot Mode). Attention: This need 7 Series 4x5 Carrier CPLD Firmware update.
Download
- TE0820/<PCB Revision>/Firmware/
- Use files from the subfolders of your PCB revision
General instructions
CPLD Firmware Update - General Requirements
- Lattice Diamond or Lattice Diamond Programmer is available for free on http://www.latticesemi.com/
- Lattice compatible JTAG Programmer, for example:
- Trenz TE0790 or Carrier with FTDI for JTAG
- Most JTAG programmer, which used FTDI Chip to translate USB to JTAG
- Digilent FTDI based programmer are not compatible with Lattice.
- JTAG must be connected to CPLD JTAG
- JTAG Enable Pin of CPLD must be selectable and set to VDD
- Correct CPLD Firmware (JED-File) from Trenz Electronic Download
CPLD Firmware Update - General Procedure
Important:
- Connect only one JTAG device to host PC.
- Close all other JTAG programs, like Xilinx tools (on WinOS check hw_server.exe is terminated).
Procedure:
- Enable CPLD JTAG access (See JTAG section on CPLD Firmware description)
- Connect JTAG
- Power on System
- Open Lattice Diamond Programmer
- Detect Cable and click "Ok"
For some devices second Port must be selected: - Select Device (See CPLD Firmware overview description).
In the most cases select the correct detected device one time (it's yellow at first on the menue) - Select correct Firmware from Download Area (JED File)
- Program CPLD:
- Disable CPLD JTAG access (See JTAG section on CPLD Firmware description)
- Restart System
More Information are available on the CPLD Firmware description and on the readme.txt included into the download zip.
Overview
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