Board bring-up overview for TEI0022

Introduction

Bringing-up SoC boards can be board dependent. Therefore, an overview introducing into the basic requirements to bring-up the board TEI0022 could be very helpful. To reach this goal this guide shows users with basic knowledge of computers, basic ideas of FPGAs, and Software Design Tools, a detailed insight into the required steps to create the necessary files for booting the Hard Processor System (HPS) of an Intel Cyclone V SoC from an SD card.

The whole design process needs several tools, whereby output files and folders from one step are essential for the next processing step. Therefore, each step can be handled independently with its complexity. The usage of tools will be described in sequential order, according to the necessary path, booting the HPS. This process is described by showing the requirements in the next section. The following section displays the necessary steps withing the tool "Intel Quartus Project" (Step 1). After that, the generation of the preloader and the main bootloader from u-boot sources (Step 2) is shown, followed by the generation of the device tree blob (Step 3). Then, the SD card setup for the Intel Cycone V HPS (Step 4) is delivered and finally, references for further information are mentioned.

Requirements

The requirements for bring-up the HPS in the Intel Cyclone V SoC consists of the following tools:

• Intel® Quartus® Prime Lite - Version 18.1 build 625
• Intel® Soc FPGA Embedded Development Suite (Soc EDS) - Version 18.1 build 625
• Linux Installation(, whereby the Windows Subsystem for Linux is not suitable)

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This step by step guide covers the tools and console commands for Windows users. The programs and tools this guide uses
are Linux based. Intels approach for making these Linux tools accessible to Windows users is the wrapper Cygwin, because of
that, the steps and console commands in a Linux environment are nearly identical.

All required Editors and tools are part of the Intel FPGA Design software packages.

Only the SD card build requires low level access to the SD card and can therefore only be performed in native Linux environment.

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Step 1 - Intel Quartus Project

The first step within the HPS booting procedure is using the tool "Intel Quartus". Within this tool it is necessary to create a new project. After that, it is mandatory to configure the resources (system memory and SD card access) withing the Plattform Designer. After that, connect the basis interfaces (UART, I2C) of the HPS to the board resources and compile the project to create the ".sopinfo", the ".qip" files, and the "handoff" folder. Refer to "Intel Quartus project" for more detailed information.

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 - Setup a project in Quartus Prime Lite (folder: project and project name: HPSexample)

 - Use the Plattform Designer to configure the resources needed to boot the HPS
    (System Memory and SD card access)

 - Connect the basic interfaces (Uart and i²c) of the HPS to the board resources

 - Compile the project to get the required files and folders for the next steps
    HPSexample.sopinfo / PlattformEditorHPS.qip file and (hps_isw_)handoff folder

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Step 2 - Preloader/Bootloader generation

After the generation of the Intel Quartus project, it is necessary to handle the SoC booting. The boot process, according to the next figure, consists of several steps:

• BootROM:

The BootROM is hard coded into the chip. Its purpose is to detect the selected boot source and to perform a minimal HPS setup. After that the preloader can be loaded into the On Chip RAM (OCRM) and can be executed.

• Preloader:

While executing the preloader, a further HPS and SDRAM initialization can be done. After that, the bootloader can be loaded and executed.

• Bootloader:

The bootloader loads the linux operating system (OS) or a bare metal application into the RAM and starts them. If a linux OS is loaded, the kernel is loaded which loads the linux root file system.

In the second step, the in the first step generated handoff folder is used to generate the preloader and the main bootloader. Refer to "Preloader/Bootloader generation" for more detailed information.

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[preloader-mkpimage.bin u-boot.img]

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Step 3 - Device Tree Blob Generation

In the third step, the device tree blob is generated with the ".sopfile" file as input from the Plattform Designer in step 1. Refer to "Device Tree Blob Generation" for more detailed information.

Step 4 - SD card setup

In the final step, the SD card setup is created to prepare the boot medium to bring-up the HPS within Intel Cyclone V HPS. Refer to "SD card setup" for more detailed information.

References

In this reference section, further additionally information are delivered for deeper investigation.

• Building Bootloader
• Embedded Linux Beginners Guide
• Embedded Peripherals IP User Guide
• Device Tree Generation
• Generating and Compiling the Preloader
• HPS SoC Boot Guide - Cyclone V SoC Development Kit
• Intel® SoC EDS Support
• Intel® SoC FPGA Embedded Development Suite User Guide
• Introducing the Intel® Quartus® Prime Pro and Standard Edition Software User Guides
• Preloader and U-Boot Customization - v13.1
• U-Boot programming: A tutorial -- Part I
• U-Boot programming: A tutorial -- Part II
• U-Boot programming: A tutorial -- Part III

Videos for SoC HPS System Generation

• Preloader and U-boot Generation for Altery Cyclone V SoC
• SoC HPS Quartus II Integration (HW/SW Hand-off)
• SoC HPS System Generation Using Qsys