Additional Information

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Informationsfragmente:

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Background

• Boot ROM
   - Load the next Boot stage [Preloader / u-boot-spl] into the On chip RAM [OCRAM]
      therefore the preloader / SPL u-boot is limited to 64 kByte on Cyclone 5 devices
  
  
• Preloader
   - Preloader-optins:
          u-boot - SPL
          SoC EDS - MPL [Altera bare-metal libraries - HWLibs]
   - For Cyclone 5 devices, the preloader consists of 4 identical copies. each 64 kB in size,
      256 kb in total
   - When generating the preloader, it can be necessary to manually add a header and checksum
     into the binary, the tool mkpimage can perform these additions
  
  
• Main Bootloader
   - When generating the preloader, it can be necessary to manually add a header and checksum 
     into the binary, the tool mkimage can perform these additions

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Device Tree Blob

Generate   - .dtb or .dts file from .sopcinfo file

Enter into the Shell the following command:
sopc2dts --input HPS.sopcinfo --output DTBsocfpga.dtb --type dtb --board hps_common_board_info.xml --bridge-removal all --clocks

Kurzform:
sopc2dts -i HPS.sopcinfo -o DTBsocfpga.dtb -t dtb --board hps_common_board_info.xml --bridge-removal all --clocks

In case a .dts file is desired, use this command:
sopc2dts -i HPS.sopcinfo -o DTBsocfpga.dts -t dts --board hps_common_board_info.xml --bridge-removal all --clocks

Decompile - .dtb file to .dts file

C:\intelFPGA\18.1\embedded\host_tools\gnu\dtc\   dtc.exe

cd /cygdrive/c/intelFPGA/18.1/embedded/host_tools/gnu/dtc

dtc -I dts -O dtb -o device-tree.dtb devicetree.dts

Generate   - .dts file to .dtb file

cd /cygdrive/c/intelFPGA/18.1/embedded/host_tools/gnu/dtc

dtc -I dtb -O dts -o devicetree.dts soc_system.dtb

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