Template Revision 1.0 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Important General Note:
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Table of contents |
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This demo is a Webserver which utilizes SmartFusion2 SoC ARM Cortex-M3 core, Ethernet, USB / COM-port, Real Time Clock and the on-board LEDs.
The demo is offered in two variants, one which is stored into the embedded nonvolatile memory (eNVM) and the other executed from the external DDR3/L SDRAM memory.
Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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<<============== ABKLÄREN OB BEIDE HW-Revisionen unterstütz werden
Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.
Hardware Requirements:
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Content of the zip archieve:
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Reference Design is only usable with the specified Libero/SoftConsole version. Do never use different versions of Microsemi Software for the same Project.
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Reference Design is available on:
The reference design is available as a prebuild zip archieve, which contains the hard & soft -ware project folders and the board configuration file "microsemi-smartfusion2-smartberry-ddr.cfg" . It was created and tested in windows environment.
The zip archieve must to be extracted. The board configuration file needs to copied into your SoftConsole installation directory. When taking the required SoftConsole version into account, SoftConsole version 6.2, and the default installation path, copy the board configuration file into:
"C:\Microsemi\SoftConsole_v6.2\openocd\share\openocd\scripts\board\"
Connecet the board via usb cable to your demo host computer. Check in the Windows Device Manager the appearence of the tree board driver related devices:
The Device Manager is accesible via "Right mouse click context menue" from the Windows Start Menu Button.
Connect the boards ethernet port to your demo host computer. The demo is confiured to establish a network connection via the DHCP protocol, therefore a free router / network port can be used.
A direct port to port connection between the demo host computer and the board is also possible but requires to reconfigure the software project.
Open Libero 12.4, in the to left corner, open the demo hardware project via "Project > Open Project" and point to file dialog to the demo archieves hardware project dicsk:\Path_to_the_hardware_project_inside_the_archieve\ , double left mouse click onto the project file "Smartberry_Webserver.prjx" to open it.
The board is automatically selected and setup to be flashed by Libero.
In the upper left section of Libero, select the tab "Design Flow" and flash it to the board via "Program Design > and double left mouse click onto Run PROGRAM Action".
Warnings can be ignored.
The hardware design is volatile and therefore lost when powering the board down.
Open SoftConsole 6.2 and point the "Workspace:" to the folder "SmartberrySoftconsole-6.2" inside the demo folder.
Subsequently the program opens.
The SoftConsole display to the left the projects which the Workspace contains.
The two demo projects "Smartberry_Webserver_6.2" and "Smartberry_Webserver_DDR_6.2" are identical variants of the demo, they only differ in the memory location.
The first one is stored in embedded non volatile memory (eNVM) and the later is stored volatile in the external DDR ram and therefore lost during power down.
Before flashing the demo, open a comport terminal to the boards comport, so that its messages about the used IP Adress and Mode can be captured.
To simply run the demo press the triangle right to the button marked with a "R" in the picture above and select the variant of the demo.
Pressing the triangle next to the button marked with "D" let you select which variant to be executed in debug mode.
Debug controlls - Resume - Pause - Stop
Switch between Debug and Run perspective (upper right corner program window)
To disengaging the DHCP mode one has to setup up an IP Address in the code unit "main.c" line 274, a gateway address has is not required.
Furthermore the corresponding compiler flag needs to be deleted (optional renamed) in the project setting. To do so, in the "Project Explorer" tab, right mouse click onto the project and select Properties in the appearing menu.
In the left section of the properties window select "C/C++ Build > Settings" in the right section select the tab "Tool Settings > GNU ARM Cross C Compiler > Preprocessor" under "Defined symbols (-D)" delete the compiler flag "NET_USE_DHCP" and press "Apply". Confirm the following dialog and press "Cancel".
Lastly, the project needs to be recompiled. In the top menu of the SoftConsole select "Project > Build ALL / Build Project".
Warnings can be ignored.
Open a new tab in a web browser and enter the IP Adress from the comport terminal.
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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For basic board setup, LEDs... see: TEBF0808 Getting Started
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Not used in this example.
Not used on this Example.
Hard Disk (optional)
To locate root file system on Hard disk:
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Activated interfaces:
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
#System Controller IP #LED_HD SC0 J3:31 #LED_XMOD SC17 J3:48 #CAN RX SC19 J3:52 B47_L2_P in #CAN TX SC18 J3:50 B47_L2_N out #CAN S SC16 J3:46 B47_L3_N out set_property PACKAGE_PIN J14 [get_ports BASE_sc0] set_property PACKAGE_PIN G13 [get_ports BASE_sc5] set_property PACKAGE_PIN J15 [get_ports BASE_sc6] set_property PACKAGE_PIN K15 [get_ports BASE_sc7] set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io] set_property PACKAGE_PIN B15 [get_ports BASE_sc11] set_property PACKAGE_PIN C13 [get_ports BASE_sc12] set_property PACKAGE_PIN C14 [get_ports BASE_sc13] set_property PACKAGE_PIN E13 [get_ports BASE_sc14] set_property PACKAGE_PIN E14 [get_ports BASE_sc15] set_property PACKAGE_PIN A13 [get_ports BASE_sc16] set_property PACKAGE_PIN B13 [get_ports BASE_sc17] set_property PACKAGE_PIN A14 [get_ports BASE_sc18] set_property PACKAGE_PIN B14 [get_ports BASE_sc19] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19] # PLL #set_property PACKAGE_PIN AH6 [get_ports {si570_clk_p[0]}] #set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}] #set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}] # Clocks #set_property PACKAGE_PIN J8 [get_ports {B229_CLK1_clk_p[0]}] #set_property PACKAGE_PIN F25 [get_ports {B128_CLK0_clk_p[0]}] # SFP #set_property PACKAGE_PIN G8 [get_ports {B230_CLK0_clk_p}] # B230_RX3_P #set_property PACKAGE_PIN A4 [get_ports {SFP1_rxp}] # B230_TX3_P #set_property PACKAGE_PIN A8 [get_ports {SFP1_txp}] # B230_RX2_P #set_property PACKAGE_PIN B2 [get_ports {SFP2_rxp}] # B230_TX2_P #set_property PACKAGE_PIN B6 [get_ports {SFP2_txp}] # Audio Codec #LRCLK J3:49 B47_L9_N #BCLK J3:51 B47_L9_P #DAC_SDATA J3:53 B47_L7_N #ADC_SDATA J3:55 B47_L7_P set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ] set_property PACKAGE_PIN G15 [get_ports I2S_bclk ] set_property PACKAGE_PIN E15 [get_ports I2S_sdin ] set_property PACKAGE_PIN F15 [get_ports I2S_sdout ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ] set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ] |
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For SDK project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
SDK template in ./sw_lib/sw_apps/ available.
TE modified 2019.2 FSBL
General:
Module Specific:
TE modified 2019.2 FSBL
General:
Xilinx default PMU firmware.
Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Note:
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For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Select Image Packaging Configuration ==> Root filesystem type ==> Select SD Card
Changes:
# CONFIG_SUBSYSTEM_BOOTARGS_AUTO is not set
CONFIG_SUBSYSTEM_USER_CMDLINE="console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=1024M"
CONFIG_SUBSYSTEM_DEVICETREE_FLAGS=""
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"
CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_IMAGE_NAME="Image"
Start with petalinux-config -c u-boot
Changes:
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
CONFIG_I2C_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_SYS_EEPROM_SIZE=256
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; bootargs= "console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=1024M"; /* notes: root=/dev/mmcblk1p2 for SD and root=/dev/sda for hard disk will be changed automatically by executing the debian/ubuntu script*/ }; }; /* notes: serdes: // PHY TYP see: dt-bindings/phy/phy.h */ /* default */ /* SD */ &sdhci1 { disable-wp; no-1-8-v; }; /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; phys = <&lane1 4 0 2 100000000>; maximum-speed = "super-speed"; }; /* ETH PHY */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* I2C */ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // SFP TEBF0808 PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { // PCIe #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // SFP1 TEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 {// SFP2 TEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // TEBF0808 EEPROM #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom: eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; i2c@6 { // TEBF0808 FMC #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // TEBF0808 USB HUB #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2cswitch@77 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 PMOD P1 #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // i2c Audio Codec #address-cells = <1>; #size-cells = <0>; reg = <1>; /* adau1761: adau1761@38 { compatible = "adi,adau1761"; reg = <0x38>; }; */ }; i2c@2 { // TEBF0808 Firefly A #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // TEBF0808 Firefly B #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { //Module PLL Si5338 or SI5345 #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { //TEBF0808 CPLD #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { //TEBF0808 Firefly PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // TEBF0808 PMOD P3 #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; }; |
Start with petalinux-config -c kernel
Changes:
CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
Applications will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)
Applications will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)
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No additional software is needed.
File location <design name>/misc/Si5345/Si5345-*.slabtimeproj
General documentation how you work with these project will be available on Si5345
To get content of older revision got to "Change History" of this page and select older document revision number.
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