Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Notes :
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Refer to http://trenz.org/am0010-info for the current online version of this manual and other available documentation.
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
*used as reference |
Design supports following carriers:
*used as reference |
Additional HW Requirements:
*used as reference |
Notes :
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For general structure and usage of the reference design, see Project Delivery - Xilinx devices
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Notes :
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Notes :
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI is the same, except file export to prebuilt folder. |
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
This step depends on Xilinx Device/Hardware for Zynq-7000 series
for ZynqMP
for ...
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Generate Programming Files with Vitis
TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Note:
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_am0010 (optional) |
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup |
Not used on this example.
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used. |
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for Microblaze 1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR for native FPGA ... |
select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
petalinux login: root Password: root |
Note: Wait until Linux boot finished |
You can use Linux shell now.
i2cdetect -y -r 0 (check I2C 0 Bus) i2cdetect -y -r 1 (check I2C 1 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) |
Option Features
Note:
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
Note:
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Note:
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Activated interfaces:
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
############################################# #CLOCKs ############################################# # Y6 B224_CLK0_P # Y5 B224_CLK0_N # V6 B224_CLK1_P # V5 B224_CLK1_N #set_property -dict { IOSTANDARD LVDS_25 PACKAGE_PIN Y6 } [get_ports {CLK_IN_D_224_clk_p[0]}] #set_property -dict { IOSTANDARD LVDS_25 PACKAGE_PIN V6 } [get_ports {CLK_IN_D_224_clk_p[1]}] # AA13 B24_L7_P # AB13 B24_L7_N # AC14 B24_L6_P # AC13 B24_L6_N set_property -dict { IOSTANDARD LVDS_25 PACKAGE_PIN AA13 } [get_ports {CLK_IN_D_24_clk_p[0]}] set_property -dict { IOSTANDARD LVDS_25 PACKAGE_PIN AC14 } [get_ports {CLK_IN_D_24_clk_p[1]}] ############################################## #LED and DIP Switch ############################################## # D15 USER_LED[0] # D14 USER_LED[1] # G15 USER_LED[2] # G14 USER_LED[3] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN D15 } [get_ports {LED[0]}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN D14 } [get_ports {LED[1]}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN G15 } [get_ports {LED[2]}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN G14 } [get_ports {LED[3]}] # F13 USER_SW[0] # G13 USER_SW[1] # E15 USER_SW[2] # F15 USER_SW[3] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN F13 } [get_ports {SW[0]}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN G13 } [get_ports {SW[1]}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN E15 } [get_ports {SW[2]}] set_property -dict { IOSTANDARD LVCMOS33 PACKAGE_PIN F15 } [get_ports {SW[3]}] ############################################## #HYPERRAM ############################################## # #CK # set_property PACKAGE_PIN AG10 [get_ports CLK_P] # #CKN/RFU # set_property PACKAGE_PIN AH10 [get_ports CLK_N] # #DQ0..7 # set_property PACKAGE_PIN AB9 [get_ports {D[0]}] # set_property PACKAGE_PIN AC11 [get_ports {D[1]}] # set_property PACKAGE_PIN Y10 [get_ports {D[2]}] # set_property PACKAGE_PIN AA8 [get_ports {D[3]}] # set_property PACKAGE_PIN Y9 [get_ports {D[4]}] # set_property PACKAGE_PIN AD11 [get_ports {D[5]}] # set_property PACKAGE_PIN AB10 [get_ports {D[6]}] # set_property PACKAGE_PIN AF10 [get_ports {D[7]}] # #RWDS/RDS # set_property PACKAGE_PIN AA10 [get_ports RWDS] # #CSN # set_property PACKAGE_PIN AD10 [get_ports CS0_N ] # #RFU # set_property PACKAGE_PIN AE10 [get_ports CS1_N] # #RESETN # set_property PACKAGE_PIN AB11 [get_ports RESET_N] # #INT # set_property PACKAGE_PIN AA11 [get_ports INT_N ] |
Note:
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For Vitis project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2020.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2020.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2020.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2020.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
TE modified 2020.2 FSBL
General:
Module Specific:
TE modified 2020.2 FSBL
General:
Xilinx default PMU firmware.
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General Example:
Hello AM0010 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Note:
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For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
Start with petalinux-config -c u-boot
Changes:
Change platform-top.h:
/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; }; /*------------------ QSPI -------------------- */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { //compatible = "flash name, "micron,m25p80"; compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /*------------------ I2C --------------------- */ &i2c0 { //optiga: optiga@30 { // #address-cells = <1>; // #size-cells = <0>; // compatible = "atmel,24c08"; // reg = <0x30>; //}; eeprom: eeprom@53 { #address-cells = <1>; #size-cells = <0>; compatible = "atmel,24c08"; reg = <0x53>; }; //crypto: crypto@60 { // #address-cells = <1>; // #size-cells = <0>; // compatible = "atmel,24c08"; // reg = <0x60>; //}; }; &i2c1 { extern: extern@20 { compatible = "atmel,24c08"; reg = <0x20>; }; }; /* ------------------ GEM3 ------------------- */ &gem3 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy0>; ethernet_phy0: ethernet-phy@0x3 { compatible = "marvell,88e1510"; reg = <0x3>; #address-cells = <0x1>; #size-cells = <0x1>; }; }; /*------------------ USB0 ---------------------*/ /* &dwc3_0 { status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /delete-property/phy-names; /delete-property/phys; /delete-property/snps,usb3_lpm_capable; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; */ /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; maximum-speed = "high-speed"; /delete-property/phy-names; /delete-property/phys; /delete-property/snps,usb3_lpm_capable; snps,dis_u2_susphy_quirk; snps,dis_u3_susphy_quirk; }; &usb0 { status = "okay"; /delete-property/ clocks; /delete-property/ clock-names; clocks = <0x3 0x20>; clock-names = "bus_clk"; }; /*------------------- SD1 ------------------*/ &sdhci1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci1_default>; disable-wp; no-1-8-v; }; &pinctrl0 { status = "okay"; pinctrl_sdhci1_default: sdhci1-default { mux { groups = "sdio1_0_grp"; function = "sdio1"; }; conf { groups = "sdio1_0_grp"; slew-rate = <1>; io-standard = <1>; bias-disable; }; /* mux-cd { groups = "sdio1_cd_0_grp"; function = "sdio1_cd"; }; conf-cd { groups = "sdio1_cd_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; mux-wp { groups = "sdio1_wp_0_grp"; function = "sdio1_wp"; }; conf-wp { groups = "sdio1_wp_0_grp"; bias-high-impedance; bias-pull-up; slew-rate = <1>; io-standard = <1>; }; */ }; }; /*-------------------- SD0 eMMC ----------------*/ &sdhci0 { // disable-wp; no-1-8-v; }; |
Must be add manually, see template
Start with petalinux-config -c kernel
Changes:
# CONFIG_CPU_IDLE is not set
# CONFIG_CPU_FREQ is not set
CONFIG_EDAC_CORTEX_ARM64=y
Start with petalinux-config -c rootfs
Changes:
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
Script App to load init.sh from SD Card if available.
Webserver application suitable for Zynq access. Need busybox-httpd
Note: |
No additional software is needed.
To get content of older revision go to "Change History" of this page and select older document revision number.
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