Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Refer to http://trenz.org/te0763-info for the current online version of this manual and other available documentation.
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
*used as reference |
Design supports following carriers:
*used as reference |
Additional HW Requirements:
*used as reference |
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For general structure and usage of the reference design, see Project Delivery - Xilinx devices
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Reference Design is only usable with the specified Vivado/Vitis version. Do never use different Versions of Xilinx Software for the same project.
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Reference Design for download is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow |
Create Bitstream and hardware description file (.xsa file) and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI to generate the Bitstream is the same, except file export to prebuilt folder. |
Generate Programming Files with Vitis
TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
Option for hello_te0763.mcs on QSPI Flash.
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
TE::pr_program_flash -swapp hello_te0763 |
To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup |
Select QSPI Boot Mode
Note: See TRM of the Carrier, which is used. |
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
1. FPGA loads Bitstream(hello_te0763 application included) from Flash 2. The hello_te0763.elf application starts 2. Hello Trenz will be run on JTAG console |
This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for Microblaze with Linux 1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available) 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR for native FPGA ... |
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property CONFIG_MODE SPIx1 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 1 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] # # # |
#CLKS set_property PACKAGE_PIN Y18 [get_ports {FPGA_24MHz[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_24MHz[0]}] set_property PACKAGE_PIN C18 [get_ports {SYSCLK[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {SYSCLK[0]}] |
## Clock signal create_clock -period 41.666 -name {CLK1B[0]} -waveform {0.000 20.833} [get_ports {FPGA_24MHz[0]}] create_clock -period 10.000 -name {CLK1B[0]} -waveform {0.000 5.000} [get_ports {SYSCLK[0]}] |
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For Vitis project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2021.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2021.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2021.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2021.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2021.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2021.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
Trenz Hello World example as endless loop instead of one console output.
Template location: \sw_lib\sw_apps\hello_te0763
Note: |
Cypress USB Controller
Software and Firmware modified to work with TE0763
Link to TE-USB-Suite-Master
To get content of older revision go to "Change History" of this page and select older document revision number.
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