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Table of Contents |
<!-- Wiki Link: Go to Base Folder of the Module or Carrier, for example : https://wiki.trenz-electronic.de/display/PD/TE0712 --> |
Refer to https://wiki.trenz-electronic.de/display/PD/TEB0911+TRM for the current online version of this manual and other available documentation. |
The Trenz Electronic TEB0911 UltraRack+ board is an industrial-grade motherboard integrating a Xilinx Zynq Ultrascale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SODIMM socket with 64-bit wide data bus, 24 MGT Lanes and powerful switch-mode power supplies for all on-board voltages.. The motherboard exposes the Zynq MPSoC's pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ MPSoC and for developing purposes. The motherboard is capable to be fitted to a dedicated enclosure. On the enclosure's rear and front panel, I/O's and MGT interfaces are accessible through 6 on-board FMC connectors and other standard high-speed interfaces for USB3.0, SFP+, SSD, GbE, etc.
Additional assembly options are available for cost or performance optimization upon request.
Put your block diagram here...
Figure 1: TE0xxx-xx block diagram.
Put top and bottom pics with labels of the real PCB here...
Table 1: TE0xxx-xx main components.
Add description list of PCB labels here...
Storage device name | Content | Notes |
---|---|---|
User configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT) | ||
USB3.0 HUB Configuration EEPROM (Microchip 24LC128-I/ST) | Empty | Not programmed |
Si5338A programmable PLL NVM OTP | ||
Si5345A programmable PLL NVM OTP |
Table 1: Initial delivery state of programmable devices on the module.
For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:
S3-3 (SC_SW1) | S3-4 (SC_SW2) | MIO Location | Description | Notes |
---|---|---|---|---|
OFF | OFF | MIO[43:38] | SD1 Boot Mode (SD-Card on J11) | Supports SD 2.0. |
OFF | ON | MIO[29:26] | PJTAG0 | PS JTAG connection 0 option. |
ON | OFF | MIO[12:0] | QSPI32 | 32-bit addressing, configured with dual on-board QSPI Flash Memory. |
ON | ON | - | JTAG | Dedicated PS interface. |
Table 2: Available boot modes of the on-board Zynq MPSoC
Refer also to the documentation of the SC CPLD firmware of the TEB0911 motherboard.
<!-- Connections and Interfaces or B2B Pin's which are accessible by User --> |
The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT Lanes for use by other mezzanine modules and expansion cards.
The connector supports single ended and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
Following diagram gives an overview of the FMC connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller CPLD U27:
Figure x: General overview of the FMC connectors
<!-- MGT lanes should be listed separately, as they are more specific than just general I/Os. --> |
Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors A - F:
FMC A Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J10 (FMC A) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - |
46 | 28 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 128 GTH | - | 4x MGT lanes | |
Clock Input | - | 1 | Bank 128 GTH | - | 1x Reference clock input to MGT bank | |
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT' |
Table 3: FMC A connector interfaces
FMC A MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J10 (FMC A) | 0 | 128 | GTH |
|
|
|
1 | 128 | GTH |
|
|
| |
2 | 128 | GTH |
|
|
| |
3 | 128 | GTH |
|
|
|
Table 4: FMC A connector MGT lanes
FMC A Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J10 (FMC A) |
| 128 |
|
| Supplied by attached module |
Table 5: FMC A connector clock signal input
FMC A VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J10 (FMC A) | FMCA_3V3 |
| DCDC U32, | Enable by SC CPLD U27, Signal: 'EN_A_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V_FMC_AF |
| DCDC U51, | - | |
FMCAF_1V8 |
| DCDC U39, | Enable by SC CPLD U27, Signal: 'EN_AF_1V8' |
Table 6: FMC A connector available VCC/VCCIO
FMC A Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J10 (FMC A) | M1 | Enable by SC CPLD U27, Signal: 'FAN_A_EN' | - |
Table 7: FMC A connector cooling fan
FMC F Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J21 (FMC F) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - |
28 | 14 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||
68 | 34 | SC CPLD U27 Bank 3 | FMCAF_1V8 | - | ||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 4 (2 x RX/TX) | Bank 129 GTH | - | 2x MGT lanes | |
Clock Input | - | 1 | Bank 129 GTH | - | 1x Reference clock input to MGT bank | |
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT' |
Table 8: FMC F connector interface
FMC F MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J21 (FMC F) | 0 | 129 | GTH |
|
|
|
1 | 129 | GTH |
|
|
|
Table 9: FMC F connector MGT lanes
FMC F Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J21 (FMC F) |
| 129 |
|
| Supplied by attached module |
Table 10: FMC F connector clock signal input
FMC F VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J21 (FMC F) | FMCF_3V3 |
| DCDC U42, | Enable by SC CPLD U27, Signal: 'EN_A_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V_FMC_AF |
| DCDC U51, | - | |
FMCAF_1V8 |
| DCDC U39, | Enable by SC CPLD U27, Signal: 'EN_AF_1V8' |
Table 11: FMC F connector available VCC/VCCIO
FMC F Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J21 (FMC F) | M6 | Enable by SC CPLD U27, Signal: 'FAN_F_EN' | - |
Table 12: FMC F connector cooling fan
FMC B Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J4 | I/O | 24 | 12 | Bank 47 HD | FMCBC_1V8 | - |
20 | 10 | Bank 48 HD | FMCBC_1V8 | - | ||
24 | 12 | Bank 49 HD | FMCBC_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 0 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 130 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 48 HD | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 130 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT' |
Table 13: FMC B connector interfaces
FMC B MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J4 (FMC B) | 3 | 130 | GTH |
|
|
|
2 | 130 | GTH |
|
|
| |
1 | 130 | GTH |
|
|
| |
0 | 130 | GTH |
|
|
|
Table 14: FMC B connector MGT lanes
FMC B Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J4 (FMC B) |
| 130 |
|
| Supplied by attached module |
| 48 HD |
|
| Supplied by attached module | |
| 48 HD |
|
| Supplied by attached module |
Table 15: FMC B connector clock signal input
FMC B VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J4 (FMC B) | FMCB_3V3 |
| DCDC U33, | Enable by SC CPLD U27, Signal: 'EN_B_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC | |
FMCBC_1V8 |
| DCDC U40, | Enable by SC CPLD U27, Signal: 'EN_BC_1V8' |
Table 16: FMC B connector available VCC/VCCIO
FMC B Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J4 (FMC B) | M2 | Enable by SC CPLD U27, Signal: 'FAN_B_EN' | - |
Table 17: FMC B connector cooling fan
FMC C Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J8 | I/O | 20 | 10 | Bank 50 HD | FMCBC_1V8 | - |
68 | 34 | Bank 67 HP | FMCBC_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 230 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 50 HD | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 230 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT' |
Table 18: FMC C connector interfaces
FMC C MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J8 (FMC C) | 3 | 230 | GTH |
|
|
|
2 | 230 | GTH |
|
|
| |
1 | 230 | GTH |
|
|
| |
0 | 230 | GTH |
|
|
|
Table 19: FMC C connector MGT lanes
FMC C Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J8 (FMC C) |
| 230 |
|
| Supplied by attached module |
| 50 HD |
|
| Supplied by attached module | |
| 50 HD |
|
| Supplied by attached module |
Table 20: FMC C connector clock signal input
FMC C VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J8 (FMC C) | FMCC_3V3 |
| DCDC U34, | Enable by SC CPLD U27, Signal: 'EN_C_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC | |
FMCBC_1V8 |
| DCDC U40, | Enable by SC CPLD U27, Signal: 'EN_BC_1V8' |
Table 21: FMC C connector available VCC/VCCIO
FMC C Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J8 (FMC C) | M3 | Enable by SC CPLD U27, Signal: 'FAN_C_EN' | - |
Table 22: FMC C connector cooling fan
FMC D Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J7 | I/O | 20 | 10 | Bank 65 HP | FMCDE_1V8 | - |
48 | 24 | Bank 66 HP | FMCDE_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 229 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 65 HP | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 229 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT' |
Table 23: FMC D connector interfaces
FMC D MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Donnector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J7 (FMC D) | 3 | 229 | GTH |
|
|
|
2 | 229 | GTH |
|
|
| |
1 | 229 | GTH |
|
|
| |
0 | 229 | GTH |
|
|
|
Table 24: FMC D connector MGT lanes
FMC D Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J7 (FMC D) |
| 229 |
|
| Supplied by attached module |
| 65 HP |
|
| Supplied by attached module | |
| 65 HP |
|
| Supplied by attached module |
Table 25: FMC D connector clock signal input
FMC D VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J7 (FMC D) | FMCD_3V3 |
| DCDC U35, | Enable by SC CPLD U27, Signal: 'EN_D_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC | |
FMCDE_1V8 |
| DCDC U41, | Enable by SC CPLD U27, Signal: 'EN_DE_1V8' |
Table 26: FMC D connector available VCC/VCCIO
FMC D Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J7 (FMC D) | M4 | Enable by SC CPLD U27, Signal: 'FAN_D_EN' | - |
Table 27: FMC D connector cooling fan
FMC E Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J6 | I/O | 24 | 12 | Bank 65 HP | FMCDE_1V8 | - |
44 | 22 | Bank 64 HP | FMCDE_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 228 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 64 HP | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 228 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT' |
Table 28: FMC E connector interfaces
FMC E MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J6 (FMC E) | 3 | 228 | GTH |
|
|
|
2 | 228 | GTH |
|
|
| |
1 | 228 | GTH |
|
|
| |
0 | 228 | GTH |
|
|
|
Table 29: FMC E connector MGT lanes
FMC E Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J6 (FMC E) |
| 228 |
|
| Supplied by attached module |
| 64 HP |
|
| Supplied by attached module | |
| 64 HP |
|
| Supplied by attached module |
Table 30: FMC E connector clock signal input
FMC E VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J6 (FMC E) | FMCE_3V3 |
| DCDC U36, | Enable by SC CPLD U27, Signal: 'EN_E_3V3' |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC | |
FMCDE_1V8 |
| DCDC U41, | Enable by SC CPLD U27, Signal: 'EN_DE_1V8' |
Table 31: FMC E connector available VCC/VCCIO
FMC E Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J6 (FMC E) | M5 | Enable by SC CPLD U27, Signal: 'FAN_E_EN' | - |
Table 32: FMC E connector cooling fan
JTAG access to the ... is provided through XMOD connector ....
JTAG Signal | B2B Connector Pin |
---|---|
TCK | JMx-xx |
TDI | JMx-xx |
TDO | JMx-xx |
TMS | JMx-xx |
Table 5: JTAG interface signals.
Describe SD Card interface shortly here if the module has one...
FPGA / SoC Pin | Connected To | Signal Name | Notes |
---|---|---|---|
MIO0 | J10-9 | Card detect switch | |
MIO10 | J10-7 | DAT0 | |
MIO11 | J10-3 | CMD | |
MIO12 | J10-5 | CLK | |
MIO13 | J10-8 | DAT1 | |
MIO14 | J10-1 | DAT3 | |
MIO15 | J10-2 | CD/DAT3 |
Table x: SD Card interface signals and connections.
<!-- Components on the Module, like Flash, PLL, PHY... --> |
The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
For detailed information, refer to the reference page of the SC CPLD firmware of this module.
The TEB0911 UltraRack is equipped with one System Controller CPLDs - Lattice Semiconductor LCMXO2-7000HC (MachXO2 Product Family) with the schematic designators U27.
The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic of the CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO, PL IO-bank differential lanes and I²C interface.
The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.
Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS (MIO), PL bank pins and I²C interface.
<!-- Put in link to the Wiki reference page of the firmware of the SC CPLD. --> |
Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:
Pin Name | Mode | Function | B2B Connector Pin | Default Configuration |
---|---|---|---|---|
PGOOD | Output | Power Good | J1-148 | Active high when all on-module power supplies are working properly. |
JTAGEN | Input | JTAG Select | J2-131 | Low for normal operation. |
.. | .. | .. | .. | .. |
Table x: System Controller CPLD I/O pins.
<!-- For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD. Add link to the Wiki reference page of the SC CPLD, if available. --> |
USB PHY (U9) is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U10).
PHY Pin | Connected to | Notes |
---|---|---|
ULPI | PS bank MIO52 ... MIO63 | Zynq Ultrascale+ USB0 MIO pins are connected to the PHY |
REFCLK | - | 52MHz from on board oscillator (U9) |
REFSEL[0..2] | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz) |
RESETB | SC CPLD U17 | Low active USB PHY Reset (pulled-up to PS_1.8V). |
DP, DM | 4-port USB3.0 Hub U4 | USB2.0 data lane |
CPEN | - | External USB power switch active-high enable signal |
VBUS | 5V | Connected to USB VBUS via a series of resistors, see schematic |
ID | - | For an A-device connect to the ground. For a B-device, leave floating |
Table 17: USB PHY interface connections
Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).
On the carrier board there are up to 4 USB3.0 Super Speed ports available, which are also downward compatible to USB2.0 High Speed ports. The USB3.0 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub controller U4. The pin-strap configuration option of the USB3.0 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller is also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U16.
On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank to establish the USB3.0 data lane. For the USB2.0 interface, the controller is connected to the on-board USB2.0 PHY U9. The USB2.0 PHY is connected per ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.
The USB3.0 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.
On-board Gigabit Ethernet PHY (U12) is provided with Marvell Alaska 88E1512 IC. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator (U13). The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U17, pin 70.
PHY Pin | Connected to | Notes |
---|---|---|
MDC/MDIO | PS bank MIO76, MIO77 | - |
PHY LED0..1 | SC CPLD U17, pin 67,86 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
PHY_LED2 / INTn: | SC CPLD U17, pin 85 | Active low interrupt line |
PHY_CLK125M | SC CPLD U17, pin 70 | 125 MHz Ethernet PHY clock out |
CONFIG | SC CPLD U17, pin 65 | Configuration of PHY address LSB and VDDO level |
RESETn | SC CPLD U17, pin 62 | Active low reset line |
RGMII | PS bank MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
SGMII | - | Serial Gigabit Media Independent Interface |
MDI | RJ45 GbE MagJack J7 | Media Dependent Interface |
Table 18: Ethernet PHY interface connections
On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.
All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.
For this purpose, the TEB0911 carrier board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.
Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches.
The I2C bus works internally on-module with reference voltage 1.8V, it is connected to the MPSoC I2C interface via PS MIO bank (pins MIO38, MIO39) configured as master.
MIO | Signal Schematic Name | Notes |
---|---|---|
38 | I2C_SCL | 1.8V reference voltage |
39 | I2C_SDA | 1.8V reference voltage |
Table 19: MIO-pin assignment of the module's I2C interface
I2C addresses for on-board slave devices are listed in the table below:
I²C Slave Devices connected to MPSoC I²C Interface | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
---|---|---|---|
8-channel I²C switch U16 | - | 0x73 | I2C_SDA / I2C_SCL |
8-channel I²C switch U27 | - | 0x77 | I2C_SDA / I2C_SCL |
SC CPLD U39, bank 2, pins 52 (SDA), 50 (SCL) | - | User programmable | I2C_SDA / I2C_SCL |
I²C Slave Devices connected to 8-channel I²C Switch U16 | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
On-board Quad programmable PLL clock generator U35 Si5338 | 0 | 0x70 | MCLK_SDA / MCLK_SCL |
8-bit I²C IO Expander U44 | 1 | 0x26 | SFP_SDA / SFP_SCL |
PCIe Connector J1 | 2 | module dependent | PCIE_SDA / PCIE_SCL |
SFP+ Connector J14A | 3 | module dependent | SFP1_SDA / SFP1_SCL |
SFP+ Connector J14B | 4 | module dependent | SFP2_SDA / SFP2_SCL |
Configuration EEPROM U24 | 5 | 0x54 | MEM_SDA / MEM_SCL |
Configuration EEPROM U36 | 5 | 0x52 | MEM_SDA / MEM_SCL |
Configuration EEPROM U41 | 5 | 0x51 | MEM_SDA / MEM_SCL |
Configuration EEPROM U22 | 5 | 0x50 | MEM_SDA / MEM_SCL |
8-bit I²C IO Expander U38 | 5 | 0x27 | MEM_SDA / MEM_SCL |
FMC Connector J5 | 6 | module dependent | FMC_SDA / FMC_SCL |
USB3.0 Hub configuration EEPROM U5 | 7 | 0x51 | USBH_SDA / USBH_SCL |
USB3.0 Hub | 7 | 0x60 | USBH_SDA / USBH_SCL |
I²C Slave Devices connected to 8-channel I²C Switch U27 | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
PMOD Connector P1 | 0 | module dependent | PMOD_SDA / PMOD_SCL |
24-bit Audio Codec U3 | 1 | 0x38 | A_I2C_SDA / A_I2C_SCL |
FireFly Connector J15 | 2 | module dependent | FFA_SDA / FFA_SCL |
FireFly Connector J22 | 3 | module dependent | FFB_SDA / FFB_SCL |
On-module Quad programmable PLL clock generator Si5345 (TE0808) | 4 | 0x69 | PLL_SDA / PLL_SCL |
SC CPLD U17, bank 3, pins 13 (SDA), 14 (SCL) | 5 | User programmable | SC_SDA / SC_SCL |
8-bit I²C IO Expander U34 | 6 | 0x24 | FF_E_SDA / FF_E_SCL |
PMOD Connector P3 | 7 | module dependent | EXT_SDA / EXT_SCL |
Table 20: On-board peripherals' I2C-interfaces device slave addresses
The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:
EEPROM Modell | Schematic Designator | Memory Density | Purpose |
---|---|---|---|
24LC128-I/ST | U24 | 128 Kbit | user |
24AA025E48T-I/OT | U36 | 2 Kbit | user |
24AA025E48T-I/OT | U41 | 2 Kbit | user |
24AA025E48T-I/OT | U42 | 2 Kbit | user |
24LC128-I/ST | U5 | 128 Kbit | USB3.0 Hub U4 configuration memory |
Table 21: On-board configuration EEPROMs overview
On-board CAN FD (Flexible Data Rate) transceiver is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.
The transceiver is connected to System Controller CPLD U17, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD U17.
The TEB0911 UltraRack board is equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.
On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.
The TEB0911 carrier board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:
Clock Source | Schematic Name | Frequency | Clock Input Destination |
---|---|---|---|
SiTime SiT8008BI oscillator, U10 | USB0_RCLK | 52.000000 MHz | USB 2.0 transceiver PHY U9, pin 26 |
SiTime SiT8008BI oscillator, U13 | ETH_CLK | 25.000000 MHz | Gigabit Ethernet PHY U12, pin 34 |
SiTime SiT8008BI oscillator, U7 | - | 25.000000 MHz | Quad PLL clock generator U35, pin 3 |
DSC1123 oscillator, U23 | B505_CLK1 | 150.0000 MHz | PS GT Bank, dedicated for SATA interface |
DSC1123 oscillator, U6 optional, not equipped | B505_CLK0 | 100.0000 MHz | PS GT Bank, dedicated for USB interface |
Silicon Labs 570FBB000290DG, U45 optional, not equipped | B47_L5 (LVDS) | 250.MHz | PL Bank clock capable input pins |
SiTime SiT8008BI oscillator, U25 | CLK_CPLD | 25.576000 MHz | System Controller CPLD U35, pin 128 |
Table 16: Reference clock signal oscillators
There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.
Si5338A Pin | Signal Name / Description | Connected To | Direction | Note |
---|---|---|---|---|
IN1 | - | Not connected. | Input | Not used. |
IN2 | - | GND | Input | Not used. |
IN3 | Reference input clock. | U3, pin 3 | Input | 25.000000 MHz oscillator, Si8208AI. |
IN4 | - | GND | Input | I2C slave device address LSB. |
IN5 | - | Not connected. | Input | Not used. |
IN6 | - | GND | Input | Not used. |
CLK0A | CLK1_P | U1, R23 | Output | FPGA bank 45. |
CLK0B | CLK1_N | U1, P23 | Output | FPGA bank 45. |
CLK1A | MGT_CLK1_N | U1, V5 | Output | FPGA MGT bank 225 reference clock. |
CLK1B | MGT_CLK1_P | U1, V6 | Output | FPGA MGT bank 225 reference clock. |
CLK2A | MGT_CLK3_N | U1, AB5 | Output | FPGA MGT bank 224 reference clock. |
CLK2B | MGT_CLK3_P | U1, AB6 | Output | FPGA MGT bank 224 reference clock. |
CLK3A | CLK0_P | U1, pin T24 | Output | FPGA bank 45. |
CLK3B | CLK0_N | U1, pin T25 | Output | FPGA bank 45. |
Table : Programmable quad PLL clock generator inputs and outputs.
The module has following reference clock signals provided by on-board oscillators and external source from carrier board:
Clock Source | Schematic Name | Frequency | Clock Destination |
---|---|---|---|
.. | .. | .. | .. |
SiTime SiT8008BI oscillator, U21 | - | 25.000000 MHz | Quad PLL clock generator U16, pin 3. |
Table : Reference clock signals.
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D1 | Green | ||
.. | .. | .. | .. |
Table : On-board LEDs.
<!-- If power sequencing and distribution is not so much, you can join both sub sections together --> |
The maximum power consumption of the board mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Power Input | Typical Current |
---|---|
24V VIN | TBD* |
Table : Typical power consumption, *to Be Determined soon with reference design setup.
Power supply with minimum current capability of ?? A for system startup is recommended.
The TEB0911 UltraRack board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.
This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular on-board DC-DC converters.
The Processing System contains three Power Domains:
There are following dependencies how the initial 24V voltage from the main power jack J34 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:
To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.
On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller CPLD U27:
Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance is asserted.
Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.
Figure : Module power-on diagram.
If the module has one, describe it here...
NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.
Power Rail Name | B2B JM1 Pins | B2B JM2 Pins | Direction | Notes |
---|---|---|---|---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Main supply voltage from the carrier board. |
3.3V | - | 10, 12, 91 | Output | Module on-board 3.3V voltage supply. (would be good to add max. current allowed here if possible) |
B64_VCO | 9, 11 | - | Input | HR (High Range) bank voltage supply from the carrier board. |
VBAT_IN | 79 | - | Input | RTC battery supply voltage from the carrier board. |
... | ... | ... | ... | ... |
Table : Module power rails.
Different modules (not just 4 x 5 cm ones) have different type of connectors with different specifications. Following note is for Samtec Razor Beam™ LSHM connectors only, but we should consider adding such note into included file in Board to Board Connectors section instead of here.
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered). |
Bank | Schematic Name | Voltage | Voltage Range |
---|---|---|---|
500 (MIO0) | PS_1.8V | 1.8V | - |
501 (MIO1) | PS_1.8V | 1.8V | - |
502 (DDR3) | 1.35V | 1.35V | - |
12 HR | VCCIO_12 | User | HR: 1.2V to 3.3V |
13 HR | VCCIO_13 | User | HR: 1.2V to 3.3V |
33 HP | VCCIO_33 | User | HP: 1.2V to 1.8V |
34 HP | VCCIO_34 | User | HP: 1.2V to 1.8V |
35 HP | VCCIO_35 | User | HP: 1.2V to 1.8V |
Table : Module PL I/O bank voltages.
<!-- Generate new entry: Replace with correct on for selected module series --> |
NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.
Module Variant | FPGA / SoC | Operating Temperature | Temperature Range |
---|---|---|---|
TE0710-02-35-2CF | XC7A35T-2CSG324C | 0°C to +70°C | Commercial |
TE0715-04-30-3E | XC7Z030-3SBG485E | 0°C to +85°C | Extended |
TE0841-01-035-1I | XCKU035-1SFVA784I | –40°C to +85°C | Industrial |
.. | .. | .. | .. |
Table : Module variants.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | V | - | ||
Storage temperature | °C | - |
Table : Module absolute maximum ratings.
Assembly variants for higher storage temperature range are available on request. |
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | ||||
Operating temperature |
Table : Module recommended operating conditions.
Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings. |
Commercial grade: 0°C to +70°C.
Extended grade: 0°C to +85°C.
Industrial grade: -40°C to +85°C.
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Module size: ... mm × ... mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: ... mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Put mechanical drawings here...
Figure : Module physical dimensions drawing.
Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
- | 01 | Prototypes |
Table : Module hardware revision history.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Put picture of actual PCB showing model and hardware revision number here...
Figure : Module hardware revision number.
<!-- Generate new entry: 1.add new row below first 2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number 3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> |
Date | Revision | Contributors | Description |
---|---|---|---|
John Hartfiel | Remove Link to Download | ||
2017-11-10 | v.58 | Ali Naseri |
|
2017-09-06 | v.56 | Jan Kumann |
|
2017-09-02 | v.54 | Jan Kumann | DDR Memory section added. |
2017-08-27 | v.43 | John Hartfiel |
|
2017-08-16 | v.42 | Jan Kumann |
|
2017-08-07 | v.32 | Jan Kumann | Few corrections and cosmetic changes. |
2017-07-14 | v.25 | John Hartfiel | Removed weight section update template version |
2017-06-08 | v.20 | John Hartfiel | Add revision number and update document change history |
2017-05-30 | v.1 | Jan Kumann | Initial document. |
all | Jan Kumann, John Hartfiel |
Table : Document change history.