Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Notes :
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Refer to http://trenz.org/te0712-info for the current online version of this manual and other available documentation.
For directly getting started with the prebuilt files jump to the section Launch.
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Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
*used as reference |
Design supports following carriers:
*used as reference |
Additional HW Requirements:
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Notes :
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For general structure and usage of the reference design, see Project Delivery - AMD devices
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Notes :
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of AMD(Xilinx) Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also: AMD Development Tools#XilinxSoftware-BasicUserGuides
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
Press 0 and enter to start "Module Selection Guide"
optional for manual changes: Select correct device and AMD(Xilinx) install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI is the same, except file export to prebuilt folder. |
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The petalinux build images are located in the "<plnx-proj-root>/images/linux" directory
Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings, FPGA+Boot+bootenv=0xA00000 (increase automatically generate Boot partition), increase image size to A:, see Config |
copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
This step depends on Xilinx Device/Hardware for Zynq-7000 series
for ZynqMP
for ...
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Generate Programming Files with Vitis
TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Copy "<project folder>\prebuilt\software\<short name>\spi_bootloader.elf" into "<project folder>\firmware\microblaze_0\"
Copy "<project folder>\workspace\sdk\scu_te0712\Release\scu_te0712.elf" into "\firmware\microblaze_mcs_0\"
Regenerate Vivado Project or Update Bitfile only with "spi_bootloader.elf" and "scu_te0712.elf"
TE::hw_build_design -export_prebuilt TE::sw_run_vitis -all |
Note:
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
AMD(Xilinx) documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Select create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
Option for u-boot.mcs on QSPI Flash.
(u-boot.mcs contains all files necessary to boot up linux)
Connect the USB cable(JTAG) and power supply on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd".
Enter the following TCL-Command into the TCL-Console inside Vivado to program the QSPI Flash.
TE::pr_program_flash -swapp u-boot |
Reboot (if not done automatically)
Not used on this Example.
Not used on this Example.
Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select QSPI as Boot Mode
Note: See TRM of the Carrier, which is used. |
Power On PCB and push the reset button if present on carrier.
1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 (per default off with REV03) and starts Microblaze, 3. SPI Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR |
Open Serial Console (e.g. putty)
Speed: 9600
COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Boot process takes a while, please wait...
Linux Console:
petalinux login: petalinux -> assign new password |
Note: Wait until Linux boot finished. Linux boot process is slower on Microblaze. |
You can use Linux shell now.
udhcpc (ETH0 check) |
Note:
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz
Monitoring:
MGT REF~125MHz, MIG_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz
System reset from MCS and GIO outputs
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property CONFIG_MODE SPIx4 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] |
set_property PULLDOWN true [get_ports reset] |
#I2C #set_property PACKAGE_PIN W21 [get_ports PLL_I2C_scl_io] #set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_scl_io] #set_property PACKAGE_PIN T20 [get_ports PLL_I2C_sda_io] #set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_sda_io] set_property PACKAGE_PIN W21 [get_ports PLL_I2C_ext_scl_o] set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_scl_o] set_property PACKAGE_PIN T20 [get_ports PLL_I2C_ext_sda] set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_sda] #Reset set_property PACKAGE_PIN T3 [get_ports reset] set_property IOSTANDARD LVCMOS15 [get_ports reset] #CLKS set_property PACKAGE_PIN R4 [get_ports {CLK1B[0]}] set_property IOSTANDARD LVCMOS15 [get_ports {CLK1B[0]}] set_property PACKAGE_PIN K4 [get_ports {CLK0_clk_p[0]}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {CLK0_clk_p[0]}] #ETH PHY set_property PACKAGE_PIN N17 [get_ports phy_rst_n] set_property IOSTANDARD LVCMOS33 [get_ports phy_rst_n] #EEPROM onewire (MAC ADDRESS) set_property IOSTANDARD LVCMOS33 [get_ports EEPROM_tri_io] set_property PACKAGE_PIN V22 [get_ports EEPROM_tri_io] #I2C connected to CPLD set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN W22} [get_ports IIC_0_scl_io] set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN U22} [get_ports IIC_0_sda_io] |
create_clock -period 8.000 -name mgt_clk0_clk_p -waveform {0.000 4.000} [get_ports mgt_clk0_clk_p] create_clock -period 10.000 -name {CLK0_clk_p[0]} -waveform {0.000 5.000} [get_ports {CLK0_clk_p[0]}] create_clock -period 20.000 -name {CLK1B[0]} -waveform {0.000 10.000} [get_ports {CLK1B[0]}] create_clock -period 15.152 -name CFGMCLK -waveform {0.000 7.576} [get_pins -hierarchical -filter {NAME =~*NO_DUAL_QUAD_MODE.QSPI_NORMAL/*STARTUP_7SERIES_GEN.STARTUP2_7SERIES_inst/CFGMCLK}] set_false_path -from [get_clocks {CLK0_clk_p[0]}] -to [get_clocks clk_pll_i] set_false_path -from [get_clocks mgt_clk0_clk_p] -to [get_clocks clk_pll_i] set_false_path -from [get_pins {msys_i/SC0712_0/U0/rst_delay_i_reg[3]/C}] -to [get_pins -hierarchical -filter {NAME =~*u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0*/PRE}] set_false_path -from [get_clocks -of_objects [get_pins msys_i/mig_7series_0/u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]] -to [get_clocks mgt_clk0_clk_p] set _xlnx_shared_i0 [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}] set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/C}] -to $_xlnx_shared_i0 set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/COUNTER_REFCLK_inst/bl.DSP48E_2/CLK] -to $_xlnx_shared_i0 set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/D}] |
Note:
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For Vitis project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. spi_bootloaderTE modified SPI Bootloader from Henrik Brix Andersen. Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2020.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2020.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2020.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. eepromeeprom is a petalinux application that executes on startup. It reads the unique 48-bit MAC from the onboard eeprom and uses it to set the system MAC address. |
Template location: "<project folder>\sw_lib\sw_apps\"
MCS Firmware to configure SI5338 and Reset System.
TE modified SPI Bootloader from Henrik Brix Andersen.
Bootloader to load app or second bootloader from flash into DDR.
Here it loads the u-boot.elf from QSPI-Flash to RAM. Hence u-boot.srec becomes redundant.
Descriptions:
Hello TE0712 is a AMD(Xilinx) Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate u-boot.srec(obsolete). Vivado to generate *.mcs
Note:
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For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
(Tipp: Search for Settings with shortcut "Shift"+"/")
Changes:
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000 (fpga)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x400000 (boot)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000 (bootenv)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xB00000 (kernel)
(with this kernel flash address is 0xA00000 (fpga+boot+bootenv) and Kernel size 0xB00000)
Start with petalinux-config -c u-boot
Changes:
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
# CONFIG_PHY_ATHEROS is not set
# CONFIG_PHY_BROADCOM is not set
# CONFIG_PHY_DAVICOM is not set
# CONFIG_PHY_LXT is not set
# CONFIG_PHY_MICREL_KSZ90X1 is not set
# CONFIG_PHY_MICREL is not set
# CONFIG_PHY_NATSEMI is not set
# CONFIG_PHY_REALTEK is not set
CONFIG_RGMII=y
Content of platform-top.h located in <plnx-proj-root>\project-spec\meta-user\recipes-bsp\u-boot\files:
#include <configs/microblaze-generic.h> #include <configs/platform-auto.h> #define CONFIG_SYS_BOOTM_LEN 0xF000000 |
Content of system-user.dtsi located in <petalinux project directory>\project-spec\meta-user\recipes-bsp\device-tree\files:
/include/ "system-conf.dtsi" / { }; /* QSPI PHY */ &axi_quad_spi_0 { #address-cells = <1>; #size-cells = <0>; flash0: flash@0 { compatible = "jedec,spi-nor"; spi-tx-bus-width=<1>; spi-rx-bus-width=<4>; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <25000000>; }; }; /* ETH PHY */ &axi_ethernetlite_0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { device_type = "ethernet-phy"; reg = <1>; }; }; }; |
Start with petalinux-config -c kernel
Changes:
No changes.
Start with petalinux-config -c rootfs
Changes:
# CONFIG_dropbear is not set
# CONFIG_dropbear-dev is not set
# CONFIG_dropbear-dbg is not set
# CONFIG_package-group-core-ssh-dropbear is not set
# CONFIG_packagegroup-core-ssh-dropbear-dev is not set
# CONFIG_packagegroup-core-ssh-dropbear-dbg is not set
# CONFIG_imagefeature-ssh-server-dropbear is not set
optional: to change the password settings at startup look at Adding extra users to the petalinux system.
"Dropbear" is part of the "petalinux-image-minimal" configuration, so changes in the petalinux rootfs will not be applied. To remove "dropbear" anyway, enter the following line in petalinuxbsp.conf in ..\petalinux\project-spec\meta-user\conf:
PACKAGE_EXCLUDE += " dropbear dropbear-openssh-sftp-server dropbear-dev dropbear-dbg dropbear-openssh-sftp-server packagegroup-core-ssh-dropbear packagegroup-core-ssh-dropbear-dbg packagegroup-core-ssh-dropbear-dev" |
No additional application.
Note: |
File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"
General documentation how you work with this project will be available on Si5338
To get content of older revision got to "Change History" of this page and select older document revision number.
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