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Table of Contents |
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Refer to https://wiki.trenz-electronic.de/display/PD/TEB0911+TRM for the current online version of this manual and other available documentation. |
The Trenz Electronic TEB0911 UltraRack+ board is an industrial-grade motherboard integrating a Xilinx Zynq Ultrascale+ MPSoC with 4 GByte Flash memory for configuration and operation, DDR4-SDRAM SODIMM socket with 64-bit wide data bus, 24 MGT Lanes and powerful switch-mode power supplies for all on-board voltages.. The motherboard exposes the Zynq MPSoC's pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ MPSoC and for developing purposes. The motherboard is capable to be fitted to a dedicated enclosure. On the enclosure's rear and front panel, I/O's and MGT interfaces are accessible through 6 on-board FMC connectors and other standard high-speed interfaces for USB3.0, SFP+, SSD, GbE, etc.
Additional assembly options are available for cost or performance optimization upon request.
Put your block diagram here...
Figure 1: TE0xxx-xx block diagram.
Put top and bottom pics with labels of the real PCB here...
Table 1: TE0xxx-xx main components.
Add description list of PCB labels here...
Storage device name | Content | Notes |
---|---|---|
User configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT) | Empty | Not programmed |
USB3.0 HUB Configuration EEPROM (Microchip 24LC128-I/ST) | Empty | Not programmed |
Si5338A programmable PLL NVM OTP | ||
Si5345A programmable PLL NVM OTP |
Table 1: Initial delivery state of programmable devices on the module.
For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:
S3-3 (SC_SW1) | S3-4 (SC_SW2) | MIO Location | Description | Notes |
---|---|---|---|---|
OFF | OFF | MIO[43:38] | SD1 Boot Mode (SD-Card on J11) | Supports SD 2.0. |
OFF | ON | MIO[29:26] | PJTAG0 | PS JTAG connection 0 option. |
ON | OFF | MIO[12:0] | QSPI32 | 32-bit addressing, configured with dual on-board QSPI Flash Memory. |
ON | ON | - | JTAG | Dedicated PS interface. |
Table 2: Available boot modes of the on-board Zynq MPSoC
Refer also to the documentation of the SC CPLD firmware of the TEB0911 motherboard.
<!-- Connections and Interfaces or B2B Pin's which are accessible by User --> |
The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT Lanes for use by other mezzanine modules and expansion cards.
The connector supports single ended and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
Following diagram gives an overview of the FMC connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller CPLD U27:
Figure x: General overview of the FMC connectors
<!-- MGT lanes should be listed separately, as they are more specific than just general I/Os. --> |
Following tables contains information about the interfaces, I/O's, clock and VCCIO sources available on the FMC connectors A - F:
FMC A
FMC A Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J10 (FMC A) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - |
46 | 28 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 128 GTH | - | 4x MGT lanes | |
Clock Input | - | 1 | Bank 128 GTH | - | 1x Reference clock input to MGT bank | |
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT' |
Table 3: FMC A connector interfaces
FMC A MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J10 (FMC A) | 0 | 128 | GTH |
|
|
|
1 | 128 | GTH |
|
|
| |
2 | 128 | GTH |
|
|
| |
3 | 128 | GTH |
|
|
|
Table 4: FMC A connector MGT lanes
FMC A Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J10 (FMC A) |
| 128 |
|
| Supplied by attached module |
Table 5: FMC A connector clock signal input
FMC A VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J10 (FMC A) | FMCA_3V3 |
| DCDC U32, | Enable by SC CPLD U27, bank 2, pin Y18 |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V_FMC_AF |
| DCDC U51, | - | |
FMCAF_1V8 |
| DCDC U39, | Enable by SC CPLD U27, bank 2, pin W19 |
Table 6: FMC A connector available VCC/VCCIO
FMC A Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J10 (FMC A) | M1 | Enable by SC CPLD U27, bank 2, pin Y19 | - |
Table 7: FMC A connector cooling fan
FMC F
FMC F Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J21 (FMC F) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - |
28 | 14 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||
68 | 34 | SC CPLD U27 Bank 3 | FMCAF_1V8 | - | ||
I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 4 (2 x RX/TX) | Bank 129 GTH | - | 2x MGT lanes | |
Clock Input | - | 1 | Bank 129 GTH | - | 1x Reference clock input to MGT bank | |
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCF_PG_C2M', 'FMCF_PG_M2C', 'FMCF_PRSNT' |
Table 8: FMC F connector interface
FMC F MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J21 (FMC F) | 0 | 129 | GTH |
|
|
|
1 | 129 | GTH |
|
|
|
Table 9: FMC F connector MGT lanes
FMC F Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J21 (FMC F) |
| 129 |
|
| Supplied by attached module |
Table 10: FMC F connector clock signal input
FMC F VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J21 (FMC F) | FMCF_3V3 |
| DCDC U42, | Enable by SC CPLD U27, bank 2, pin Y10 |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V_FMC_AF |
| DCDC U51, | - | |
FMCAF_1V8 |
| DCDC U39, | Enable by SC CPLD U27, bank 2, pin W19 |
Table 11: FMC F connector available VCC/VCCIO
FMC F Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J21 (FMC F) | M6 | Enable by SC CPLD U27, bank 2, pin W18 | - |
Table 12: FMC F connector cooling fan
FMC B
FMC B Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J4 (FMC B) | I/O | 24 | 12 | Bank 47 HD | FMCBC_1V8 | - |
20 | 10 | Bank 48 HD | FMCBC_1V8 | - | ||
24 | 12 | Bank 49 HD | FMCBC_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 0 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 130 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 48 HD | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 130 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCB_PG_C2M', 'FMCB_PG_M2C', 'FMCB_PRSNT' |
Table 13: FMC B connector interfaces
FMC B MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J4 (FMC B) | 3 | 130 | GTH |
|
|
|
2 | 130 | GTH |
|
|
| |
1 | 130 | GTH |
|
|
| |
0 | 130 | GTH |
|
|
|
Table 14: FMC B connector MGT lanes
FMC B Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J4 (FMC B) |
| 130 |
|
| Supplied by attached module |
| 48 HD |
|
| Supplied by attached module | |
| 48 HD |
|
| Supplied by attached module |
Table 15: FMC B connector clock signal input
FMC B VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J4 (FMC B) | FMCB_3V3 |
| DCDC U33, | Enable by SC CPLD U27, bank 0, pin G11 |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC connectors | |
FMCBC_1V8 |
| DCDC U40, | Enable by SC CPLD U27, bank 0, pin A3 |
Table 16: FMC B connector available VCC/VCCIO
FMC B Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J4 (FMC B) | M2 | Enable by SC CPLD U27, bank 0, pin A2 | - |
Table 17: FMC B connector cooling fan
FMC C
FMC C Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J8 (FMC C) | I/O | 20 | 10 | Bank 50 HD | FMCBC_1V8 | - |
68 | 34 | Bank 67 HP | FMCBC_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 230 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 50 HD | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 230 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCC_PG_C2M', 'FMCC_PG_M2C', 'FMCC_PRSNT' |
Table 18: FMC C connector interfaces
FMC C MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J8 (FMC C) | 3 | 230 | GTH |
|
|
|
2 | 230 | GTH |
|
|
| |
1 | 230 | GTH |
|
|
| |
0 | 230 | GTH |
|
|
|
Table 19: FMC C connector MGT lanes
FMC C Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J8 (FMC C) |
| 230 |
|
| Supplied by attached module |
| 50 HD |
|
| Supplied by attached module | |
| 50 HD |
|
| Supplied by attached module |
Table 20: FMC C connector clock signal input
FMC C VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J8 (FMC C) | FMCC_3V3 |
| DCDC U34, | Enable by SC CPLD U27, bank 0, pin E11 |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC connectors | |
FMCBC_1V8 |
| DCDC U40, | Enable by SC CPLD U27, bank 0, pin A3 |
Table 21: FMC C connector available VCC/VCCIO
FMC C Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J8 (FMC C) | M3 | Enable by SC CPLD U27, bank 0, pin B3 | - |
Table 22: FMC C connector cooling fan
FMC D
FMC D Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J7 (FMC D) | I/O | 20 | 10 | Bank 65 HP | FMCDE_1V8 | - |
48 | 24 | Bank 66 HP | FMCDE_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 229 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 65 HP | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 229 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCD_PG_C2M', 'FMCD_PG_M2C', 'FMCD_PRSNT' |
Table 23: FMC D connector interfaces
FMC D MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Donnector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J7 (FMC D) | 3 | 229 | GTH |
|
|
|
2 | 229 | GTH |
|
|
| |
1 | 229 | GTH |
|
|
| |
0 | 229 | GTH |
|
|
|
Table 24: FMC D connector MGT lanes
FMC D Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J7 (FMC D) |
| 229 |
|
| Supplied by attached module |
| 65 HP |
|
| Supplied by attached module | |
| 65 HP |
|
| Supplied by attached module |
Table 25: FMC D connector clock signal input
FMC D VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J7 (FMC D) | FMCD_3V3 |
| DCDC U35, | Enable by SC CPLD U27, bank 0, pin F8 |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC connectors | |
FMCDE_1V8 |
| DCDC U41, | Enable by SC CPLD U27, bank 0, pin C5 |
Table 26: FMC D connector available VCC/VCCIO
FMC D Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J7 (FMC D) | M4 | Enable by SC CPLD U27, bank 0, pin D7 | - |
Table 27: FMC D connector cooling fan
FMC E
FMC E Interfaces:
FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
---|---|---|---|---|---|---|
J6 (FMC E) | I/O | 24 | 12 | Bank 65 HP | FMCDE_1V8 | - |
44 | 22 | Bank 64 HP | FMCDE_1V8 | - | ||
I²C | 2 | - | I²C-Switch U13 | - | Muxed to MIO Bank 501 I²C Inteface | |
JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
MGT | - | 8 (4 x RX/TX) | Bank 228 GTH | - | 4x MGT lanes | |
Clock Input | - | 2 | Bank 64 HP | - | 2x Reference clock inputs to PL bank | |
- | 1 | Bank 228 GTH | - | 1x Reference clock input to MGT bank | ||
Control Signals | 3 | - | SC CPLD U27 Bank 2 | 3.3VSB | 'FMCE_PG_C2M', 'FMCE_PG_M2C', 'FMCE_PRSNT' |
Table 28: FMC E connector interfaces
FMC E MGT Lanes:
FMC | MGT Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
---|---|---|---|---|---|---|
J6 (FMC E) | 3 | 228 | GTH |
|
|
|
2 | 228 | GTH |
|
|
| |
1 | 228 | GTH |
|
|
| |
0 | 228 | GTH |
|
|
|
Table 29: FMC E connector MGT lanes
FMC E Clock Signals:
FMC | Clock Signal | Bank | FMC Connector Pin | FPGA Pin | Notes |
---|---|---|---|---|---|
J6 (FMC E) |
| 228 |
|
| Supplied by attached module |
| 64 HP |
|
| Supplied by attached module | |
| 64 HP |
|
| Supplied by attached module |
Table 30: FMC E connector clock signal input
FMC E VCC/VCCIO:
FMC | Available VCC/VCCIO | FMC Connector Pin | Source | Notes |
---|---|---|---|---|
J6 (FMC E) | FMCE_3V3 |
| DCDC U36, | Enable by SC CPLD U27, bank 0, pin E8 |
3V3SB |
| DCDC U50, max. cur.: 1A | not dedicated for FMC connectors | |
12V |
| DCDC U82, | not dedicated for FMC connectors | |
FMCDE_1V8 |
| DCDC U41, | Enable by SC CPLD U27, bank 0, pin C5 |
Table 31: FMC E connector available VCC/VCCIO
FMC E Cooling Fan:
FMC | Fan Designator | Enable Signal | Notes |
---|---|---|---|
J6 (FMC E) | M5 | Enable by SC CPLD U27, bank 0, pin D6 | - |
Table 32: FMC E connector cooling fan
JTAG access to the Zynq MPSoC and SC CPLD is provided through XMOD header J24 and J35.
Figure X: XMOD header J24 and J35
Signal Assignment of XMOD header J24 and J35
Connector | Interface | Signal Schematic Name | XMOD Header Pin | Connected to | VCCIO | VCC |
---|---|---|---|---|---|---|
XMOD Header J24 | JTAG | F_TCK | J24-4 | Bank 503 PS Config, Pin R25 | PS_1V8 | 3V3SB |
F_TDI | J24-10 | Bank 503 PS Config, Pin U25 | ||||
F_TDO | J24-8 | Bank 503 PS Config, Pin T25 | ||||
F_TMS | J24-12 | Bank 503 PS Config, Pin R24 | ||||
GPIO/ | XMOD2_A | J24-3 | SC CPLD U27, bank 5, Pin K7 | |||
XMOD2_B | J24-7 | SC CPLD U27, bank 5, Pin K6 | ||||
XMOD2_E | J24-9 | SC CPLD U27, bank 5, Pin H7 | ||||
XMOD2_G | J24-11 | SC CPLD U27, bank 5, Pin H6 | ||||
XMOD Header J35 | JTAG | C_TCK | J35-4 | SC CPLD U27, bank 0, Pin A8 | 3V3SB | |
C_TDI | J35-10 | SC CPLD U27, bank 0, Pin C7 | ||||
C_TDO | J35-8 | SC CPLD U27, bank 0, Pin A6 | ||||
C_TMS | J35-12 | SC CPLD U27, bank 0, Pin C9 | ||||
GPIO/ | XMOD1_A | J35-3 | SC CPLD U27, bank 0, Pin B19 | |||
XMOD1_B | J35-9 | SC CPLD U27, bank 0, Pin A17 | ||||
XMOD1_E | J35-7 | SC CPLD U27, bank 0, Pin C17 | ||||
XMOD1_G | J35-11 | SC CPLD U27, bank 0, Pin A18 |
Table 33: XMOD interface signals
The JTAG interfaces of the TEB0911 UltraRack board can accessed with the XMOD-FT2232H adapter-board TE0790. The on-board devices Zynq MPSoC U1 and SC CPLD U27 can be programmed via USB2.0 interface of the TE0790 board.
XMOD-Header J24 is designated to program the Zynq Ultrascale+ MPSoC via USB interface, the 4 GPIO/UART pins (XMOD2_A/B/E/G) of this header are routed to the System Controller CPLD U27.
XMOD-Header J35 is designated to program the System Controller CPLD U27 via USB interface, the 4 GPIO/UART pins (XMOD1_A/B/E/G) of this header are also routed to the System Controller CPLD U27.
To program the System Controller CPLD, the JTAG interface of this devices have to be activated by DIP-switch S3-2.
When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO on both headers J24 and J35 will be sourced by the on-board supply voltages. Set the XMOD DIP-switch with the setting:
XMOD DIP-switches | Position |
---|---|
Switch 1 | ON |
Switch 2 | OFF |
Switch 3 | OFF |
Switch 4 | OFF |
Table 34: XMOD adapter board DIP-switch positions for voltage configuration
Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices. The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download. |
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 502. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the System Controller CPLD bank 2, pins Y12, Y13 and Y14.
Figure X: Gigabit Ethernet interface
PHY Pin | Connected to | Notes |
---|---|---|
MDC/MDIO | PS bank 502 MIO76, MIO77 | - |
PHY LED0..2 | SC CPLD U27, bank 4, pin L5, L1, K1 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
PHY_CLK125M | SC CPLD U27, bank 4, pin K2 | 125 MHz Ethernet PHY clock out |
CONFIG | pulled up to PS_1V8 | Configuration of PHY address LSB and VDDO level |
RESETn | SC CPLD U27, bank 4, pin L6 | Active low reset line |
RGMII | PS bank 502 MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
SGMII | - | Serial Gigabit Media Independent Interface |
MDI | RJ45 GbE MagJack J13 | Media Dependent Interface |
Table 35: Ethernet PHY interface connections
On the TEB0911 board two USB3 Superspeed ports are available to the user, which are downward compatible to USB2 Highspeed.
Figure X: USB3 interface
The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:
IC | Interface | Signal Schematic Names | Connected to | Note |
---|---|---|---|---|
USB3 Hub U4 | USB3 Upstream MGT lane |
| PS GTR bank 505 Pins:
| - |
USB2 Uptream data LVDS pair |
| USB2 PHY U15 Pins: 18,19 | - | |
USB3 Downstream lane |
| 2-port USB3 A / RJ-45 connector | - | |
USB2 Downstream LVDS pair |
| 2-port USB3 A / RJ-45 connector | - | |
I²C |
| Configuration EEPROM U5, 8-channel I²C-switch U37 | EEPROM U5 is configuration and | |
Control Lines |
| SC CPLD U27, bank 2 Pins: Y17, Y16, Y15 | - | |
USB2 PHY U15 | USB2 ULPI |
| PS bank 502 Pins: MIO52 ... MIO63 | - |
USB2 data LVDS pair |
| USB3 Hub U4 Pins: 71,72 | - | |
Control Lines | USB0_RST | SC CPLD U27, bank 4 Pin: M2 | - |
Table 36: USB3 signals and interfaces
The TEB0911 board provides the high speed MGT interface connectors "SFP+" (Enhanced small form-factor pluggable) with data transmission rates up to 10 Gbit/s.
Block diagram below shows the dependencies between the implied devices which establish the SFP+ interface:
Figure X: SFP+ interface
Connector | Interface | Signal Schematic Name | Connected to | FPGA Direction | Description | Logic | Notes |
---|---|---|---|---|---|---|---|
SFP+ J9A | MGT Lane |
| GTH bank 129 Pins:
| BiDir | Multi gigabit highspeed data lane | - | - |
I²C |
| 8-channel I²C-switch U37 | BiDir | 2-wire Serial Interface | - | - | |
Control Lines | SFP0_RS0 | I²C 8-bit I/O Port-Expander U86 | Output | Full RX bandwidth | Low active | I/O Port Expander on | |
SFP0_RS1 | Output | Reduced RX bandwidth | Low active | ||||
SFP0_M-DEF0 | Input | Module present / not present | Low active | ||||
SFP0_TX_FAULT | Input | Fault / Normal Operation | High active | ||||
SFP0_LOS | SC CPLD U27, bank 2, pin V8 | Input | Loss of receiver signal | High active | - | ||
SFP0_TX_DIS | SC CPLD U27, bank 2, pin Y7 | Output | SFP Enabled / Disabled | Low active | - | ||
SFP+ J9B | MGT Lane |
| GTH bank 129 Pins:
| BiDir | Multi gigabit highspeed | - | - |
I²C |
| 8-channel I²C-switch U37 | BiDir | 2-wire Serial Interface | - | - | |
Control Lines | SFP1_RS0 | I²C 8-bit I/O Port-Expander U86 | Output | Full RX bandwidth | Low active | I/O Port Expander on | |
SFP1_RS1 | Output | Reduced RX bandwidth | Low active | ||||
SFP1_M-DEF0 | Input | Module present / not present | Low active | ||||
SFP1_TX_FAULT | Input | Fault / Normal Operation | High active | ||||
SFP1_LOS | SC CPLD U27, bank 2, pin W7 | Input | Loss of receiver signal | High active | - | ||
SFP1_TX_DIS | SC CPLD U27, bank 2, pin V7 | Output | SFP Enabled / Disabled | Low active | - |
Table 37: SFP+ signals and interfaces
On the TEB0911 UltraRack board one SSD interface is available provided by a NGFF (Next Generation Form Faktor) M.2 socket (Key M) which supports data transmission rates for PCIe3, SATA3 and USB3 interfaces.
Figure X: SSD interface
Connector | Interface | Signal Schematic Name | Connected to | FPGA Direction | Description | Logic | Notes |
---|---|---|---|---|---|---|---|
M.2-NGFF PCIe Socket U2 | MGT Lane |
| PS GTR bank 505 Pins:
| BiDir | Multi gigabit highspeed data lane | - | - |
Clock Input |
| Quad programmable PLL clock generator U12, CLK0 | - | Reference clock signal | - | - | |
Control Lines | SSD1_LED | SC CPLD U27, bank 2, pin AA13 | Output | LED Output | High active | - | |
SSD1_SLEEP | SC CPLD U27, bank 2, pin AA12 | Input | PCIe sleep state | Low active | |||
SSD1_PERSTN | SC CPLD U27, bank 2, pin AA11 | Input | PCIe reset input | Low active | - | ||
SSD1_WAKE | SC CPLD U27, bank 2, pin AB11 | Input | PCIe Link reactivation | Low active | - | ||
SSD1_CLKRQ | connect to GND | BiDir | PCIe Clock Request | Low active | - |
Table 38: SSD signals and interfaces
The TEB0911 board provides the high speed DisplayPort interface for visual output. The DisplayPort is connected with two transmit LVDS-pairs of bank 505 PS GTR lanes. Additionally the auxiliary transmit line is established by the SC CPLD in conjunction with a LVDS Line Driver/Receiver.
Figure X: DisplayPort interface
Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:
Connector | Interface | Signal Schematic Name | Connected to | FPGA Direction | Description | Notes |
---|---|---|---|---|---|---|
DisplayPort Connector J12 | MGT Lane |
| PS GTR bank 505 Pins:
| Output | Multi gigabit highspeed data lane (only transmit pairs) | - |
Auxiliary Line |
| LVDS Line Driver/Receiver, U30 | - | Convert signal from single ended to LVDS Single ended signals: 'DP_AUX_TX', 'DP_AUX_RX', | - | |
Control Lines | DP_TX_HPD | SC CPLD U27, bank 2, pin AA15 | Input | DisplayPort Hot Plug Detect | - | |
DP_EN | LDO U29 | - | 3.3V Supply Voltage for DisplayPort | - |
Table 39: DisplayPort signals and interfaces
On the TEB0911 board there is a DDR4 memory interface with a 64-bit databus width available for SO-DIMM modules.
Figure X: DDR4 memory interface
Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface:
Connector | DDR4 SDRAM I/O Signal | Signal Schematic Name | Description | Connected to | Notes |
---|---|---|---|---|---|
DDR4 SO-DIMM Socket U13 | Address inputs | DDR4-A0 ... DDR4-A16 | - | PS DDR Bank 504 | - |
Bank address inputs | DDR4-BA0 / DDR4-BA1 | - | - | ||
Bank group inputs | DDR4-BG0 / DDR4-BG1 | - | - | ||
Differential clocks |
| 2 x DDR4 clock | - | ||
Data input/output | DQ0 ... DQ63 | - | - | ||
Check bit input/output | CB0 ... CB7 | - | - | ||
Data strobe (differential) |
| - | - | ||
Data mask and data bus inversion | DDR4-DM0 ... DDR4-DM8 | - | - | ||
Serial address inputs | DDR4-SA0 ... DDR4-SA2 | address range configuration on I²C bus | - | ||
Control Signals | DDR4-CS_N0 / DDR4-CS_N1 | chip selest signal | - | ||
DDR4-ODT0 / DDR4-ODT1 | On-die termination enable | - | |||
DDR4-RESET | nRESET | - | |||
DDR4-PAR | Command and address parity input | - | |||
DDR4-CKE0 / DDR4-CKE1 | Clock enable | - | |||
DDR4-ALERT | CRC error flag | - | |||
DDR4-ACT | Activation command input | - | |||
DDR4-EVENT | Temperature event | - | |||
I²C |
| - | 8-channel I²C switch U37 | - |
Table 40: DDR4 64-bit memory interface signals and pins
Refer to the Xilinx Zynq UltraScale+ datasheet DS925 for more information on whether the specific package of the Zynq UltraScale+ MPSoC supports the maximum data transmission rate of 2400 MByte/s, which also depends on the used SO-DIMM module.
The TEB0911 board provides a CAN interface, the CAN transceiver is connected and operated by the SC CPLD:
Figure X: CAN interface
The CAN interface of external devices can be connected via D-SUB 9-pin male connector J3 or to the 6-pin male header J15:
Connector | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
D-SUB 9-pin J3 | CAN_H, pin 7 | CAN Transceiver U48, pin 7 | - |
CAN_L, pin 2 | CAN Transceiver U48, pin 6 | - | |
6-pin male header J15 | CAN_H, pin 4 | CAN Transceiver U48, pin 7 | - |
CAN_L, pin 3 | CAN Transceiver U48, pin 6 | - | |
CAN Transceiver | Signal Schematic Name | Connected to | Notes |
TCAN337 U48 | CAN_TX | SC CPLD U27, bank 0, pin C16 | 3.3V VCCIO |
CAN_RX | SC CPLD U27, bank 0, pin B15 | 3.3V VCCIO | |
CAN_S | SC CPLD U27, bank 0, pin C15 | 3.3V VCCIO | |
CAN_FAULT | SC CPLD U27, bank 0, pin D15 | 3.3V VCCIO |
Table 41: CAN interface signals and pins
The SD Card interface of the TEB0911 board is routed via SD IO interface to the PS MIO bank 501 of the Zynq Ultrascale+ MPSoC (3.3V VCCO). The SC CPLD U27 controls the load switch Q3 to enable the card sockets J11 with signal 'SD_EN', bank 2, pin U11. The "Card Detect" and "Write Protect" signal are also routed to the SC CPLD:
Figure X: SD Card interface
The SD Card socket have following signal and pin assignment:
Connector | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
SD Card Socket J11 | SD_DAT0, J11-7 | PS bank 501 Pins: MIO46 ... MIO51 | - |
SD_DAT1, J11-8 | - | ||
SD_DAT2, J11-9 | - | ||
SD_DAT3, J11-1 | - | ||
SD_CMD, J11-2 | - | ||
SD_CK, J11-5 | - | ||
SD_CD, J11-10 | SC CPLD U27, bank 2, pin T11 | Card Detect | |
SD_WP, J11-11 | SC CPLD U27, bank 2, pin T10 | Write Protect |
Table 42: SD Card interface signals and connections
The TEB0911 offers 3x 4-wire PWM FAN connectors for optional cooling fans controlled by SC CPLD U27:
Figure X: 4-Wire PWM FAN connectors
Connector | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
Fan Connector J2 | F1PWM | SC CPLD U27, bank 0, pin E10 | - |
F1SENSE | SC CPLD U27, bank 0, pin D11 | - | |
F1_EN | SC CPLD U27, bank 0, pin C8 | Controls 12V Load Switch | |
Fan Connector J23 | F2PWM | SC CPLD U27, bank 0, pin D9 | - |
F2SENSE | SC CPLD U27, bank 0, pin G12 | - | |
F2_EN | SC CPLD U27, bank 0, pin B4 | Controls 12V Load Switch | |
Fan Connector J33 | F3PWM | SC CPLD U27, bank 0, pin B13 | - |
F3SENSE | SC CPLD U27, bank 0, pin A13 | - | |
F3_EN | SC CPLD U27, bank 0, pin A12 | Controls 12V Load Switch |
Table 43: 4-wire PWM fan connectors signals and pins
The programmable 10-output reference clock generator U17 can be accessed through its I²C interface to be programed. The I²C interface is connected to the Zynq MPSoc via I²C switch U13 and to pin header J22.
With the SMA Coaxial connector J25 the clock generator can be supplied with an external clock signal.
Figure X: PLL clock interfaces
Connector | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
Pin Header J22 | PLL_SCL | clock generator U17, pin 16 | PS_1V8 VCCIO |
PLL_SDA | clock generator U17, pin 18 | ||
SMA Coax J25 | CLK_PLL_IN | clock generator U17, pin 1 | - |
Table 44: Clock generator Si5345A external interfaces
<!-- Components on the Module, like Flash, PLL, PHY... --> |
The TEB0911 UltraRack is equipped with one System Controller CPLDs - Lattice Semiconductor LCMXO2-7000HC (MachXO2 Product Family) with the schematic designators U27. The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module. The functionalities and configuration of the pins depend on the CPLDs' firmware. The documentations of the firmware of SC CPLD U27 contains detailed information on this matter.
The Sytem Controller CPLDs are connected to the Zynq Ultrascale+ MPSoC through MIO pins. The signals of these pins are forwarded by the SC CPLD to control some of the on board peripherals.
Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS MIO pins:
For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.
The PS_1V8 and VCCINT_0V85 voltage levels are monitored by the voltage monitor circuit U89, which generates the POR_B signal to reset the board if voltage failure occurs. A manual reset is also possible by driving the pin 'MR' on SC CPLD, bank 4, pin L7 to GND.
<!-- Put in link to the Wiki reference page of the firmware of the SC CPLD. --> |
<!-- For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD. Add link to the Wiki reference page of the SC CPLD, if available. --> |
USB2 PHY U15 is provided by USB3320 from Microchip. The ULPI interface is connected to the Zynq Ultrascale+ PS USB0. I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator U16.
PHY Pin | Connected to | Notes |
---|---|---|
ULPI | PS bank MIO52 ... MIO63 | Zynq Ultrascale+ USB0 MIO pins are connected to the PHY |
REFCLK | - | 52MHz from on board oscillator U16 |
REFSEL[0..2] | - | All pins set to GND selects the external reference clock frequency (52.000000 MHz) |
RESETB | SC CPLD U27, bank 4, Pin: M2 | Low active USB2 PHY Reset (pulled-up to PS_1.8V) |
DP, DM | 4-port USB3 Hub U4 | USB2 data lane |
CPEN | - | External USB power switch active-high enable signal |
VBUS | 5V | Connected to USB VBUS via a series of resistors, see schematic |
ID | - | For an A-device connect to the ground. For a B-device, leave floating |
Table 45: USB PHY interface connections
On the TEB0911 board there are to 2 USB3 Super Speed ports available, which are also downward compatible to USB2 High Speed ports. The USB3 ports are provided by Cypress Semiconductor CYUSB3324 4-port USB3 Hub controller U4. The pin-strap configuration option of the USB3 Hub is disabled, so this controller gets the configuration data and parameter from the configuration EEPROM U5. The I²C interface of the EEPROM and the controller are also accessible by the Zynq Ultrascale+ MPSoC through I²C switch U37.
On the Upstream-side, this controller is connected to the MGT1 lane of MPSoC's PS GT bank 505 to establish the USB3 data lane. For the USB2 interface, the controller is connected to the on-board USB2 PHY U15. The USB2 PHY is connected via ULPI interface (MIO pins 52..63) to MPSoC's MIO bank.
The USB3 Hub controller has also an ARM Cortex-M0 controller integrated, refer to the data sheet for further features and programmable options.
On-board Gigabit Ethernet PHY U20 is provided with Marvell Alaska 88E1512. The Ethernet PHY RGMII interface is connected to the Zynq Ultrascale+ Ethernet0 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The 125MHz PHY output clock (PHY_CLK125M) is routed to System Controller CPLD U27, bank 4, pin K2.
All on-board and on-module peripherals with accessible I²C interface are muxed to the I²C interface of the Zynq Ultrascale+ MPSoC as master.
For this purpose, the TEB0911 board is equipped with two 8-channel I²C switches provided by TCA9548A from Texas Instruments, together creating up to 16 switched I²C channels.
Refer to the data sheet of the TCA9548A chip how to address and and transmit data to the I²C slave devices through this switches.
The on-board I2C bus works with reference voltage 3.3V, it is connected to the MPSoC I2C interface via PS MIO bank (pins MIO38, MIO39) and configured as master.
MIO | Signal Schematic Name | Notes |
---|---|---|
38 | I2C_SCL | 3.3V reference voltage |
39 | I2C_SDA | 3.3V reference voltage |
Table 46: MIO-pin assignment of the module's I2C interface
The I²C switches can be reseted simultanously by the pin 'I2C_RST', which is connected to SC CPLD U27, bank 4 pin L2 with low active logic.
I2C addresses (7 bit without read/write-bit) for on-board slave devices are listed in the table below:
I²C Slave Devices connected to MPSoC I²C Interface | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
---|---|---|---|
8-channel I²C switch U13 | - | 0x76 | I2C_SDA / I2C_SCL |
8-channel I²C switch U37 | - | 0x77 | I2C_SDA / I2C_SCL |
I²C Slave Devices connected to 8-channel I²C Switch U13 | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
FMC Connector J7 (FMC D) | 2 | 0x50 | FMCD_SDA / FMCD_SCL |
FMC Connector J6 (FMC E) | 3 | 0x50 | FMCE_SDA / FMCE_SCL |
FMC Connector J4 (FMC B) | 4 | 0x50 | FMCB_SDA / FMCB_SCL |
FMC Connector J8 (FMC C) | 5 | 0x50 | FMCC_SDA / FMCC_SCL |
PLL clock generator U17 Si5345A | 6 | 0x69 | PLL_SDA / PLL_SCL |
I²C Slave Devices connected to 8-channel I²C Switch U37 | I²C Switch Position | I²C Slave Address | Schematic Names of I²C Bus Lines |
FMC Connector J10 (FMC A) | 1 | 0x50 | FMCA_SDA / FMCA_SCL |
FMC Connector J21 (FMC F) | 2 | 0x50 | FMCF_SDA / FMCF_SCL |
SFP+ Connector J9A | 3 | 0x50 / 0x51 | SFP0_SDA / SFP0_SCL |
8-bit I²C IO Expander U86 (SPF+ connector control signals) | 3 | 0x27 | SFP0_SDA / SFP0_SCL |
SFP+ Connector J9B | 4 | 0x50 / 0x51 | SFP1_SDA / SFP1_SCL |
PLL clock generator U12 Si5338A | 5 | 0x70 | MEM_SDA / MEM_SCL |
Configuration EEPROM U83 | 5 | 0x51 | MEM_SDA / MEM_SCL |
Configuration EEPROM U45 | 5 | 0x52 | MEM_SDA / MEM_SCL |
Configuration EEPROM U60 | 5 | 0x53 | MEM_SDA / MEM_SCL |
Configuration EEPROM U57 | 5 | 0x57 | MEM_SDA / MEM_SCL |
SC CPLD U27 | 5 | user configurable | MEM_SDA / MEM_SCL |
DDR4 SODIMM I²C interface | 6 | module dependent | DDR4-SDA / DDR4-SCL |
USB3 Hub U4 | 7 | 0x60 | USBH_SDA / USBH_SCL |
USB3 Hub configuration EEPROM U5 | 7 | 0x51 | USBH_SDA / USBH_SCL |
Table 46: On-board peripherals' I2C-interfaces device slave addresses
The TEB0911 carrier board contains several EEPROMs for configuration and general user purposes. The EEPROMs are provided by Microchip and all have I²C interfaces:
EEPROM Modell | Schematic Designator | Memory Density | Purpose |
---|---|---|---|
24LC128-I/ST | U57 | 128 Kbit | user |
24AA025E48T-I/OT | U60 | 2 Kbit | user |
24AA025E48T-I/OT | U45 | 2 Kbit | user |
24AA025E48T-I/OT | U83 | 2 Kbit | user |
24LC128-I/ST | U5 | 128 Kbit | USB3 Hub U4 configuration memory |
Table 47: On-board configuration EEPROMs overview
On-board CAN FD (Flexible Data Rate) transceiver U48 is provided by Texas Instruments TCAN337. This controller is the physical layer of the CAN interface and is specified for data rates up to 1 Mbps. The controller has many protection features included to ensure CAN network robustness and to eliminate the need for additional protection circuits. Refer to the data sheet of this transceiver for more details and specifications.
The transceiver is connected to System Controller CPLD U27, means it works on this interface with 3.3V VCCIO. The logical signal processing of the CAN interface depends on the current firmware ot the SC CPLD.
On-board QSPI flash memory U24 and U25 on the TEB0911 board is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity each. The QSPI Flash memory ICs are connected to the PS MIO bank (Dual QSPI MIO0 ... MIO12) of the Zynq Ultrascale+ MPSoC. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the Zynq MPSoC allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
The TEB0911 board is also equipped with embedded MMC memory connected to the PS MIO bank (MIO13 ... MIO23) of the Zynq Ultrascale+ MPSoC. The memory is provided by MTFC4GACAJCN-4M IT from Micron Technology. It has a memory density of 32 Gbit (4 GByte) and is sectored into 8 banks a 4 Gbit.
IC | Name | Memory Density | Connected to | Notes |
---|---|---|---|---|
QSPI Flash U24 | N25Q256A11E1240E | 256 Mbit (32 MByte) | QSPI0: MIO0 ... MIO5 | dual parallel booting possible, 64 MByte total QSPI Flash memory connected via Dual QSPI MIO0 ... MIO12 |
QSPI Flash U25 | N25Q256A11E1240E | 256 Mbit (32 MByte) | QSPI0: MIO7 ... MIO12 | |
eMMC Flash U26 | MTFC4GACAJCN-4M IT | 32 Gbit (4 GByte) | SD0 eMMC: MIO13 ... MIO23 | bootable eMMC |
Table 48: On-board Flash memory ICs overview
Quad SPI Flash memory ICs U24 and U25 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.
eMMC Flash memory IC U25 is connected to Zynq MPSoC by pins MIO13 ... MIO23.
MIO | Signal Name | U24 Pin | MIO | Signal Name | U25 Pin | MIO | Signal Name | U25 Pin | ||
---|---|---|---|---|---|---|---|---|---|---|
0 | SPI Flash CLK | B2 | 7 | SPI Flash CS | C2 | 13 | MMC D0 | H3 | ||
1 | SPI Flash IO1 | D2 | 8 | SPI Flash IO0 | D3 | 14 | MMC D1 | H4 | ||
2 | SPI Flash IO2 | C4 | 9 | SPI Flash IO1 | D2 | 15 | MMC D2 | H5 | ||
3 | SPI Flash IO3 | D4 | 10 | SPI Flash IO2 | C4 | 16 | MMC D3 | J2 | ||
4 | SPI Flash IO0 | D3 | 11 | SPI Flash IO3 | D4 | 17 | MMC D4 | J3 | ||
5 | SPI Flash CS | C2 | 12 | SPI Flash CLK | B2 | 18 | MMC D5 | J4 | ||
19 | MMC D6 | J5 | ||||||||
20 | MMC D7 | J6 | ||||||||
21 | MMC CMD | W5 | ||||||||
22 | MMC CLKR | W6 | ||||||||
23 | MMC RST | U5 |
Table 49: PS MIO pin assignment of the Flash memory ICs
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
The TEB0911 board is equipped several on-board oscillators to provide the Zynq Ultrascale+ MPSoC's PS and PL banks and the on-board peripherals with reference clock-signals:
Clock Source | Schematic Name | Frequency | Clock Input Destination |
---|---|---|---|
SiTime SiT8008BI oscillator, U22 | PS_CLK | 33.333333 MHz | Zynq MPSoC PS Config Bank 503, pin U24 |
SiTime SiT8008AI oscillator, U16 | USB_CLK | 52.000000 MHz | USB2 transceiver PHY U15, pin 26 |
Kyocera CX3225SB26000, Y3 | - | 26.000 MHz | 4-port USB3 Hub U4, pin 68/69 |
Kyocera CX3225SB26000, Y2 |
| 54.000 MHz | PLL clock generator U17, pin 8/9 |
SiTime SiT8008BI oscillator, U21 | ETH_CLKIN | 25.000000 MHz | Gigabit Ethernet PHY U20, pin 34 |
SiTime SiT8008AI oscillator, U87 optional, not equipped | CLK_SC | 25.000000 MHz | System Controller CPLD U27, bank 2, pin AA9 |
SiTime SiT8008BI oscillator, U18 | IN0_P | 25.000000 MHz | PLL clock generator U17, pin 63 |
SiTime SiT8008AI oscillator, U85 | - | 25.000000 MHz | PLL clock generator U12, pin 3 |
DSC1123 oscillator, U92 optional, not equipped |
| 100.0000 MHz | PS GTR Bank 505 Lane 3, dedicated for DisplayPort, Pin U31, U32 |
Table 50: Reference clock signal oscillators
There is a Si5338A U12, Silicon Labs I2C programmable quad PLL clock generator on-board to generate various reference clocks for the Zynq MPSoC MGT banks and on-board peripherals.
Si5338A Pin | Signal Name / Description | Connected To | Direction | Note |
---|---|---|---|---|
IN1 | CLK8_N | U17, pin 54 | Input | Differential reference clock input from PLL clock generator U17 |
IN2 | CLK8_P | U17, pin 53 | Input | |
IN3 | Reference input clock | U85, pin 3 | Input | 25.000000 MHz oscillator, Si8008AI |
IN4 | - | GND | Input | LSB (pin 'IN4') of the default I²C-adress 0x70 not set |
IN5 | - | Not connected | Input | Not used |
IN6 | - | GND | Input | Not used |
CLK0A | SSD_RCLK_P | U2, pin 55 | Output | NGFF M.2 PCIe socket (Key M), |
CLK0B | SSD_RCLK_N | U2, pin 53 | Output | |
CLK1A | B505_CLK2_N | U1, pin U27 | Output | PS GTR Bank 505 Lane 2, dedicated for DisplayPort, |
CLK1B | B505_CLK2_P | U1, pin U28 | Output | |
CLK2A | B505_CLK1_N | U1, pin W27 | Output | PS GTR Bank 505 Lane 1, dedicated for USB3 interface |
CLK2B | B505_CLK1_P | U1, pin W28 | Output | |
CLK3A | B505_CLK0_P | U1, pin AA27 | Output | PS GTR Bank 505 Lane 0, dedicated for SSD interface |
CLK3B | B505_CLK0_N | U1, pin AA28 | Output |
Table 51: Programmable quad PLL clock generator inputs and outputs
Following table shows on-board Silicon Labs I2C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:
Si5345A Pin | Signal Name / Description | Connected To | Direction | Note |
---|---|---|---|---|
IN0 | IN0_P | not connected | Input | Not used |
IN0_N | GND | |||
IN1 | IN1_P | SMA Coax J25, pin 1 | Input | external reference clock input |
IN1_N | GND | |||
IN2 | - | not connected | Input | not used |
- | not connected | |||
IN3 | - | not connected | Input | not used |
- | not connected | |||
OUT0 | CLK0_P | not connected | Output | not used |
CLK0_N | not connected | |||
OUT1 | CLK1_P | U1, pin E8 | Output | GTH bank 229 reference clock input |
CLK1_N | U1, pin E7 | |||
OUT2 | CLK2_P | U1, pin B10 | Output | GTH bank 230 reference clock input |
CLK2_N | U1, pin B9 | |||
OUT3 | CLK3_P | U1, pin J8 | Output | GTH bank 228 reference clock input |
CLK3_N | U1, pin J7 | |||
OUT4 | CLK4_P | U1, pin N27 | Output | GTH bank 128 reference clock input |
CLK4_N | U1, pin N28 | |||
OUT5 | CLK5_P | U1, pin J27 | Output | GTH bank 129 reference clock input |
CLK5_N | U1, pin J28 | |||
OUT6 | CLK6_P | U1, pin E27 | Output | GTH bank 130 reference clock input |
CLK6_N | U1, pin E28 | |||
OUT7 | CLK7_P | U27, pin E1 | Output | Clock signal input to SC CPLD, bank 5 |
CLK7_N | not connected | |||
OUT8 | CLK8_P | U12, pin 2 | Output | Differential reference clock input to |
CLK8_N | U12, pin 1 | |||
OUT9 | - | not connected | Output | not used |
- | not connected | |||
XA/XB | XAXB_P | 54.000 MHz quartz oscillator Y1 | Input | Differential quartz oscillator clock input |
XAXB_N |
Table 52: Programmable 10-output PLL clock generator inputs and outputs
Note: The PLL clock generator U17 can be reseted by the pin 'PLL_RST', which is connected to SC CPLD U27, bank 4 pin L4 with low active logic.
The TEB0911 board is equipped with several LEDs to signal current states and activities.
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D6 | red | Zynq MPSoC U1, pin W21 | Reflects inverted DONE signal. ON when FPGA is not configured, |
D17 | green | USB3 Hub U4, pin 25 | LED is on if all USB3 and USB2 ports are in the suspend state and is |
D18 | green | USB3 Hub U4, pin 4 | LED output for downstream 1 port |
D19 | green | USB3 Hub U4, pin 63 | LED output for downstream 3 port |
D2 | red | SC CPLD U27, bank 2, pin AB17 | SFP+ interface status LED |
D4 | green | SC CPLD U27, bank 2, pin AB18 | SFP+ interface status LED |
D3 | red | SC CPLD U27, bank 2, pin AA16 | SFP+ interface status LED |
D5 | green | SC CPLD U27, bank 2, pin AB15 | SFP+ interface status LED |
D13 | green | SC CPLD U27, bank 2, pin U12 | functionality depends on the current firmware of the SC CPLD U27 |
D14 | green | SC CPLD U27, bank 2, pin V12 | |
D15 | green | SC CPLD U27, bank 2, pin W12 | |
D1 | red | SC CPLD U27, bank 2, pin V13 |
Table 53: On-board LEDs
There are two switch buttons available to the user connected to the SC CPLD U27:
Button | Color | Connected to | Description and Notes |
---|---|---|---|
D6 | red | Zynq MPSoC U1, pin W21 | Reflects inverted DONE signal. ON when FPGA is not configured, |
D17 | green | USB3 Hub U4, pin 25 | LED is on if all USB3 and USB2 ports are in the suspend state and is |
D2 | red | SC CPLD U27, bank 2, pin AB17 | SFP+ interface status LED |
D4 | green | SC CPLD U27, bank 2, pin AB18 | SFP+ interface status LED |
D3 | red | SC CPLD U27, bank 2, pin AA16 | SFP+ interface status LED |
D5 | green | SC CPLD U27, bank 2, pin AB15 | SFP+ interface status LED |
D13 | green | SC CPLD U27, bank 2, pin U12 | functionality depends on the current firmware of the SC CPLD U27 |
D14 | green | SC CPLD U27, bank 2, pin V12 | |
D15 | green | SC CPLD U27, bank 2, pin W12 | |
D1 | red | SC CPLD U27, bank 2, pin V13 |
<!-- If power sequencing and distribution is not so much, you can join both sub sections together --> |
The maximum power consumption of the board mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Power Input | Typical Current |
---|---|
24V VIN | TBD* |
Table : Typical power consumption, *to Be Determined soon with reference design setup.
Power supply with minimum current capability of ?? A for system startup is recommended.
The TEB0911 UltraRack board is equipped with the Xilinx Zynq UltraScale+ MPSoC delivers a heterogeneous multi-processing system with integrated programmable logic and independently operable elements and is designed to meet embedded system power management requirement by advanced power management features. This features allow to offset the power and heat constraints against overall performance and operational efficiency.
This features allowing highly flexible power management are achieved by establishing Power Domains for power isolation. The Zynq UltraScale+ MPSoC has multiple power domains, whereby each power domain requires its own particular on-board DC-DC converters.
The Processing System contains three Power Domains:
There are following dependencies how the initial 24V voltage from the main power jack J34 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:
To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
The TEB0911 UltraRack board meets the recommended criteria to power up the Xilinx Zynq UltraScale+ MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular Power Domains and powering up the on-board voltages.
On the TEB0911 UltraRack board following Power Domains will be powered up in a certain sequence with by enable and power-good signals of the DC-DC converters, which are controlled by the System Controller CPLD U27:
Hence, those three power instances will be powered up consecutively and the Power-Good-Signals of the previous instance is asserted.
Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.
Figure : Module power-on diagram.
Temp core dc
NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.
Power Rail Name | B2B JM1 Pins | B2B JM2 Pins | Direction | Notes |
---|---|---|---|---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Main supply voltage from the carrier board. |
3.3V | - | 10, 12, 91 | Output | Module on-board 3.3V voltage supply. (would be good to add max. current allowed here if possible) |
B64_VCO | 9, 11 | - | Input | HR (High Range) bank voltage supply from the carrier board. |
VBAT_IN | 79 | - | Input | RTC battery supply voltage from the carrier board. |
... | ... | ... | ... | ... |
Table : Module power rails
Bank | Schematic Name | Voltage | Voltage Range |
---|---|---|---|
500 (MIO0) | PS_1.8V | 1.8V | - |
501 (MIO1) | PS_1.8V | 1.8V | - |
502 (DDR3) | 1.35V | 1.35V | - |
12 HR | VCCIO_12 | User | HR: 1.2V to 3.3V |
13 HR | VCCIO_13 | User | HR: 1.2V to 3.3V |
33 HP | VCCIO_33 | User | HP: 1.2V to 1.8V |
34 HP | VCCIO_34 | User | HP: 1.2V to 1.8V |
35 HP | VCCIO_35 | User | HP: 1.2V to 1.8V |
Table : Module PL I/O bank voltages
NB! Note that here we look at the module as a whole, so you just can't rely only on junction temperature or max voltage of particular SoC or FPGA chip on the module. See examples in the table below.
Module Variant | FPGA / SoC | Operating Temperature | Temperature Range |
---|---|---|---|
TE0710-02-35-2CF | XC7A35T-2CSG324C | 0°C to +70°C | Commercial |
TE0715-04-30-3E | XC7Z030-3SBG485E | 0°C to +85°C | Extended |
TE0841-01-035-1I | XCKU035-1SFVA784I | –40°C to +85°C | Industrial |
.. | .. | .. | .. |
Table : Module variants
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | V | - | ||
Storage temperature | °C | - |
Table : Module absolute maximum ratings
Assembly variants for higher storage temperature range are available on request. |
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | ||||
Operating temperature |
Table : Module recommended operating conditions
Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings. |
Commercial grade: 0°C to +70°C.
Extended grade: 0°C to +85°C.
Industrial grade: -40°C to +85°C.
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Module size: ... mm × ... mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: ... mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Put mechanical drawings here...
Figure : Module physical dimensions drawing.
Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
- | 01 | Prototypes |
Table : Module hardware revision history
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Put picture of actual PCB showing model and hardware revision number here...
Figure : Module hardware revision number.
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Date | Revision | Contributors | Description |
---|---|---|---|
Ali Naseri | Initial document |
Table : Document change history