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Overview

The Trenz Electronic TEF1001 FPGA board is a PCI Express form factor card (PCIe 2.0 or higher) integrating the Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC. The FPGA-board is designed for high system resources and intended for use in applications with high demands on system performance and throughput. To extent the board with standard DDR3 SDRAM memory module, there is a 204-pin SODIMM socket with 64bit databus width on the board present.

The board offers a HPC (High Pin Count) ANSI/VITA 57.1 compatible FMC interface connector for standard FPGA Mezzanine cards and modules. Other interface connectors found on-board include JTAG for accessing FPGA and on-board System Controller CPLD, and also connector with 5 high-speed I/O differential signaling pairs.

The TEF1001 FPGA board is intended to be used as add-on card in a PCIe 2.0 or higher capable host systems, it can not be used as a stand-alone device.

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Refer to http://trenz.org/tef1001-info for the current online version of this manual and other available documentation.

Key Features

• Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC
• Large number of configurable I/Os are provided via rugged HPC FMC connector
• Dual ARM Cortex-A9 MPCore
  • 1 GByte RAM (32-Bit wide DDR3)
  • 32 MByte QSPI Flash memory
  • 2 x Hi-Speed USB2 ULPI transceiver PHY
  • 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
  • 4 GByte eMMC (optional up to 64 GByte)
• 2 x MAC-address EEPROMs
• Optional 2x 64 MByte HyperFLASH or 2x 8 MByte HyperRAM (max 2x 32 MByte HyperRAM)
• Temperature compensated RTC (real-time clock)
• Si5338A programmable quad PLL clock generator for GTX transceiver clocks
• Plug-on module with 3 x 160-pin high-speed strips
  • 16 GTX high-performance transceiver
  • 2x GT transceiver clock inputs
  • 254 FPGA I/O's (125 LVDS pairs)
• On-board high-efficiency switch-mode DC-DC converters
• System management
• eFUSE bit-stream encryption
• AES bit-stream encryption
• Evenly-spread supply pins for good signal integrity
• User LED
• PCI Express 2.0 x8 card with maximum throughput of 4 GB/s
• FMC High Pin Count (HPC) connector
• 8 FPGA MGT lanes available on PCIe interface
• DDR3 SO-DIMM SDRAM socket
• 256-Mbit (32-MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
  • FPGA
  • JTAG port (SPI indirect, bus width x4)
• External clock input via SMA coaxial connector
• 28 GTH transceivers, each with up to 13.1 Gbit/s data transmission rate
• FPGA configuration through:
  • JTAG connector
  • Quad SPI Flash memory
• Programmable quad clock generator

• TI LMK04828B ultra low-noise JESD204B compliant clock jitter cleaner

• On-board high-efficiency DC-DC converters
• Up to 202 FPGA I/O pins available on FMC connector (up to 101 LVDS pairs possible)
• System management and power sequencing
• AES bit-stream encryption
• eFUSE bit-stream encryption
• Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
• 2 banks of 1024 MByte DDR4 SDRAM, 32bit wide memory interface
• 512 Mbit (64 MByte) QSPI Flash
• 3 x Samtec Razor Beam LSHM B2B, 260 terminals total
  - 60 x HR I/Os
  - 84 x HP I/Os
  - 8 x GTH transceiver lanes (TX/RX)
  - 2 x MGT external clock inputs
• Clocking
  - Si5338 - 4 output PLLs, GT and PL clocks
  - 200 MHz LVDS oscillator
• All power supplies on-board, single power source operation
• Evenly spread supply pins for optimized signal integrity
• Size: 40 x 50 mm
• 3 mm mounting holes for skyline heat spreader
• Rugged for industrial applications
  
  
  

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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Main Components

1. Xilinx Kintex XC7K-2FBG676I FPGA SoC, U6
2. ANSI/VITA 57.1 compliant FMC HPC connector, J2
3. Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
4. PCIe x8 connector, J1
5. SO-DIMM socket, U2
6. 6-pin 12V power connector, J5
7. Step-down DC-DC converter @1.5V and @4V (LT LTM4676A), U3
8. Step-down DC-DC converter @1.0V (LT LTM4676A), U4
9. 256 Mbit Quad SPI Flash Memory (Micron N25Q256A), U12
10. 10x Green user LEDs connected to FPGA, D1 ... D10
11. 4-wire PWM fan connector, J4
12. User button, S2
13. FPGA JTAG connector, J9
14. 4bit DIP switch, S1
15. I²C header for LTM4676A DC-DC converter, J10
16. System Controller CPLD JTAG header, J8
17. 1x Green LED connected to SC CPLD, D11
18. 2-pin 5V FAN header, J6
19. System Controller CPLD (Lattice Semiconductor LCMXO2-1200HC), U5
20. 6A PowerSoC DC-DC converter @FMC_VADJ (Altera EN5365QI), U7
21. 4A PowerSoC DC-DC converter @3.3V (3V3FMC) (Altera EN6347QI), U15
22. LDO converter @1.2V (MGTAVTT_FPGA) (TI TPS74401RGW), U17
23. LDO converter @1.0V (MGTAVCC_FPGA) (TI TPS74401RGW), U18
24. 4A PowerSoC DC-DC converter @1.8V (Altera EN6347QI), U7

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

Boot Process

By default the configuration mode pins M[2:0] of the FPGA are set to QSPI mode (Master SPI), hence the FPGA is configured from serial NOR flash at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memory.

Signals, Interfaces and Pins

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FMC HPC Connector I/Os

I/O signals connected to the SoCs I/O bank and B2B connector:

Table 2: General overview of FPGA's PL I/O signals connected to the FMC connector

For detailed information about the pin out, please refer to the Pin-out Tables.

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PCI Express Interface

The TEF1001 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots (PCIe 2.0 or higher) and is PCIe Gen. 2 capable. See next section for the overview of FPGA MGT lanes routed to the PCIe interface.

MGT Lanes

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. The MGT lanes are connected to the FMC connector and to the PCIe x8 connector. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:

Table 3: FPGA to B2B connectors routed MGT lanes overview

Below are listed MGT banks reference clock sources:

Table 4: MGT reference clock sources

JTAG Interface

There are three JTAG interfaces available on the TEF1001 board:

Table 5: JTAG interface signals

System Controller CPLD I/O Pins

Special purpose pins are connected to the System Controller CPLD and have following default configuration:

Table 6: System Controller CPLD I/O pins

For detailed function of the pins and signals, the internal signal assignment and the implemented logic, look to the Wiki reference page of the module's SC CPLD or into its bitstream file.

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Quad SPI Interface

Quad SPI interface is connected to the FPGA configuration bank 0.

Table 7: Quad SPI interface signals and connections

I2C Interface

On-module I²C interface is routed  from PL bank 65 I/O pins (PLL_SCL and PLL_SDA) to the I²C interface of Si5338 PLL quad clock generator U2, also two further pins of bank 65 can be used as external I²C interface of the modue:

Table 8: I²C slave device addresses

On-board Peripherals

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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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DDR3 SD-RAM SODIMM Socket

By default TE0841 module has two K4A8G165WB-BIRC DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-module RAM. Different memory sizes are available optionally.

Quad SPI Flash Memory

On-module QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q512A11G1240E with 512-Mbit (64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Programmable Clock Generator

There is a Silicon Labs I²C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.

 Table 9: Programmable quad PLL clock generator inputs and outputs, *PCB REV01 is not programmed

Oscillators

The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Table 10: Reference clock signals

On-board LEDs

Table 11: On-board LEDs

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 12: Typical power consumption

 * TBD - To Be Determined soon with reference design setup.

Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Power Distribution Dependencies

See also Xilinx datasheet DS892 for additional information. User should also check related base board documentation when intending base board design for TE0841 module.

Power-On Sequence

The TE0841 SoM meets the recommended criteria to power up the Xilinx FPGA properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the FPGA chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Power Rails

Table 13: Module power rails

Bank Voltages

Table 14: Module PL I/O bank voltages

Variants Currently In Production

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See also the current available variants on the Trenz Electronic shop page

Technical Specifications

Absolute Maximum Ratings

Table 16: Module absolute maximum ratings

Recommended Operating Conditions

Table 17: Module recommended operating conditions

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: 8 mm.

• PCB thickness: 1.65 mm.

• Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Revision History

Hardware Revision History

Table 18: Module hardware revision history

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Date	Revision	Contributors	Description
			Initial document.

Table 18: Document change history

Disclaimer

02 Sept 2017