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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
Table of contents |
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MicroBlaze Design with HyperRAM memory test example.
This reference designs is bundled with a FREE evaluation edition of the commercially proven, low-cost, low-circuit area, high performance, HyperBus Memory Controller (HBMC) IP supplied by Synaptic Laboratories Ltd. Synaptic Labs HBMC IP is commercially proven in both Intel and Xilinx projects, and was selected by Intel. This FREE HBMC IP evaluation license never expires, and no customer registration or NIC ID is required.
You can check for and obtain the latest version of the FREE evaluation HBMC IP from S/Labs website for Xilinx on S/Labs HBMC IP (Free Trail IP) . Please send your HBMC IP support questions to info@synaptic-labs.com
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Date | Vivado | Project Built | Authors | Description |
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2018-06-05 | 2017.4 | TE0725-HyperRAM_noprebuilt-vivado_2017.4-build_10_20180605162539.zip TE0725-HyperRAM-vivado_2017.4-build_10_20180605162425.zip | John Hartfiel |
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Issues | Description | Workaround | To be fixed version |
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No known issues | --- | --- | --- |
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Software | Version | Note |
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Vivado | 2017.4 | needed |
SDK | 2017.4 | needed |
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
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TE0725-03-15-1C | 15_1c | REV01, REV02, REV03 | --- | 32 | 8MB HypeRAM | |
TE0725-03-35-2C | 35_2c | REV01, REV02, REV03 | --- | 32 | 8MB HypeRAM | |
TE0725-03-100-2C | 100_2c | REV01, REV02, REV03 | --- | 32 | 8MB HypeRAM | |
TE0725-03-100-2CF | 100_2c | REV01, REV02, REV03 | --- | 32 | 8MB HypeRAM | POF assembled |
TE0725-03-100-2I9 | 100_2i | REV01, REV02, REV03 | --- | 32 | 8MB HypeRAM |
Design supports following carriers:
Carrier Model | Notes |
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--- |
Additional HW Requirements:
Additional Hardware | Notes |
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TE0790 JTAG Programmer | It's not recommended to use TE0790 for power supply( TE0790 TRM#PowerandPower-OnSequence) |
External power supply |
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For general structure and of the reference design, see Project Delivery
Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
Type | Location | Notes |
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<!-- <table width="100%"> <tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr> <tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr> <tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr> <tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr> <tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr> <tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr> <tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr> <tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr> <tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr> <tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr> <tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr> <tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr> <tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr> <tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr> </table> --> |
File | File-Extension | Description |
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BIT-File | *.bit | FPGA (PL Part) Configuration File |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Not used on this Example.
HBMC IP is a 10 minute run-time limited evaluation version of the full-edition |
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
set_property PACKAGE_PIN A13 [get_ports HB_CLK0_0] set_property PACKAGE_PIN A14 [get_ports HB_CLK0n_0] set_property PACKAGE_PIN E17 [get_ports {HB_dq_0[0]}] set_property PACKAGE_PIN B17 [get_ports {HB_dq_0[1]}] set_property PACKAGE_PIN F18 [get_ports {HB_dq_0[2]}] set_property PACKAGE_PIN F16 [get_ports {HB_dq_0[3]}] set_property PACKAGE_PIN G17 [get_ports {HB_dq_0[4]}] set_property PACKAGE_PIN D18 [get_ports {HB_dq_0[5]}] set_property PACKAGE_PIN B18 [get_ports {HB_dq_0[6]}] set_property PACKAGE_PIN A16 [get_ports {HB_dq_0[7]}] set_property PACKAGE_PIN E18 [get_ports HB_RWDS_0] set_property PACKAGE_PIN D17 [get_ports HB_CS1n_0] set_property PACKAGE_PIN J17 [get_ports HB_RSTn_0] #set_property PACKAGE_PIN A18 [get_ports HB_CS0n_0 ] #set_property PACKAGE_PIN J18 [get_ports HB_INTn_0 ] #set_property PACKAGE_PIN C17 [get_ports HB_RSTOn_0] # # FPGA Pin Voltage assignment # set_property IOSTANDARD LVCMOS18 [get_ports HB_CLK0_0] set_property IOSTANDARD LVCMOS18 [get_ports HB_CLK0n_0] set_property IOSTANDARD LVCMOS18 [get_ports {HB_dq_0[*]}] set_property IOSTANDARD LVCMOS18 [get_ports HB_CS1n_0] set_property IOSTANDARD LVCMOS18 [get_ports HB_RSTn_0] set_property IOSTANDARD LVCMOS18 [get_ports HB_RWDS_0] #set_property IOSTANDARD LVCMOS18 [get_ports HB_CS0n_0] #set_property IOSTANDARD LVCMOS18 [get_ports HB_INTn_0] #set_property IOSTANDARD LVCMOS18 [get_ports HB_RSTOn_0] #set_property PULLUP true [get_ports HB_RSTOn_0] #set_property PULLUP true [get_ports HB_INTn_0] # #Hyperbus Clock - change according to clk pin on PLL # create_generated_clock -name clk_0 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock sys_clock [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0] create_generated_clock -name clk_90 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock sys_clock [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT1] create_generated_clock -name clk_180 -source [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKIN1] -master_clock sys_clock [get_pins msys_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT2] # #100Mhz clock freqeuncy - change accordingly # set hbus_freq_ns 10 set dqs_in_min_dly -0.5 set dqs_in_max_dly 0.5 set HB_dq_ports [get_ports HB_dq_0[*]] # #Create RDS clock and RDS virtual clock # create_clock -period $hbus_freq_ns -name rwds_clk [get_ports HB_RWDS_0] create_clock -period $hbus_freq_ns -name virt_rwds_clk # #Input Delay Constraint - HB_RWDS-HB_DQ # set_input_delay -clock [get_clocks virt_rwds_clk] -max ${dqs_in_max_dly} ${HB_dq_ports} set_input_delay -clock [get_clocks virt_rwds_clk] -clock_fall -max ${dqs_in_max_dly} ${HB_dq_ports} -add_delay set_input_delay -clock [get_clocks virt_rwds_clk] -min ${dqs_in_min_dly} ${HB_dq_ports} -add_delay set_input_delay -clock [get_clocks virt_rwds_clk] -clock_fall -min ${dqs_in_min_dly} ${HB_dq_ports} -add_delay set_multicycle_path -setup -end -rise_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] 0 set_multicycle_path -setup -end -fall_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] 0 set_false_path -fall_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] -setup set_false_path -rise_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] -setup set_false_path -fall_from [get_clocks virt_rwds_clk] -fall_to [get_clocks rwds_clk] -hold set_false_path -rise_from [get_clocks virt_rwds_clk] -rise_to [get_clocks rwds_clk] -hold set_false_path -from [get_clocks clk_0] -to [get_clocks rwds_clk] set_false_path -from [get_clocks rwds_clk] -to [get_clocks clk_0] # #Output Delay Constraint - HB_CLK0-HB_DQ # create_generated_clock -name HB_CLK0_0 -source [get_pins */*/*/U_IO/U_CLK0/dq_idx_[0].ODDR_inst/C] -multiply_by 1 -invert [get_ports HB_CLK0_0] set_output_delay -clock [get_clocks HB_CLK0_0] -min -1.000 ${HB_dq_ports} set_output_delay -clock [get_clocks HB_CLK0_0] -max 1.000 ${HB_dq_ports} set_output_delay -clock [get_clocks HB_CLK0_0] -min -1.000 ${HB_dq_ports} -clock_fall -add_delay set_output_delay -clock [get_clocks HB_CLK0_0] -max 1.000 ${HB_dq_ports} -clock_fall -add_delay set_false_path -from [get_pins */*/*/U_HBC/*/dq_io_tri_reg/C] -to ${HB_dq_ports} set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_1_reg/CLR] set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_2_reg/CLR] set_false_path -from * -to [get_pins */*/inst/*/i_iavs0_270_rstn_3_reg/CLR] |
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For SDK project creation, follow instructions from:
Xilinx default memory test.
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No additional software is needed.
To get content of older revision got to "Change History" of this page and select older document revision number.
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v.2 | John Hartfiel |
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2018-05-06 | v.1 |
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