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Table of Contents |
The Trenz Electronic TEF1001 FPGA board is a PCI Express form factor card (PCIe 2.0 or higher) integrating the Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC. The FPGA-board is designed for high system resources and intended for use in applications with high demands on system performance and throughput. To extent the board with standard DDR3 SDRAM memory module, there is a 204-pin SODIMM socket with 64bit databus width on the board present.
The board offers a HPC (High Pin Count) ANSI/VITA 57.1 compatible FMC interface connector for standard FPGA Mezzanine cards and modules. Other interface connectors found on-board include JTAG for accessing FPGA and on-board System Controller CPLD, and also connector with 5 high-speed I/O differential signaling pairs.
The TEF1001 FPGA board is intended to be used as add-on card in a PCIe 2.0 or higher capable host systems, it can not be used as a stand-alone device.
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Refer to http://trenz.org/tef1001-info for the current online version of this manual and other available documentation. |
TI LMK04828B ultra low-noise JESD204B compliant clock jitter cleaner
Additional assembly options are available for cost or performance optimization upon request.
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Storage device name | Content | Notes |
---|---|---|
Si5338A OTP Area | not programmed | - |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | - |
SPI Flash main array | demo design | - |
HyperFlash Memory | not programmed | - |
eFUSE USER | Not programmed | - |
eFUSE Security | Not programmed | - |
Table 1: Initial delivery state of programmable devices on the module
By default the configuration mode pins M[2:0] of the FPGA are set to QSPI mode (Master SPI), hence the FPGA is configured from serial NOR flash at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memory.
<!-- Connections and Interfaces or B2B Pin's which are accessible by User --> |
I/O signals connected to the SoCs I/O bank and FMC connector J2:
FPGA Bank | Type | I/O Signal Count | Bank VCCO Voltage | Notes |
---|---|---|---|---|
12 | HR | 48 IO's, 24 LVDS pairs | FMC_VADJ | Bank voltage supplied by DC-DC converter U7 |
13 | HR | 34 IO's, 17 LVDS pairs | FMC_VADJ | |
15 | HR | 34 IO's, 17 LVDS pairs | FMC_VADJ | |
16 | HR | 44 IO's, 22 LVDS pairs | VIO_B_FMC | Bank voltage supplied by FMC connector J2 |
Table 2: General overview of FPGA's PL I/O signals connected to the FMC connector
For detailed information about the pin out, please refer to the Pin-out Tables.
<!-- TO-DO (future): If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module. --> |
The TEF1001 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots (PCIe 2.0 or higher) and is PCIe Gen. 2 capable. See next section for the overview of FPGA MGT lanes routed to the PCIe interface.
<!-- MGT lanes should be listed separately, as they are more specific than just general I/Os. --> |
MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. The MGT lanes are connected to the FMC connector and to the PCIe x8 connector. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:
Lane | Bank | Type | Signal Name | PCIe Connector Pin | FPGA Pin |
---|---|---|---|---|---|
0 | 115 | GTX |
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1 | 115 | GTX |
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2 | 115 | GTX |
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3 | 115 | GTX |
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Lane | Bank | Type | Signal Name | FMC Connector Pin | FPGA Pin |
0 | 116 | GTX |
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1 | 116 | GTX |
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2 | 116 | GTX |
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3 | 116 | GTX |
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Table 3: FPGA to B2B connectors routed MGT lanes overview
Below are listed MGT banks reference clock sources:
Clock signal | Bank | Source | FPGA Pin | Notes |
---|---|---|---|---|
MGTCLK_5338_P | 115 | U13, CLK1A | MGTREFCLK0P_115, H6 | Supplied by on-board Si5338A |
MGTCLK_5338_N | U13, CLK1B | MGTREFCLK0N_115, H5 | ||
PCIE_CLK_P | 115 | J1-A13, REFCLK+ | MGTREFCLK1P_115, K6 | External clock from PCIe slot |
PCIE_CLK_N | J1-A14, REFCLK- | MGTREFCLK1N_115, K6 | ||
GBTCLK0_M2C_P | 116 | J2-D4 | MGTREFCLK0P_116, D6 | External clock from FMC connector |
GBTCLK0_M2C_N | J2-D5 | MGTREFCLK0N_116, D5 | ||
GBTCLK1_M2C_P | 116 | J2-B20 | MGTREFCLK1P_116, F6 | External clock from FMC connector |
GBTCLK1_M2C_N | J2-B21 | MGTREFCLK1N_116, F5 |
Table 4: MGT reference clock sources
There are three JTAG interfaces available on the TEF1001 board:
JTAG Interface | Signal Schematic Name | JTAG Connector Pin | Connected to |
---|---|---|---|
CPLD JTAG VCCIO: 3.3V Connector: J8 | CPLD_JTAG_TMS | J8-1 | SC CPLD, bank 0, pin 90 |
CPLD_JTAG_TDI | J8-2 | SC CPLD, bank 0, pin 94 | |
CPLD_JTAG_TDO | J8-3 | SC CPLD, bank 0, pin 95 | |
CPLD_JTAG_TCK | J8-4 | SC CPLD, bank 0, pin 91 | |
FPGA JTAG VCCIO: 1.8V Connector: J9 | FPGA_JTAG_TMS | J9-4 | FPGA, bank 0, pin N9 |
FPGA_JTAG_TCK | J9-6 | FPGA, bank 0, pin M8 | |
FPGA_JTAG_TDO | J9-8 | FPGA, bank 0, pin N8 | |
FPGA_JTAG_TDI | J9-10 | FPGA, bank 0, pin L8 | |
FMC JTAG VCCIO: 3.3V Connector: J2 | FMC_TRST | J2-D34 | SC CPLD, bank 2, pin 36 |
FMC_TCK | J2-D29 | SC CPLD, bank 2, pin 27 | |
FMC_TMS | J2-D33 | SC CPLD, bank 2, pin 28 | |
FMC_TDI | J2-D30 | SC CPLD, bank 2, pin 31 | |
FMC_TDO | J2-D31 | SC CPLD, bank 2, pin 32 |
Table 5: JTAG interface signals
Special purpose pins are connected to the System Controller CPLD and have following default configuration:
Pin Name | SC CPLD Direction | Function | Default Configuration |
---|---|---|---|
JTAG_EN | Input | JTAG select | Low for normal operation |
nRST_SC0 | Input | Reset | Low active board reset input |
SC1 | - | - | not currently used ('BOOTMODE' in default B2B pin out') |
SC2 | Input / Output | - | Power good signal ('PGOOD' in default B2B pin out) |
SC3 | Input | - | Power enable pin ('EN1' in default B2B pin out) |
SC4 | - | - | not currently used ('NOSEQ' in default B2B pin out') |
F_TCK | Output | JTAG signals between | B2B JTAG signals are forwarded to the FPGA through SC CPLD. |
F_TMS | Output | ||
F_TDI | Output | ||
F_TDO | Input | ||
TCK | Input | JTAG signals between SC CPLD and B2B connector | Program FPGA or SC CPLD depending on pin JTAGMODE. |
TMS | Input | ||
TDI | Input | ||
TDO | Output | ||
PROG_B | Output | FPGA configuration | PL configuration reset signal. |
DONE | Input | FPGA configuration done | PL configuration completed. |
PUDC_B | Output | Pull up during configuration | PL I/O's are 3-stated until configuration of the FPGA completes. |
INIT_B | Input | Initialization done | Low active FPGA initialization pin or configuration error signal. |
EN_PL | Input | Enable PL Power DC-DC converters | Set to contant logical high. |
CPLD_IO | Output | user I/O | Connected to FPGA Bank 45, pin P28. |
Table 6: System Controller CPLD I/O pins
CPLD Functionality | Interface | Designated CPLD Pins | Connected to | Notes |
---|---|---|---|---|
I2C interface between on-board peripherals and FPGA | I2C |
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| VCCIO: 1V8, all with pull-up to 1V8. Following devices and connectors are linked to the FPGA_IIC I2C interface:
Note: FPGA_IIC_OE must kept high for I2C operation. For I2C slave device addresses refer to the component datasheets. |
User I/Os External LVDS pairs | 10 I/Os 5 x LVDS pairs |
|
| Can also be used for single-ended signaling. |
User I/Os Internal LVDS pairs | 13 I/Os 6 x LVDS pairs |
|
| VCCIO: 1V8 Can also be used for single-ended signaling. FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and clock synthesizer U9 (FCLK). Internal signal assignment: FEX_DIR <= FMC_PRSNT_M2C_L |
FPGA programming control and state | 2 I/Os |
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| VCCIO: 1V8 |
I2C interface to programmable quad clock generator | I2C |
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| VCCIO: 1V8 Only PLL_SDA has 1V8 pull-up. |
Fan PWM control J4 | 2 I/Os |
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| Internal signal assignment:
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Button S2 | 1 I/O |
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| Functionality depends on CPLD firmware, activating pin PROGRAM_B (active low) and LED1 in standard configuration. |
LED1 | 1 I/O |
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| Fast blinking, when FPGA is not programmed. Internal signal assignment:
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PCIe control line RESET_B | 1 I/O |
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| Internal signal assignment:
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Control interface to clock synthesizer U9 (TI LMK04828B) | SPI (3 I/Os), 4 I/Os |
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| Pull up to 3V3PCI.
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Control Interface to DC-DC converters U3 and U4 (both LTM4676) | I2C (2 I/Os), 2 I/Os |
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| 3V3 pull-ups. LTM I2C interface is also accessible trough header J10. LTM1_ALERT and LTM2_ALERT signals are not used. |
Power-on sequence and monitoring | 6 I/Os |
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| Sequence of the supply voltages depend on the System Controller CPLD firmware. EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up. PG signals will not be evaluated. |
For detailed function of the pins and signals, the internal signal assignment and the implemented logic, look to the Wiki reference page of the module's SC CPLD or into its bitstream file.
<!-- For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD. Add link to the Wiki reference page of the SC CPLD, if available. --> |
Quad SPI interface is connected to the FPGA configuration bank 0.
Signal Name | QSPI Flash Memory U6 Pin | FPGA Pin |
---|---|---|
SPI_CS | C2 | RDWR_FCS_B_0, AH7 |
SPI_D0 | D3 | D00_MOSI_0, AA7 |
SPI_D1 | D2 | D01_DIN_0, Y7 |
SPI_D2 | C4 | D02_0, U7 |
SPI_D3 | D4 | D03_0, V7 |
SPI_CLK | B2 | CCLK_0, V11 |
Table 7: Quad SPI interface signals and connections
On-module I²C interface is routed from PL bank 65 I/O pins (PLL_SCL and PLL_SDA) to the I²C interface of Si5338 PLL quad clock generator U2, also two further pins of bank 65 can be used as external I²C interface of the modue:
I²C Interface | Schematic net names | Connected to | I²C Address | Notes |
---|---|---|---|---|
PL bank 65 I/O | 'PLL_SCL', pin AB20 'PLL_SDA' pin AB19 | Si5338 U2, pin 12 Si5338 U2, pin 19 | 0x70 | default address |
PL bank 65 I/O | 'B65_SCL', pin Y19 'B65_SDA', pin AA19 | B2B JM1, pin 95 B2B JM1, pin 93 | - |
Table 8: I2C slave device addresses
<!-- Components on the Module, like Flash, PLL, PHY... --> |
The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA module are by-passed, forwarded and controlled by the System Controller CPLD.
Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.
For detailed information, refer to the reference page of the SC CPLD firmware of this module.
<!-- Put in link to the Wiki reference page of the firmware of the SC CPLD. --> |
By default TE0841 module has two K4A8G165WB-BIRC DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-module RAM. Different memory sizes are available optionally.
On-module QSPI flash memory (U6) on the TE0841-01 is provided by Micron Serial NOR Flash Memory N25Q512A11G1240E with 512-Mbit (64 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant. |
There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U2) to generate various reference clocks for the module.
Si5338A Pin | Signal Name / Description | Connected to | Direction | Note |
---|---|---|---|---|
IN1 | - | not connected | Input | not used |
IN2 | - | GND | Input | not used |
IN3 | Reference input clock | U3, pin 3 | Input | 25.000000 MHz oscillator, Si8208AI |
IN4 | - | GND | Input | I2C slave device address LSB. |
IN5 | - | not connected | Input | not used |
IN6 | - | GND | Input | not used |
CLK0A | CLK1_P | U1, R23 | Output | FPGA bank 45, default 100MHz* |
CLK0B | CLK1_N | U1, P23 | ||
CLK1A | MGT_CLK1_N | U1, V5 | Output | FPGA MGT bank 225 reference clock, default 125MHz* |
CLK1B | MGT_CLK1_P | U1, V6 | ||
CLK2A | MGT_CLK3_N | U1, AB5 | Output | FPGA MGT bank 224 reference clock, default 156,25MHz* |
CLK2B | MGT_CLK3_P | U1, AB6 | ||
CLK3A | CLK0_P | U1, pin T24 | Output | FPGA bank 45, default 156,25MHz* |
CLK3B | CLK0_N | U1, pin T25 |
Table 9: Programmable quad PLL clock generator inputs and outputs, *PCB REV01 is not programmed
The FPGA module has following reference clocking signals provided by external baseboard sources and on-board oscillators:
Clock Source | Frequency | Signal Name | Clock Destination | Notes |
---|---|---|---|---|
U3, SiT8208AI | 25.000000 MHz | CLK | Si5338A PLL U2, pin 3 (IN3) | - |
U11, DSC1123DL5 | 200.0000 MHz | CLK200M_P | FPGA bank 45, pin R25 | Enable by FPGA bank 65, pin AF24 Signal: 'ENOSC' |
CLK200M_N | FPGA bank 45, pin R26 |
Table 10: Reference clock signals
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D1 | Green | System Controller CPLD, bank 3 | Exact function is defined by SC CPLD firmware. |
Table 11: On-board LEDs
<!-- If power sequencing and distribution is not so much, you can join both sub sections together --> |
The maximum power consumption of a module mainly depends on the design running on the FPGA.
Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Power Input | Typical Current |
---|---|
VIN | TBD* |
3.3VIN | TBD* |
Table 12: Typical power consumption
* TBD - To Be Determined soon with reference design setup.
Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.
For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any FPGA's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
See also Xilinx datasheet DS892 for additional information. User should also check related base board documentation when intending base board design for TE0841 module.
The TE0841 SoM meets the recommended criteria to power up the Xilinx FPGA properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the FPGA chip and powering up the on-board voltages.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
Power Rail Name | B2B JM1 Pins | B2B JM2 Pins | Input/Output | Notes |
---|---|---|---|---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage |
3.3VIN | 13, 15 | - | Input | Supply voltage |
B64_VCO | 9, 11 | - | Input | HR (High Range) bank voltage |
B66_VCO | - | 1, 3 | Input | HP (High Performance) bank voltage |
B67_VCO | - | 7, 9 | Input | HP (High Performance) bank voltage |
B68_VCO | - | 5 | Input | HP (High Performance) bank voltage |
VBAT_IN | 79 | - | Input | RTC battery supply voltage |
3.3V | - | 10, 12, 91 | Output | Module on-board 3.3V voltage level |
Table 13: Module power rails
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered). |
Bank | Schematic Name | Voltage | Voltage Range |
---|---|---|---|
0 (config) | PL_1.8V | 1.8V | - |
44 HP | DDR_1V2 | 1.2V | HP: 1.2V to 1.8V |
45 HP | PL_1.8V | 1.8V | HP: 1.2V to 1.8V |
46 HP | DDR_1V2 | 1.2V | HP: 1.2V to 1.8V |
64 HR | B64_VCO | user | HR: 1.2V to 3.3V |
65 HR | 3.3V | 3.3V | HR: 1.2V to 3.3V |
66 HP | B66_VCO | user | HP: 1.2V to 1.8V |
67 HP | B67_VCO | user | HP: 1.2V to 1.8V |
68 HP | B68_VCO | user | HP: 1.2V to 1.8V |
Table 14: Module PL I/O bank voltages
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See also the current available variants on the Trenz Electronic shop page
Trenz shop TEF1001 overview page | |
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English page | German page |
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | -0.3 | 6.0 | V | EN63A0QI, TPS74401RGW datasheets |
3.3VIN supply voltage | -0.1 | 3.4 | V | Xilinx datasheet DS892 (HR Bank VCCO) |
VBAT_IN | -0.3 | 6.0 | V | TPS780xx datasheet |
Supply voltage for HR I/O banks (VCCO) | -0.500 | 3.400 | V | Xilinx datasheet DS892 |
Supply voltage for HP I/O banks (VCCO) | -0.500 | 2.000 | V | Xilinx datasheet DS892 |
I/O input voltage for HR I/O banks | -0.400 | VCCO + 0.550 | V | Xilinx datasheet DS892 |
I/O input voltage for HP I/O banks | -0.550 | VCCO + 0.550 | V | Xilinx datasheet DS892 |
I/O input voltage for SC CPLD U18 | -0.5 | 3.75 | V | LCMXO2-256HC datasheet |
GTH and GTY transceiver reference clocks absolute input voltage (MGT_CLK0, MGT_CLK2) | -0.500 | 1.320 | V | Xilinx datasheet DS892 |
GTH and GTY transceiver receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage | -0.500 | 1.260 | V | Xilinx datasheet DS892 |
Storage temperature | -40 | +100 | °C | SML-P11 LED datasheet |
Table 16: Module absolute maximum ratings
Assembly variants for higher storage temperature range are available on request. |
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | 3.3 | 5.5 | V | TPS82085SIL, TPS74401RGW datasheet |
3.3VIN supply voltage | 3.3 | 3.4 | V | Xilinx datasheet DS892 (HR Bank VCCO) |
VBAT_IN | 2.2 | 5.5 | V | TPS780xx datasheet |
Supply voltage for HR I/O banks (VCCO) | 1.140 | 3.400 | V | Xilinx datasheet DS892 |
Supply voltage for HP I/O banks (VCCO) | 0.950 | 1.890 | V | Xilinx datasheet DS892 |
I/O input voltage for HR I/O banks | –0.200 | VCCO + 0.20 | V | Xilinx datasheet DS892 |
I/O input voltage for HP I/O banks | –0.200 | VCCO + 0.20 | V | Xilinx datasheet DS892 |
I/O input voltage for SC CPLD U18 | -0.3 | 3.6 | V | LCMXO2-256HC datasheet |
Industrial Module Operating Temperature Range | -40 | 85 | °C | Xilinx datasheet DS892 |
Commercial Module Operating Temperature Range | 0 | 85 | °C | Xilinx DS892, Silicon Labs Si5338 datasheet |
Table 17: Module recommended operating conditions
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Please check also Xilinx datasheet DS892 for complete list of absolute maximum and recommended operating ratings. |
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.65 mm.
Highest part on PCB: approximately 3 mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
2018-05-11 | 02 | current available board revision | PCN-20180511 | TE0841-02 |
2015-12-09 | 01 | First production release | - | TE0841-01 |
Table 18: Module hardware revision history
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Date | Revision | Contributors | Description |
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Table 18: Document change history