Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
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Notes :
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Zynq PS Design with Linux Example and Virtual Input/Output (VIO) for Control and Monitoring with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0724-info
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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Design supports following carriers:
*used as reference |
Additional HW Requirements:
*used as reference |
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For general structure and of the reference design, see Project Delivery - AMD devices
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Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide): |
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also Vivado Board Part Flow |
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
TE::hw_build_design -export_prebuilt |
Using Vivado GUI is the same, except file export to prebuilt folder. |
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
This step depends on Xilinx Device/Hardware for Zynq-7000 series
for ZynqMP
for Microblaze
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TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Note:
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Select Create and open delivery binary folder
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0724 (optional) |
Not used on this Example.
Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
Note: See TRM of the Carrier, which is used. |
Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. |
Power On PCB
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR for Microblaze 1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR for native FPGA ... |
Select COM Port
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
# password disabled petalinux login: root Password: root |
Note: Wait until Linux boot finished |
You can use Linux shell now.
I2C i2cdetect -l (Shows a list of the available I2C buses) i2cdetect -y -r 0 (check I2C 0 Bus) RTC dmesg | grep rtc (RTC check) ETH0 udhcpc (ETH0 check) GPIO gpiodetect (list all gpiochips present on the system) gpioget `gpiofind "MIO51_J9-6"` (read value of specified GPIO) gpioset `gpiofind "MIO9_D8"`=1 (set value of specified GPIO) |
Option Features
Webserver to get access to Zynq
insert IP on web browser to start web interface
init.sh scripts
add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
Note:
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Note:
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# # Common BITGEN related settings for TE0724 SoM # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] |
# can set_property PACKAGE_PIN T11 [get_ports CAN_0_tx] set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_tx] set_property PACKAGE_PIN T10 [get_ports CAN_0_rx] set_property IOSTANDARD LVCMOS33 [get_ports CAN_0_rx] set_property PACKAGE_PIN U13 [get_ports {CAN_STBY[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {CAN_STBY[0]}] # led set_property PACKAGE_PIN U12 [get_ports {LED_RG[0]}] set_property PACKAGE_PIN W13 [get_ports {LED_RG[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {LED_RG[*]}] # CLK set_property PACKAGE_PIN U14 [get_ports {PHY_CLK125M[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {PHY_CLK125M[0]}] # PWR GPIO set_property PACKAGE_PIN T12 [get_ports {PWR_GPIO01[0]}] set_property PACKAGE_PIN U15 [get_ports {PWR_GPIO01[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {PWR_GPIO01[*]}] # TEB0724 Button set_property PACKAGE_PIN Y19 [get_ports {TEB0724_BUTTON_S24[0]}] set_property PACKAGE_PIN Y18 [get_ports {TEB0724_BUTTON_S24[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {TEB0724_BUTTON_S24[*]}] # TEB0724 LED set_property PACKAGE_PIN P18 [get_ports {TEB0724_ULED[0]}] set_property PACKAGE_PIN N17 [get_ports {TEB0724_ULED[1]}] set_property PACKAGE_PIN R17 [get_ports {TEB0724_ULED[2]}] set_property PACKAGE_PIN R16 [get_ports {TEB0724_ULED[3]}] set_property PACKAGE_PIN Y14 [get_ports {TEB0724_ULED[4]}] set_property PACKAGE_PIN W14 [get_ports {TEB0724_ULED[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {TEB0724_ULED[*]}] |
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For Vitis project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2022.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2021.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2022.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2022.2 FSBL General:
---------------------------------------------------------- ZynqMP Example: zynqmp_fsblTE modified 2022.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2022.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
TE modified 2022.2 FSBL
General:
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
Module Specific:
Hello TE0724 is a Xilinx Hello World example as endless loop instead of one console output.
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Note:
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For PetaLinux installation and project creation, follow instructions from:
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
Start with petalinux-config -c u-boot
Changes:
Change platform-top.h:
#include <configs/zynq-common.h> #no changes |
/include/ "system-conf.dtsi" /*-------------------------- default ---------------------*/ /*--------------------------- GPIO -----------------------*/ &gpio0 { gpio-line-names = "MIO0_PWR" , "" , "" , "" , "" , "" , "" , "MIO7" , "" , "MIO9_D8" , "MIO10_J7-5" , "MIO11_J7-6" , "MIO12_J7-7" , "MIO13_J7-8" , "MIO14_J7-9" , "MIO15_J7-10" , "" , "" , "" , "" , "" , "" , "" , "" , "" , "" , "" , "" , "" , "" , "MIO30_nC" , "MIO31_nC" , "MIO32_nC" , "MIO33_nC" , "MIO34_nC" , "MIO35_nC" , "MIO36_nC" , "MIO37_nC" , "MIO38_TCA-OE" , "" , "" , "" , "" , "" , "" , "" , "MIO46_J9-4" , "" , "" , "" , "MIO50_J9-5" , "MIO51_J9-6" , "" , "" ; }; /*--------------------------- QSPI -----------------------*/ &qspi { is-dual = <0>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; status = "okay"; spi-rx-bus-width = <4>; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; spi-rx-bus-width = <4>; }; }; /*-------------------------- ETH PHY ---------------------*/ &gem0 { /delete-property/ local-mac-address; phy-handle = <&phy0>; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; phy0: phy@0 { device_type = "ethernet-phy"; reg = <1>; }; }; /*---------------------------- I2C -----------------------*/ &i2c1 { //pmic pmic0: da9062@58 { compatible = "dlg,da9062"; reg = <0x58>; interrupt-parent = <&gpio0>; interrupts = <0 8>; interrupt-controller; rtc { compatible = "dlg,da9062-rtc"; }; }; //MAC EEPROM eeprom: eeprom@53 { compatible = "microchip,24aa025", "atmel,24c02"; reg = <0x53>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; //user EEPROM eeprom50: eeprom@50 { compatible = "microchip,24aa128", "atmel,24c128"; reg = <0x50>; }; }; |
Start with petalinux-config -c kernel
Changes:
CONFIG_REGMAP_IRQ=y
# CONFIG_DA9062_THERMAL is not set
# CONFIG_DA9062_WATCHDOG is not set
CONFIG_MFD_DA9062=y
# CONFIG_REGULATOR_DA9062 is not set
CONFIG_RTC_DRV_DA9063=y
Start with petalinux-config -c rootfs
Changes:
Add in <project folder>\os\petalinux\project-spec\meta-user\conf\user-rootfsconfig
CONFIG_libgpiod-tools |
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
Script App to load init.sh from SD Card if available.
Webserver application suitable for Zynq access. Need busybox-httpd
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No additional software is needed.
To get content of older revision go to "Change History" of this page and select older document revision number.
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