Template Revision 2.7 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
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Table of contents |
Overview
ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
Wiki Resources page: http://trenz.org/te0820-info
Key Features
Notes : - Add basic key futures, which can be tested with the design
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- Vitis/Vivado 2019.2
- PetaLinux
- SD
- ETH
- USB
- I2C
- RTC
- FMeter
- MAC from EEPROM
- User LED (PCB REV03 only)
- Modified FSBL for SI5338 programming
- Special FSBL for QSPI programming
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Revision History
Notes : - add every update file on the download
- add design changes on description
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Date | Vivado | Project Built | Authors | Description |
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2020-01-22 | 2019.2 | TE0820-test_board_noprebuilt-vivado_2019.2-build_3_20200122154341.zip TE0820-test_board-vivado_2019.2-build_3_20200122154318.zip | John Hartfiel | - script update for linux user
| 2020-01-14 | 2019.2 | TE0820-test_board-vivado_2019.2-build_3_20200114081551.zip TE0820-test_board_noprebuilt-vivado_2019.2-build_3_20200114081612.zip | John Hartfiel | - add fsbl_flash binary
- Vitis script updates (include linux domain and prebuilt linux files for vitis)
- prebuilt binary export on selection guide
| 2019-12-19 | 2019.2 | TE0820-test_board-vivado_2019.2-build_1_20191219075647.zip TE0820-test_board_noprebuilt-vivado_2019.2-build_1_20191219080228.zip | John Hartfiel | - 2019.2 update
- Vitis support
| 2019-10-29 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_09_20191029071045.zip TE0820-test_board-vivado_2018.3-build_09_20191029071028.zip | John Hartfiel | | 2019-08-09 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_07_20190809084040.zip TE0820-test_board-vivado_2018.3-build_07_20190809083901.zip | John Hartfiel | - bugfix fsbl (removed second PSU init)
| 2019-06-19 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_06_20190619073300.zip TE0820-test_board-vivado_2018.3-build_06_20190619073243.zip | John Hartfiel | - new assembly variants
- USB2 only (change PS IP and device tree)
- FSBL changes
| 2019-04-01 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_03_20190401130135.zip TE0820-test_board-vivado_2018.3-build_03_20190401130123.zip | John Hartfiel | - renamed ...D variants to ...A
| 2019-02-21 | 2018.3 | TE0820-test_board_noprebuilt-vivado_2018.3-build_01_20190221103025.zip TE0820-test_board-vivado_2018.3-build_01_20190221102913.zip | John Hartfiel | - TE Script update
- rework of the FSBLs
- SI5338 CLKBuilder Pro Project
- some additional Linux features
- MAC from EEPROM
- new assembly variants
- remove special compiler flags, which was needed in 2018.2
| 2018-10-31 | 2018.2 | TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20181031164506.zip TE0820-test_board-vivado_2018.2-build_03_20181031164452.zip | John Hartfiel | - new assembly variants
- update optional petalinux startup init script
| 2018-09-12 | 2018.2 | TE0820-test_board_noprebuilt-vivado_2018.2-build_03_20180912094615.zip TE0820-test_board-vivado_2018.2-build_03_20180912094558.zip | John Hartfiel | - correction:
- TE0820-03-4EV-1EA has 2GB DDR, now 2GB instead of 1GB is initialised
- small changes on DDR setup of TE0820-02-2EG-1EE
| 2018-08-15 | 2018.2 | TE0820-test_board-vivado_2018.2-build_01_20180706212937.zip TE0820-test_board_noprebuilt-vivado_2018.2-build_01_20180706212952.zip | John Hartfiel | - different design for REV03
- small petalinux changes
- IO renaming
- additional notes for FSBL generated with Win SDK
- changed *.bif
| 2018-06-19 | 2017.4 | TE0820-test_board-vivado_2017.4-build_10_20180619160713.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180619160728.zip | John Hartfiel | - bugfix board part files BANK1 MIO voltages
- Add "dummy" PS USB3 parameter so solve problems with some USB2 devices
| 2018-05-24 | 2017.4 | TE0820-test_board-vivado_2017.4-build_10_20180524151356.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_10_20180524151342.zip | John Hartfiel | - solved Linux Flash issue
- new assembly variant
| 2018-04-25 | 2017.4 | TE0820-test_board-vivado_2017.4-build_07_20180425134435.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_07_20180425134459.zip | John Hartfiel | | 2018-02-06 | 2017.4 | TE0820-test_board-vivado_2017.4-build_06_20180206203359.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_06_20180206203414.zip | John Hartfiel | | 2018-02-01 | 2017.4 | TE0820-test_board-vivado_2017.4-build_05_20180201084319.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180201094724.zip | John Hartfiel | | 2018-01-24 | 2017.4 | TE0820-test_board-vivado_2017.4-build_05_20180124085247.zip TE0820-test_board_noprebuilt-vivado_2017.4-build_05_20180124085303.zip | John Hartfiel | - rework board part files
- solved USB, QSPI and PHy issue
| 2017-11-21 | 2017.2 | TE0820-test_board-vivado_2017.2-build_05_20171121160552.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171121160606.zip | John Hartfiel | - solved SD SDX Cards Problem
- Separate csv name for all assembly variants
| 2017-11-20 | 2017.2 | TE0820-test_board-vivado_2017.2-build_05_20171120162931.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171120162851.zip | John Hartfiel | | 2017-10-19 | 2017.2 | TE0820-test_board-vivado_2017.2-build_05_20171019104824.zip TE0820-test_board_noprebuilt-vivado_2017.2-build_05_20171019104837.zip | John Hartfiel | |
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Release Notes and Know Issues
Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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Issues | Description | Workaround | To be fixed version |
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Flash access on Linux | Device tree is not correct on Linux | add compatibility to "compatible “jedec,spi-nor”" | Solved with 20180524 update | USB UART Terminal is blocked / SDK Debugging is blocked | This happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager. | Do not use HW Manager connection, or if debugging is nessecary: - Boot linux with usb terminal
- From the terminal: root root mount ifconfig eth0
- Open two new SSH terminals via ethernet: root root , run user application ...
- Exit and close the usb terminal
| Solved with 20180206 update |
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Requirements
Software
Notes : - list of software which was used to generate the design
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Software | Version | Note |
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Vitis | 2019.2 | needed Vivado is included into Vitis installation | PetaLinux | 2019.2 | needed | SI ClockBuilder Pro | --- | optional |
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Hardware
Notes : - list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0820-ES1 | es1 | REV01 | 1GB | 64MB | 4GB | NA | Not longer supported by vivado | TE0820-02-02EG-1E | 2eg_1e_1gb | REV02 | 1GB | 64MB | 4GB | NA | NA | TE0820-02-02EG-1E3 | 2eg_1e_1gb | REV02 | 1GB | 64MB | 4GB | 2.5 mm connectors | NA | TE0820-02-02CG-1E | 2cg_1e_1gb | REV02 | 1GB | 64MB | 4GB | NA | NA | TE0820-02-03EG-1E | 3eg_1e_1gb | REV02 | 1GB | 64MB | 4GB | NA | NA | TE0820-02-03EG-1E3 | 3eg_1e_1gb | REV02 | 1GB | 64MB | 4GB | 2.5 mm connectors | NA | TE0820-02-03CG-1E | 3cg_1e_1gb | REV02 | 1GB | 64MB | 4GB | NA | NA | TE0820-02-02EG-1EA | 2eg_1e_1gb | REV02 | 1GB | 128MB | 4GB | NA | NA | TE0820-02-02EG-1EL | 2eg_1e_1gb | REV02 | 1GB | 128MB | 4GB | 2.5 mm connectors | NA | TE0820-02-02CG-1EA | 2cg_1e_1gb | REV02 | 1GB | 128MB | 4GB | NA | NA | TE0820-02-03EG-1EA | 3eg_1e_1gb | REV02 | 1GB | 128MB | 4GB | NA | NA | TE0820-02-03EG-1EL | 3eg_1e_1gb | REV02 | 1GB | 128MB | 4GB | 2.5 mm connectors | NA | TE0820-02-03CG-1EA | 3cg_1e_1gb | REV02 | 1GB | 128MB | 4GB | NA | NA | TE0820-02-04CG-1EA | 4cg_1e_1gb | REV02 | 1GB | 128MB | 4GB | NA | NA | TE0820-03-04EV-1EA | 4ev_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-02CG-1EA | 2cg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-02EG-1EA | 2eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-02EG-1EL | 2eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | 2.5 mm connectors | NA | TE0820-03-03CG-1EA | 3cg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-04CG-1EA | 4cg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-03EG-1EA | 3eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-03EG-1EL | 3eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | 2.5 mm connectors | NA | TE0820-03-2AI21FA | 2cg_1i_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03-2BE21FL | 2eg_1e_2gb | REV03 | 2GB | 128MB | 8GB | 2.5 mm connectors | NA | TE0820-03-3AI210A | 3cg_1i_2gb | REV03 | 2GB | 128MB | 0GB | NA | NA | TE0820-03-3BE21FA | 3eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | NA | NA | TE0820-03-3BE21FL | 3eg_1e_2gb | REV03 | 2GB | 128MB | 4GB | 2.5 mm connectors | NA | TE0820-03-02CG-1ED | 2cg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03-2AE21FA | 2cg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03-2BE21FA | 2eg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03-3AE21FA | 3cg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03-3AI21FA | 3cg_1i_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03-4AE21FA | 4cg_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03-4DE21FA | 4ev_1e_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA | TE0820-03-4DI21FA | 4ev_1i_2gb | REV03 | 2GB | 128MB | 8GB | NA | NA |
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Design supports following carriers:
Carrier Model | Notes |
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TE0701 | | TE0703 | - Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 cm carriers
- Used as reference carrier.
| TE0705 | | TE0706 | | TEBA0841 | - Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
- No SD Slot available, pins goes to Pin Header
- For TEBA0841 REV01, please contact TE support
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Additional HW Requirements:
Additional Hardware | Notes |
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USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct typ | XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI | Cooler | It's recommended to use cooler on ZynqMP device |
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Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | Vitis | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation | PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
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Additional Sources
Type | Location | Notes |
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SI5338 | <design name>/misc/Si5338 | SI5338 Project with current PLL Configuration | init.sh | <design name>/sd/ | Additional Initialization Script for Linux |
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Prebuilt
Notes : - prebuilt files
- Template Table:
File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification forVitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see also TE Board Part Files
- Create XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Create Linux (bl31.elf, uboot.elf and image.ub) with exported XSA
- XSA is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from "/os/petalinux"
- Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\<DDR size>" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\<DDR size"
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Depending of PC performance this can take several minutes. Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" and open Vitis - (alternative) Start Vitis with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Launch
Note: - Programming and Startup procedure
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Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0820" possible - Copy image.ub on SD-Card
- use files from (<project foler>/_binaries_<Artikel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Insert SD-Card
SD
Use this description for CPLD Firmware with SD Boot selectable.
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card or QSPI as Boot Mode (Depends on used programming variant)
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD/QSPI Flash into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB2.0 device
- Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
Vivado HW Manager
SI5338_CLK0 Counter:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz
SI5338 CLK is configured to 200MHz by default.
PCB REV03 Design:
PCB REV01, REV02 Design:
System Design - Vivado
Block Design
PCB REV03
PCB REV01 REV02
PS Interfaces
Activated interfaces:
Type | Note |
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DDR |
|
QSPI | MIO |
SD0 | MIO |
SD1 | MIO |
I2C0 | MIO |
UART0 | MIO |
GPIO0 | MIO |
SWDT0..1 |
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TTC0..3 |
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GEM3 | MIO |
USB0 | MIO, USB2 only |
Constrains
Basic module constrains
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design |
Design specific constrain
set_property PACKAGE_PIN K9 [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property DIFF_TERM TRUE [get_ports {SI5338_CLK0_D_clk_p[0]}]
set_property PACKAGE_PIN H1 [get_ports {x0[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}]
set_property PACKAGE_PIN J1 [get_ports {x1[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}] |
Software Design - Vitis
For SDK project creation, follow instructions from:
Vitis
Application
---------------------------------------------------------- FPGA Example todo.. ---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2018.3 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2018.3 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2018.3 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2018.3 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
zynqmp_fsbl
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0820
Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
- CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
U-Boot
Start with petalinux-config -c u-boot
Changes:
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
CONFIG_I2C_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_I2C_EEPROM_BUS=0
CONFIG_SYS_EEPROM_SIZE=256
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
Change platform-top.h:
Device Tree
/include/ "system-conf.dtsi"
/ {
chosen {
xlnx,eeprom = &eeprom;
};
};
/* SDIO */
&sdhci1 {
disable-wp;
no-1-8-v;
};
/* ETH PHY */
&gem3 {
status = "okay";
ethernet_phy0: ethernet-phy@0 {
compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <1>;
};
};
/* USB 2.0 */
/* USB */
&dwc3_0 {
status = "okay";
dr_mode = "host";
maximum-speed = "high-speed";
/delete-property/phy-names;
/delete-property/phys;
/delete-property/snps,usb3_lpm_capable;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
};
&usb0 {
status = "okay";
/delete-property/ clocks;
/delete-property/ clock-names;
clocks = <0x3 0x20>;
clock-names = "bus_clk";
};
/* QSPI PHY */
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&i2c0 {
eeprom: eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
};
};
|
Kernel
Start with petalinux-config -c kernel
Changes:
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_i2c-tools=y
- CONFIG_busybox-httpd=y (for web server app)
- CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
Additional Software
Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
|
SI5338
File location <design name>/misc/Si5338/Si5338-*.slabtimeproj
General documentation how you work with these project will be available on Si5338
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
Date | Document Revision | Authors | Description |
---|
| | | - Script update for linux user
| 2020-01-14 | v.58 | John Hartfiel | - Script update, new features
- docu update
- add missing binary files
| 2019-12-19 | v.57 | John Hartfiel | | 2019-10-29 | v.56 | John Hartfiel | | 2019-08-09 | v.55 | John Hartfiel | | 2019-06-19 | v.54 | John Hartfiel | - design changes
- new variants
| 2019-04-01 | v.53 | John Hartfiel | - some notes
- renamed ..D variants to ...A
| 2018-09-21 | v.47 | John Hartfiel | - 2018.3 release finished (include design reworks)
| | v.43 | John Hartfiel | - Update Design files for 2GB variants
- rebuilt petalinux for optional init script
| | v.41 | John Hartfiel | - Update Design files for 2GB variants
| | v.40 | John Hartfiel | | | v.38 | John Hartfiel | | | v.34 | John Hartfiel | | | v.29 | John Hartfiel | | 2018-02-06 | v.27 | John Hartfiel | | 2018-01-29 | v.26 | John Hartfiel | | 2018-01-24 | v.25 | John Hartfiel | | 2018-01-10 | v.24 | John Hartfiel | | 2017-12-20 | v.23 | John Hartfiel | - Typo correction
- Update HW Module Table Description
| 2017-11-21 | v.19 | John Hartfiel | | 2017-11-20 | v.18 | John Hartfiel | - Design Update
- Add Variants with 128MB Flash
| 2017-11-13 | v.16 | John Hartfiel | | 2017-11-06 | v.15 | John Hartfiel | | 2017-10-23 | v.13 | John Hartfiel | - Update Key Features section
- Style Update Additional Software section
| 2017-10-19 | v.9 | John Hartfiel | | 2017-09-11 | v.1 | | Initial release |
| All | |
|
|
Legal Notices