Template Revision 2.8 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
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Table of contents |
Overview
Zynq PS Design with Linux Example.
Refer to http://trenz.org/te0726-info for the current online version of this manual and other available documentation.
Key Features
Notes : - Add basic key futures, which can be tested with the design
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- Vitis/Vivado 2019.2
- PetaLinux
- SD
- ETH
- USB
- I2C
- Special FSBL for QSPI programming
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Revision History
Notes : - add every update file on the download
- add design changes on description
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Date | Vivado | Project Built | Authors | Description |
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2020-04-08 | 2019.2 | TE0726-test_board_noprebuilt-vivado_2019.2-build_10_20200408185842.zip TE0726-test_board-vivado_2019.2-build_10_20200408185804.zip | Mohsen Chamanbaz/John Hartfiel | | 2020-03-25 | 2019.2 | TE0726-test_board_noprebuilt-vivado_2019.2-build_8_20200325080535.zip TE0726-test_board-vivado_2019.2-build_8_20200325080528.zip | Mohsen Chamanbaz/John Hartfiel | | 2020-02-14 | 2019.2 | TE0726-test_board_noprebuilt-vivado_2019.2-build_5_20200214091531.zip TE0726-test_board-vivado_2019.2-build_5_20200214091442.zip | Mohsen Chamanbaz | - Update to 19.2
- Vitis support
- prebuilt binary export on selection guide
| 2019-12-12 | 2018.3 | te0726-test_board_noprebuilt-vivado_2018.3-build_10_20191211160322.zip te0726-test_board-vivado_2018.3-build_10_20191211160314.zip | Mohsen Chamanbaz | - FSBL update to18.3
- additional linux apps
| 2018-07-13 | 2018.2 | te0726-test_board_noprebuilt-vivado_2018.2-build_02_20180713155548.zip te0726-test_board-vivado_2018.2-build_02_20180713155535.zip | John Hartfiel | - Changed SDK Notes on FSBL template fro Flash programming
| 2018-07-11 | 2018.2 | te0726-test_board_noprebuilt-vivado_2018.2-build_02_20180711113737.zip te0726-test_board-vivado_2018.2-build_02_20180711113722.zip | John Hartfiel | - change note for REV01
- no design changes
| 2018-02-17 | 2017.4 | te0726-test_board-vivado_2017.4-build_08_20180517084735.zip te0726-test_board_noprebuilt-vivado_2017.4-build_08_20180517084604.zip | John Hartfiel | - correction netboot offset for 128MB variant
| 2018-02-16 | 2017.4 | te0726-test_board-vivado_2017.4-build_06_20180216205357.zip te0726-test_board_noprebuilt-vivado_2017.4-build_06_20180216205410.zip | John Hartfiel | - correction PS REFCLK for 01 variant
| 2018-01-31 | 2017.4 | te0726-test_board-vivado_2017.4-build_05_20180131115412.zip te0726-test_board_noprebuilt-vivado_2017.4-build_05_20180131115451.zip | John Hartfiel | |
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Release Notes and Know Issues
Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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Issues | Description | Workaround | To be fixed version |
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Flash Programming failed with 19.2 | Depending on Flash content Flash programming failed with provided fsbl_flash (Xilinx AR# 70548 )2019.2 version | - Option1:
- In case Flash is empty, use fsbl_flash on programming GUI
- In case Flash is programmed use normal fsbl on programming GUI
- Option2: use in both case fsbl_flash on programming GUI and Vivado LabTools 2018.3
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Requirements
Software
Notes : - list of software which was used to generate the design
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Software | Version | Note |
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Vitis | 2019.2 | needed, Vivado is included into Vitis installation | PetaLinux | 2019.2 | needed |
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Hardware
Notes : - list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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te0726-01 | 01 | REV01 | 64MB | 16MB | NA | NA |
| te0726-03r | r | REV03,REV02 | 128MB | 16MB | NA | NA |
| te0726-03m | m | REV03,REV02 | 512MB | 16MB | NA | NA |
| te0726-03-07s-1c | 7s | REV03,REV02 | 512MB | 16MB | NA | NA |
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Design supports following carriers:
Additional HW Requirements:
Additional Hardware | Notes |
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USB Cable | Connect to USB2 or better USB3 Hub for proper power over USB |
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Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | Vitis | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation | PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
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Additional Sources
Type | Location | Notes |
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init.sh | <design name>/misc/sd/ | Additional Initialization Script for Linux |
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Prebuilt
Notes : - prebuilt files
- Template Table:
File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Create Linux (uboot.elf and image.ub) with exported XSA
- XSA is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Launch
Note: - Programming and Startup procedure
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Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
- Connect JTAG and power module (TE0726 can be powered via JTAG USB or external)
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0726" possible - Copy image.ub on SD-Card
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Important: Do not copy Boot.bin on SD(is not used see SD note), only other files.
- Insert SD-Card
SD
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (uboot)
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Insert SD Card with image.ub
- Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL loads U-boot from QSPI into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 1 Bus type: i2cdetect -y -r 1
- ETH0 works with udhcpc
- USB: insert USB device
- Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
System Design - Vivado
Block Design
PS Interfaces
Type | Note |
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DDR | --- | QSPI | MIO | SD1 | MIO | I2C1 | MIO | UART1 | MIO | GPIO | MIO | TTC0..1 | EMIO | WDT | EMIO | USB0 | MIO, ETH over USB | USB RST | MIO |
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Constrains
Basic module constrains
#
# Common BITGEN related settings for TE0726
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Design specific constrain
Software Design - Vitis
For SDK project creation, follow instructions from:
Vitis
Application
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2019.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2019.2 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2019.2 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
zynq_fsbl
TE modified 2019.2 FSBL
General:
Module Specific:
zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0726
Hello TE0726 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
For 64MB variant only:
- CONFIG_SUBSYSTEM_NETBOOT_OFFSET = 0x2000000
For 128MB variant only:
- CONFIG_SUBSYSTEM_NETBOOT_OFFSET = 0x4000000
U-Boot
Start with petalinux-config -c u-boot
Changes:
Change platform-top.h:
Device Tree
/include/ "system-conf.dtsi"
/ {
};
/* USB PHY */
/{
usb_phy0: usb_phy@0 {
compatible = "ulpi-phy";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&usb0 {
dr_mode = "host";
//dr_mode = "peripheral";
usb-phy = <&usb_phy0>;
};
/* I2C1 */
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
i2cmux0: i2cmux@70 {
compatible = "nxp,pca9544";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c1@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
id_eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
};
};
i2c1@1 { // Display Interface Connector
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
i2c1@2 { // HDMI Interface Connector
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
i2c1@3 { // Camera Interface Connector
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
};
};
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Kernel
Start with petalinux-config -c kernel
Changes:
- CONFIG_XILINX_GMII2RGMII
- CONFIG_USB_USBNET
- CONFIG_USB_NET_SMSC95XX
- CONFIG_USBIP_CORE
Rootfs
Start with petalinux-config -c rootfs
Changes:
- CONFIG_i2c-tools=y
- CONFIG_busybox-httpd=y (for web server app)
- CONFIG_packagegroup-petalinux-utils
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
Additional Software
Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
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No additional software is needed
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Date | Document Revision | Authors | Description |
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| | | - Design update
- Programming issue note
| 2020-03-25 | v.14 | John Hartfiel | | 2020-02-19 | v.13 | John Hartfiel | - 2019.2 release
- docu update
| | | | | 2018-07-13 | v.11 | John Hartfiel | | | v.9 | John Hartfiel | - bugfix design for 128MB variant
| | v.8 | John Hartfiel | | 2018-02-16 | v.6 | John Hartfiel | | 2018-02-09 | v.5 | John Hartfiel | | -- | all | | -- |
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Legal Notices