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Overview

The Trenz Electronic TE0808 is an industrial grade MPSoC SOM integrating an AMD Zynq UltraScale+ MPSoC, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

  • SoC
    • Device: ZU6 / ZU9 / ZU15 1) 2)
    • Engine: CG / EG  1)
    • Speedgrade: -1 / -2  1)
    • Temperature Range: Extended / Industrial 1)
    • Package: FFVC900
  • RAM/Storage
    • 4 GByte DDR4 SDRAM 3)
    • 2 x 64 MByte Serial Flash 4)
    • EEPROM with MAC address
  • On Board
    • Oscillator
  • Interface
    • 4 x B2B Connector (ST5)
      • up to 204 PL IO

        • HP: 156
        • HD: 48
      • up to 65 PS MIO

      • 4 GTR
      • 16 GTH
      • I2C, JTAG, CONFIG
  • Power
    • 3.3 V power supply via B2B Connector needed 5).
  • Dimension
    • 76 mm x 52 mm
  • Notes
    1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
    2) without PCIe Core on PL, see XMP104
    3) Up to 8 GByte are possible with a maximum bandwidth of 2400 MBit/s.
    4) Please, take care of the possible assembly options.
    5) Dependent on the assembly option a higher input voltage may be possible

Block Diagram

TE0808 block diagram

Main Components

TE0808 main components
  1. SoC, U1
  2. DDR4, U2, U3, U9, U12
  3. Quad SPI Flash, U7, U17
  4. Connector, J1, J2, J3, J4
  5. EEPROM, U4
  6. Clock Generator, U5
  7. Oscillator, U25, U32
  8. Done LED D1

Initial Delivery State

Storage device name

Content

Notes

DDR4 SDRAMnot programmed
Quad SPI Flashnot programmed
EEPROMnot programmed besides factory programmed MAC address
Programmable Clock Generatornot programmed
Initial delivery state of programmable devices on the module

Signals, Interfaces and Pins

Connectors

Connector TypeDesignatorInterfaceIO CNTNotes
B2BJM1MGT PL12 x MGT (RX/TX)
B2BJM1HP52 SE / 24 DIFF
B2BJM2MGT PS2 x MGT CLK
B2BJM2CLK4 x DIFF CLKPLL
B2BJM2MGT PL4 x MGT (RX/TX)
B2BJM2MGT PS4 x MGT (RX/TX)
B2BJM2CFG1)1 x JTAG
B2BJM2CFG1)4 x MODE
B2BJM2CFG1)1 x I2CPLL, EEPROM
B2BJM2CFG1)34 CTRL/Status
B2BJM3HD48 SE / 24 DIFF
B2BJM3MGT PL3 x MGT CLK
B2BJM3CLKDIFF CLKPLL
B2BJM3MIO65 PS GPIO
B2BJM4HP104 SE / 48 DIFF

1) see Configuration and System Control Signals

Board Connectors


Test Points

Test PointSignalNotes
TP1PLL_SCLpulled-up to PS_1V8
TP2PLL_SDApulled-up to PS_1V8
TP3LP_DCDC
TP4DCDCIN
TP5GND
TP6TCK
TP7PL_DCIN
TP8GND
TP9GT_DCDC
TP10GND
TP11TDI
TP12TDO
TP13TMS
TP14PS_1V8
TP15No Net NameREF3312AIDCKT (U33) ouput voltage
TP16FP_0V85
TP17DDR_2V5
TP18DDR_PLL
TP19PL_VCCINT
TP20AUX_R
TP21AVTT_R
TP22AUX_L
TP24AVCC_R
TP26AVTT_L
TP28AVCC_L
TP30PS_PLL
TP31PS_AVTT
TP32LP_0V85
TP33PS_AUX
TP34PS_AVCC
TP36POR_Bpulled-up to PS_1V8
Test Points Information

On-board Peripherals

Chip/InterfaceDesignatorConnected ToNotes

DDR4 SDRAM

U2, U3, U9, U12SoC - PS

Quad SPI Flash

U7, U17SoC - PSBooting.

EEPROM

U4B2B - J2

Clock Generator

U5B2B - J2
SoC, - MGT

Oscillator

U25Clock Generator25 MHz

Oscillator

U32SoC - PS33.333333 MHz
On board peripherals

Configuration and System Control Signals

Connector+Pin

Signal Name

Direction1)Description
JM2-77EN_PLL_PWRINEnable PLL power supply.
JM2-79EN_GT_LINEnable left GTH transceiver power-up.
JM2-80PG_PLL_1V8OUTSI_PLL_1V8 power rail powered-up.
JM2-81PLL_FINCINPLL Frequency incrementation.
JM2-82PG_PSGTOUTGTR transceivers powered-up.
JM2-83MRINManual reset.
JM2-84EN_PSGTINEnable GTR transceiver power-up.
JM2-85PLL_LOLnOUTLoss of lock status.
JM2-86ERR_STATUSOUTPS error status 2).
JM2-87PLL_SEL1INPLL clock selection.
JM2-88ERR_OUTOUTPS error indication 2).
JM2-89PLL_RSTINPLL reset.
JM2-90PLL_SCLINI2C clock. Pulled up to PS_1V8.
JM2-91PG_GT_ROUTRight GTH Transceivers powered-up.
JM2-92PLL_SDAIN/OUTI2C data. Pulled up to PS_1V8.
JM2-93PLL_SEL0INPLL clock selection.
JM2-94PLL_FDECINPLL Frequency decrementation.
JM2-95EN_GT_RINEnable right GTH transceiver power-up.
JM2-96SRST_BINSystem reset 2). Pulled-up to PS_1V8.
JM2-97PG_GT_LOUTLeft GTH Transceivers powered-up.
JM2-98INIT_BIN/OUTInitialization completion indicator after POR 2). Pulled-up to PS_1V8.
JM2-100PROG_BIN/OUTPower-on reset 2). Pulled-up to PS_1V8.
JM2-101EN_PLINEnable programable logic power-up.
JM2-102EN_FPDINEnable full-power domain power-up.
JM2-103 / JM2-105 / JM2-107 / JM2-109MODE3..0INBoot mode selection 2):
  • JTAG
  • QUAD-SPI (32 Bit)
  • SD1 (2.0)
  • eMMC (1.8 V)
  • SD1 LS (3.0)

Supported Modes depends also on used Carrier.

JM2-104PG_PLOUTProgrammable logic powered-up. Pulled-up to PL_DCIN.
JM2-106LP_GOODOUTLow-power domain powered-up. Pulled up to LP_DCDC.
JM2-108EN_LPDINEnable low-power domain power-up.
JM2-110PG_FPDOUTFull-power domain powered-up. Pulled-up to DCDCIN.
JM2-112EN_DDRINEnable DDR power-up.
JM2-114PG_DDROUTDDR power supply powered-up. Pulled-up to DCDCIN.
JM2-116DONEOUTPS done signal 2). Pulled-up to PS_1V8.
JM2-119 / JM2-121DX_P / DX_N-SoC temperatur sensing diode pins 2).
JM2-120 / JM2-122 /
JM2-124 / JM2-126
TCK / TDI / TDO / TMSSignal-dependent

JTAG configuration and debugging interface.

JTAG reference voltage: PS_1V8

JM2-125PSBATTINPS RTC Battery supply voltage 2) 3).
JM2-127PUDC_BINConfiguration pull-ups setting 2). Pulled-up to PL_1V8.

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

2) See UG1085 for additional information.

3) See Recommended Operating Conditions.

Controller signal.

Power and Power-On Sequence


Power Rails

Power Rail Name/ Schematic NameConnector + PinDirection1)Notes
VCCO_66JM1-90 / JM1-120IN
VREF_66JM1-108IN

PL_1V8

JM1-91 / JM1-121OUT
PL_DCINJM1-151 / JM1-153 / JM1-155 / JM1-157 / JM1-159IN
LP_DCDCJM2-138 / JM2-140 / JM2-142 / JM2-144IN
DCDCINJM2-153 / JM2-154 / JM2-155 / JM2-156 / JM2-157 / JM2-158 / JM2-159 / JM2-160IN
PS_1V8JM2-99 / JM3-147 / JM3-148OUT
PS_BATTJM2-125IN
DDR_1V2JM2-135OUT
VCCO_48JM3-15 / JM3-16IN
VCCO_47JM3-43 / JM3-44IN
PLL_3V3JM3-152IN
SI_PLL_1V8JM3-151OUT
GT_DCDCJM3-157 / JM3-158 / JM3-159 / JM3-160IN
VCCO_64JM4-58 / JM4-106IN
VREF_64JM4-88IN
VCCO_65JM4-69 / JM4-105IN
VREF_65JM4-15IN

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Module power rails.

Recommended Power up Sequencing

The power up sequencing highly depends on the use case. In general, it should be possible to enable/disable the processing system (PS) / programmable logic (PL) independently. Furthermore, within the processing logic it should be possible to enable/disable only low-power domain and/or low-power and full-power domain. Additionally, usage of GTR for PS side and GTH for PL side should be possible. GTH transceivers on left and right side are usable independently. Because of this flexibility the needed parts of the following table needs to be selected individually. For detailed information take a look into schematics. Attention: PL usage is not completely independent of PS side. For PL usage it is necessary to enable PS low-power domain.

SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes
0---Configuration signal setup.See Configuration and System Control Signals.
1 1)PSBATT1.2 V ... 1.5 V-Battery connection.Battery Power Domain usage. When not used, tie to GND.
2Processing System (PS):

Procedure for PS starting.
2.1Low-power domain:Bring-up for low-power domain PS.
2.1.1LP_DCDC3.3 V (± 5 %) 2)-Low-power domain power supply.Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
2.1.2EN_LPD--Low-power domain power enable.
2.1.3LP_GOOD-PU 3), LP_DCDCLow-power domain power good status.Module power-on sequencing for low-power domain finished.
2.2Full-power domain:Bring-up for full-power domain PS.Full-power PS domain needs powered low-power PS domain.
2.2.1DCDCIN3.3 V (± 5 %) 2)
Full-power domain and GTR transceiver power supply.Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
2.2.2EN_FPDDCDCIN-Full-power domain power enable.
2.2.3PG_FPD-PU 3), DCDCINFull-power domain power good status.Module power-on sequencing for full-power domain finished.
2.2.4EN_DDRDCDCIN-DDR memory power enable.
2.2.5PG_DDR-PU 3), DCDCINDDR memory power good status.Module power-on sequencing for DDR memory finished.

2.3

GTR TransceiverProcedure for GTR transceiver starting.PS transceiver usage needs powered PS (low- and full-power domain).
2.3.1EN_PSGTDCDCIN-GTR transceiver power enable.
2.3.2PG_PSGT--GTR transceiver power good status.Module power-on sequencing for GTR transceiver finished.
2Programmable Logic (PL)Procedure for PL starting.PL usage needs powered PS low-power domain.
2.1PL_DCIN3.3 V (± 5 %) 2)-Programmable logic power supply.Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.
2.2EN_PL-PU 3), PL_DCINProgrammable logic power enable.
2.3PG_PL-PU 3), PL_DCINProgrammable logic power good status.Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
2.4VCCO_47 / VCCO_48 / VCCO_64 / VCCO_65 / VCCO_66 4)-Module bank voltages.Enable bank voltages after PG_PL deassertion.
3GTH / GTY TransceiverProcedure for GTH / GTY transceiver starting.PL transceiver usage needs powered PL and low-power PS domain.
3.1GT_DCDC3.3 V (± 5 %) 2)-GTH transceiver power supply.Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
3.21)EN_PLL_PWR--PLL power enable.
3.21)PG_PLL_1V8--PLL power good status.
3.21)PLL_3V33.3 V (± 5 %)
PLL power supply
3.3EN_GT_L / EN_GT_RGT_DCDC-GTH / GTY left / right transceiver power enable.Transceivers on left / right side can be used independently.
3.4PG_GT_L / PG_GT_R--GTH / GTY transceiver power good status.
4MR

Manual ResetLow active release after all needed power domains are enabled. 

1) Optional

2) Dependent on the assembly option a higher input voltage may be possible. 

3) On module

4) See DS925 for additional information.

Baseboard Design Hints

Board to Board Connectors

5.2 x 7.6 cm UltraSoM+ modules use four Samtec Razor Beam LP Terminal Strip (ST5) on the bottom side.
  • 4x REF-192552-02 (160-pins)
    • ST5 Mates with SS5

5.2 x 7.6 cm UltraSoM+ carrier use four Samtec Razor Beam LP Socket Strip (SS5) on the top side.

  • 4x REF192552-01 (160-pins)
    • SS5 Mates with ST5
Features
  • Board-to-Board Connector 160-pins, 80 contacts per row
  • Ultrafine .0197" (0.50 mm) pitch
  • Narrow body design saves space on board
  • Lead style -03.5
  • Samtec 28+ Gbps Solution
  • Mates with: ST5
  • Insulator Material: Liquid Crystal Polymer, schwarz
  • Operating Temperature Range: -55°C bis +125°C
  • Lead-Free Solderable: Yes
  • RoHS Konform: Yes


Connector Stacking height

When using the standard type on baseboard and module, the mating height is 5 mm.

Other mating heights are possible by using connectors with a different height:

Order numberREF numberSamtec NumberTypeContribution to stacking heightComment
27219REF192552-01SS5-80-3.50-L-D-K-TRBaseboard connector3.5mm

Standard connector used on carrier

27018REF-189545-02 SS5-80-3.00-L-D-K-TRBaseboard connector3 mm 

Assembly option on request

27220REF-192552-02 ST5-80-1.50-L-D-P-TRModule connector1.5 mm

Standard connector used on modules

27017REF-189545-01 ST5-80-1.00-L-D-P-TRModule connector1 mm

Assembly option on request

Connectors.


The module can be manufactured using other connectors upon request.

Current Rating

Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row).

Connector Speed Ratings

The connector speed rating depends on the stacking height:

Stacking height

Speed rating

4 mm, Single-Ended13GHz/26Gbps
4 mm, Differential13.5GHz/27Gbps
5 mm, Single-Ended13.5GHz/27Gbps
5 mm, Differential20GHz/40 Gbps
Speed rating.

The SS5/ST5 series board-to-board spacing is currently available in 4mm (0.157"), 4.5mm (0.177") and 5mm (0.197") stack heights.

The data in the reports is applicable only to the 4mm and 5mm board-to-board mated connector stack height.

Manufacturer Documentation

  File Modified
PDF File hsc-report-sma_st5-ss5-04mm_web.pdf 30 05, 2017 by Susanne Kunath
PDF File hsc-report-sma_st5-ss5-05mm_web.pdf 30 05, 2017 by Susanne Kunath
PDF File REF-192552-01.pdf 13 11, 2017 by John Hartfiel
PDF File REF-192552-02.pdf 13 11, 2017 by John Hartfiel
PDF File ss5.pdf 13 11, 2017 by John Hartfiel
PDF File ss5-st5.pdf 13 11, 2017 by John Hartfiel
PDF File ss5-xx-x.xx-x-d-k-tr-mkt.pdf 13 11, 2017 by John Hartfiel
PDF File st5.pdf 13 11, 2017 by John Hartfiel
PDF File st5-xx-x.xx-x-d-p-tr-mkt.pdf 13 11, 2017 by John Hartfiel


Technical Specifications

Absolute Maximum Ratings *)

Power Rail Name/ Schematic NameDescriptionMinMaxUnit
LP_DCDCMicromodule Power-0.3004.0V
DCDCINMicromodule Power-0.3006.0V
GT_DCDCMicromodule Power-0.3006.0V
PL_DCINMicromodule Power-0.300

3.6

V
PLL_3V3PLL power supply-0.5003.8V
PS_BATTRTC / BBRAM-0.5002.000V
VCCO_47HD IO Bank power supply-0.5003.400V
VCCO_48HD IO Bank power supply-0.5003.400V
VCCO_64HP IO Bank power supply-0.5002.000V

VCCO_65

HP IO Bank power supply-0.5002.000V
VCCO_66HP IO Bank power supply-0.5002.000V
VREF_64Bank input reference voltage-0.5002.000V
VREF_65Bank input reference voltage-0.5002.000V
VREF_66Bank input reference voltage-0.5002.000V
Absolute maximum ratings

*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
   or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version.  Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

  • Variants of modules are described here: Article Number Information
  • Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
  • Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
  • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
  • The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.


ParameterMinMaxUnitsReference Document
LP_DCDC 1)3.1353.465V
DCDCIN 1)3.1353.465V
GT_DCDC 1)3.1353.465V
PL_DCIN 1)3.135

3.465

V
PLL_3V33.143.465V
PS_BATT1.2001.500VSee FPGA datasheet.
VCCO_471.1403.400VSee FPGA datasheet.
VCCO_481.1403.400VSee FPGA datasheet.
VCCO_640.9501.900VSee FPGA datasheet.

VCCO_65

0.9501.900VSee FPGA datasheet.
VCCO_660.9501.900VSee FPGA datasheet.
VREF_640.61.2VSee FPGA datasheet.
VREF_650.61.2VSee FPGA datasheet.
VREF_660.61.2VSee FPGA datasheet.

1) Higher values may possible. For more information consult schematic and according datasheets.

Recommended operating conditions.


Physical Dimensions

  • Module size: 76 mm × 52 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm.

PCB thickness: 1.6 mm (± 10 %).

Physical Dimension

Currently Offered Variants 

Trenz shop TE0808 overview page
English pageGerman page
Trenz Electronic Shop Overview

Revision History

Hardware Revision History

Board hardware revision number.


DateRevisionChangesDocumentation Link
-05Second production silicon:
  • revised PL_VCCINT power supply. PCB: revised routing and components placement;
  • added signal BG1 for DDP DDR4 IC. Added support of new packages. PCB: revised routing and components placement;
  • R5 pulled up to 1.2V. R5 value changed to 49.9R;
  • added test points;
  • added MAC EEPROM U48. I2C bus PLL_SCL/SDA. Added pull up resistor to I2C bus;
  • PCB - revised FPGA location. Package placed 1.5mm closer to connector J3;
  • PCB - updated silckscreen. Added company address, CE and WEEE symbols;
  • PCB - updated signal trace lengths.
  • (29.11.2022) Changed note near J2.97 and net PG_GT_L from "On board pull-up R" to "External pull-up R Required"
TE0808-05
-04First production silicon:
  • Added resistors R65,R82,R86,R87 (240R) for each DDR4-chip for supporting DDP DDR4 chips
  • Full library update
  • (09.06.2020) R19 value was changed to 10K (was: 4K99) to set PS_MGTRAVCC 0.85V
TE0808-04
-03Second ES production releaseTE0808-03
2016-03-0902First ES production releaseTE0808-02
-01Prototypes-
Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

 Date

Revision

ContributorsDescription

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  • change default RAM size on key feature section
  • typo and revision history update

2024-09-18

v.48

John Hartfiel

  • Review and Public Update

2023-10-13

v.44

ED 

  • Updated to new TRM style

2022-09-13

v.41Vadim Yunitski
  • Updated PG_PL pull-up resistor requirements
2021-09-07V.39John Hartfiel
  • Correction Power section
2021-05-17v.37John Hartfiel
  • typo correction in DDR section
2021-03-11v.35Antti Lukats
  • typo correction in PLL_RST
  • add pin on power rails table
  • correction MGT Lane assignment
  • correction MGT CLK assignment

2019-01-27

v.30Martin Rohrmüller
  • Corrected clock connection to J2

2018-11-20

v.29

John Hartfiel
  • Notes for power supply

2018-08-27

v.27John Hartfiel
  • typo correction SI5345 I2C address

2028-06-28

v.26John Hartfiel
  • typo SI5348 B2B IOs + link correction

2017-11-13

v.24Ali Naseri
  • updated B2B connector max. current rating per pin

2017-11-13

v.22
John Hartfiel
  • rework B2B section
2017-10-20

v.21

Ali Naseri
  • Update links (pdf, documentation) to revision 4
  • ES silicon note removed
2017-08-28
v.15
John Hartfiel
  • Update section: Variants Currently In Production

2017-08-28v.14Jan Kumann
  • Block diagram changed.
  • SPI flash section fixed.
  • Few smaller improvements.
2017-08-15v.12Vitali TsiukalaChanged signals count in the B2B connectors table
2017-08-15

v.11

John Hartfiel, Ali Naseri
  • PCB REV04 Initial release
  • update boot mode section
2017-02-06v.1Jan KumannInitial document

--

all

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  • --
Document change history.

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Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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