TEBF0808 TRM

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Table of Contents

Overview

The Trenz Electronic TEBF0808 Carrier Board is a baseboard for the Xilinx Zynq Ultrascale+ MPSoC modules TE0808 and TE0803, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ SoMs and for developing purposes.

Key Features

Mini-ITX form factor
ATX Power supply connector (Important 12V only Supply Required)
optional 12V Standard Power Plug
USB3 with USB3 HUB
Gigabit Ethernet RJ45
MicroSD Card (bootable)
eMMC (bootable)
PCIe slot - one PCIe lane (16 Lane Connector)
Displayport Single Lane
One SATA Connector
FMC HPC Slot (1.8V max VCCIO)
Dual SFP+
One Samtec FireFly (4 GT lanes bidir)
One Samtec FireFly connector for reverse loopback
Fan connectors, PC Enclosure, FMC Fan
Intel front panel connector (PWR/RST/LED)
Intel HDA Audio connector
CAN FD Transceiver (10 Pin IDC Connector)
20 Pin ARM JTAG Connector (PS JTAG0)

PC Enclosure Rear Panel Accessible I/O

PCIe accepting 16 Lane PCIe cards (one lane used PS GT)
FMC HPC
Dual SFP+
RJ45 Gigabit Ethernet
2x USB3 Host
Displayport (Single lane)
microSD
Two LED's
CAN FD (using DB9 to IDC10 Cable)
One PMOD

PC Front Panel I/O

Reset Button
Power Button
Power LED
HD LED
Intel HDA Audio
One USB2 HS Host port
One USB3 SS Host port

The above I/O interfaces are accessible using standard PC front panel cables.

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TEBF0808-04 Block Diagram

Main Components

Figure 2: TEBF0808-04 Carrier Board

PMOD connector, P2
MicroSD Card socket (on bottom side), J16
Display Port socket, J13
USB3.0 A 2x , RJ45 1x (stacked), J7
SFP+ 2x1 cage, J14
PCIe x16 connector (one PCIe lane connected), J11
FMC HPC, J5
FMC-Fan connector 5V, J19
USB3.0 connector, J8
PC-BEEPER 4-pin header, J23
SMA coaxial connector (SI5338A clock output), J32
SMA coaxial connector (clock input to MPSoC module), J33
eMMC Card socket, J27
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
CAN bus 6-pin header, J29
CAN bus 10-pin connector, J24
ARM-JTAG 20-pin connector, J30
ATX power supply connector, J20
4-Wire PWM fan connector, J35
JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to MPSoC module, J12
JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to System Controller CPLDs, J28
Power Jack 2.1mm 12V, J25
4x DIP-switch, S5
Power Button, S1
Samtec FireFly Connector for reverse loopback, J21/J22
Samtec FireFly Connector (4 GT lanes bidirectional), J6/J15
SATA Header, J31
4-Wire PWM fan connector, J26
Programmable on-module PLL I²C interface 10-pin header, J17
Reset Button, S2
INTEL HDA 9-pin header, J9
Intel front panel (PWR/RST/LED) 9-pin header, J10
Samtec FireFly Connector J6/J15 I²C interface 3-pin header, J34
4x DIP-switch, S4
PMOD connector, P3
PMOD connector, P1
Battery Holder CR1220, B1

Initial Delivery State

Storage device name	Content	Notes

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector:

Bank	Type	B2B Connector	I/O Signal Count	LVDS Pairs Count	Bank Voltage	Notes

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

For detailed information about the pin out, please refer to the Pin-out Tables.

The configuration of the I/O's MIOx, MIOx ... MIOx, ... are depending on the base-board peripherals connected to these pins.

MGT Lanes

Bank

Type

Lane Count

B2B Connector

Schematic Names / Connector Pins

FPGA Pin Name

MGT Bank's Reference Clock Inputs

111

GTX

4

J1

MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21
MGT_TX4_P, MGT_TX4_N, pins J1-22, J1-20

MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15
MGT_TX5_P, MGT_TX5_N, pins J1-16, J1-14

MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9
MGT_TX6_P, MGT_TX6_N, pins J1-10, J1-8

MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5
MGT_TX7_P, MGT_TX7_N, pins J1-4, J1-6

1 Reference clock MGT_CLK3 from programmable
quad clock generator U16 to bank's pins AA6/AA5.

1 Reference clock MGT_CLK2 from B2B connector J3
(pins J3-81, J3-83) to bank's pins W6/W5.

JTAG Interface

JTAG access to the ... is provided through B2B connector ....

JTAG Signal	B2B Connector Pin
TCK
TDI
TDO
TMS

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Pin Name	Mode	Function	B2B Connector Pin	Default Configuration
PGOOD	Output	Power Good	J1-148	Active high when all on-module power supplies are working properly.
JTAGEN	Input	JTAG Select	J2-131	Low for normal operation.

Quad SPI Interface

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

MIO	Signal Name	U14 Pin
1	SPI-CS	C2
2	SPI-DQ0/M0	D3
3	SPI-DQ1/M1	D2
4	SPI-DQ2/M2	C4
5	SPI-DQ3/M3	D4
6	SPI-SCK/M4	B2

Gigabit Ethernet

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

PHY Pin	PS	PL	B2B	Notes

USB Interface

USB PHY is provided with ...

PHY Pin	Pin	B2B Name	Notes

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:

I2C Device	I2C Address	Notes

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.

MODE Signal State	Boot Mode
high or open	SD Card
low or ground	QSPI

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL...

Programmable PLL Clock (Phase-Locked Loop)

There is a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U..) ..

Si5338A (U13) Input	Signal Schematic Name	Note
IN1/IN2	CLKIN_P, CLKIN_N	Reference clock signal from B2B connector J3, pins J3-74, J3-76 (base board decoupling capacitors and termination resistor necessary).
IN3	reference clock signal from oscillator SiTime SiT8008BI (U21)	25.000000 MHz fixed frequency.
IN4/IN6	pins put to GND	LSB (pin 'IN4') of the default I²C-adress 0x70 not activated.
IN5	not connected	-
Si5338A (U13) Output	Signal Schematic Name	Note
CLK0 A/B	MGTCLK1_P, MGTCLK1_N	Reference clock signal to MGT bank 112, pins U6/U5 (100 nF decoupling capacitors).
CLK3 A/B	MGTCLK3_P, MGTCLK3_N	Reference clock signal to MGT bank 111, pins AA6/AA5 (100 nF decoupling capacitors).

Oscillators

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Clock Source	Schematic Name	Frequency	Clock Input Destination
SiTime SiT8008BI oscillator, U21	-	25.000000 MHz	Quad PLL clock generator U16, pin 3

On-board LEDs

LED	Color	Connected to	Description and Notes

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Input Pin	Typical Current
VIN	TBD*
3.3VIN	TBD*

* TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.

To avoid any damage to the SoC module, check for stabilized on-board voltages in steady state before powering up the SoC's I/O bank voltages VCCO_x. All I/O's should be tri-stated during power-on sequence.

Power Distribution Dependencies

regulator dependencies and max. current.

put diagram here...

See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Power-On Sequence Diagram

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

put diagram here...

Voltage Monitor Circuit

if this circuit is fitted on module, describe it here...

Power Rails

Voltages on B2B-Connectors	B2B	B2B	B2B	Input / Output	Note

Bank Voltages

Bank	Schematic Name	Voltage	Voltage Range
500 (MIO0)	PS_1.8V	1.8V	-
501 (MIO1)	PS_1.8V	1.8V	-
502 (DDR3)	1.35V	1.35V	-
12 HR	VCCIO_12	User	HR: 1.2V to 3.3V
13 HR	VCCIO_13	User	HR: 1.2V to 3.3V
33 HP	VCCIO_33	User	HP: 1.2V to 1.8V
34 HP	VCCIO_34	User	HP: 1.2V to 1.8V
35 HP	VCCIO_35	User	HP: 1.2V to 1.8V

Board to Board Connectors

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Variants Currently In Production

Module Variant	Zynq SoC	SoC Junction Temperature	Operating Temperature Range
TE0745-02-30-1I	XC7Z030-1FBG676I	–40°C to +100°C	Industrial
TE0745-02-35-1C	XC7Z035-1FBG676C	0°C to +85°C	Commercial
TE0745-02-45-1C	XC7Z045-1FBG676C	0°C to +85°C	Commercial
TE0745-02-45-2I	XC7Z045-2FBG676I	–40°C to +100°C	Industrial

Technical Specifications

Absolute Maximum Ratings

Parameter	Min	Max	Units	Reference Document
VIN supply voltage			V	-
Storage temperature			°C	-

Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

Parameter	Min	Max	Units	Reference Document
VIN supply voltage
Operating temperature

Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

Module size: ... mm × ... mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: ... mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

All dimensions are given in millimeters.

Put mechanical drawings here...

Revision History

Hardware Revision History

Date	Revision	Notes	PCN	Documentation Link
-	01	Prototypes

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Put pic of PCB silk screen here showing model and revision ...

Document Change History

Date	Revision	Contributors	Description
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2017-06-08	v.20	John Hartfiel	add revision number and update document change history
2017-05-30	v.1	Jan Kumann	Initial document.
	all	Jan Kumann, John Hartfiel

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The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

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Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

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RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.

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Features

Mini-ITX form factor
ATX Power supply connector (Important 12V only Supply Required)
optional 12V Standard Power Plug
USB3 with USB3 HUB
Gigabit Ethernet RJ45
MicroSD Card (bootable)
eMMC (bootable)
PCIe slot - one PCIe lane (16 Lane Connector)
Displayport Single Lane
One SATA Connector
FMC HPC Slot (1.8V max VCCIO)
Dual SFP+
One Samtec FireFly (4 GT lanes bidir)
One Samtec FireFly connector for reverse loopback
Fan connectors, PC Enclosure, FMC Fan
Intel front panel connector (PWR/RST/LED)
Intel HDA Audio connector
CAN FD Transceiver (10 Pin IDC Connector)
20 Pin ARM JTAG Connector (PS JTAG0)

PC Enclosure Rear Panel Accessible I/O

PCIe accepting 16 Lane PCIe cards (one lane used PS GT)
FMC HPC
Dual SFP+
RJ45 Gigabit Ethernet
2x USB3 Host
Displayport (Single lane)
microSD
Two LED's
CAN FD (using DB9 to IDC10 Cable)
One PMOD

PC Front Panel I/O

Reset Button
Power Button
Power LED
HD LED
Intel HDA Audio
One USB2 HS Host port
One USB3 SS Host port

The above I/O interfaces are accessible using standard PC front panel cables.

TEBF0808-REV2 Component Locations

Callout	Feature	Component Designator
1	PMod 2x6 Socket	P2
2	MicroSD Connector (Bottom)	J16
3	Display Port Socket	J13
4	USB3.0 A 2x , RJ45 1x Stacked	J7
5	Dual SFP+	J14
6	PCIe x16 Connector (one PCIe lane connected)	J11
7	FMC (1.8V max VCCIO)	J5
8	FAN-FMC 2 Pol.	J19
9	USB3 Connector 19 Pol.	J8
10	USB 3.0 A Connector	J18
11	SMA (SI5338 CLK1A)	J32
12	SMA (B2B-IN2_P)	J33
13	SD Card Socket	J27
14	CAN PIN-Header 6 Pol.	J29
15	CAN Connector 10 Pol.	J24
16	4x Samtec B2B -Connector for TE0808	J1,J2,J3,J4
17	eMMC (MTFC16GJVEC-2M WT)	U2
18	Battery holder CR1220	B1
19	JTAG Connector 20 Pol.	J30
20	ATX Power supply connector	J20
21	PMod 2x6 Socket	P3
22	FFA I2C Pin Header	J34
23	Jumper 2x4 (Configuration)	S4
24	BEEPER PIN Header 4 Pol.	J23
25	Pin Header 12 Pol. (XMOD-FPGA Access)	J12
26	Pin Header 12 Pol. (XMOD-Carrier CPLD Access)	J28
27	Pin Header 9 Pol. (Intel front panel (PWR/RST/LED))	J10
28	PMod 2x6 Socket	P1
29	INTEL HDA Header 9 Pol.	J9
30	PLL I2C Connector 10 Pol.	J17
31	RST Push Button	S2
32	Samtec FireFly (4 GT lanes bidirectional)	J6,J15
33	SATA Header	J31
34	FAN-1 4 Pol.	J26
35	Samtec FireFly Connector for reverse loopback	J21,J22
36	Jumper 2x4- CPLD	S5
37	PWR Push Button	S1
38	Power Jack 2.1mm 12V	J25

Table: Board Component Description

TE0808 GT Transceivers

GT Lane	Function	Ref Clock
PS 0	PCIe	100
PS 1	USB3	100
PS 2	SATA	150
PS 3	DP.0	27
B128 0..3	FireFly
B228 0..3	FMC 0..3
B229 0..3	FMC 4..7
B230 0.1	FMC 8..9
B230 2	SFP	125/156.25
B230 3	SFP	125/156.25

GT Lane Assignment

GT Clock	From	Default	Notes
PS 0	Oscillator	User	not fitted oscillator
PS 1	Oscillator	150MHz	SATA
PS 2	Si5345	100Mhz	USB/PCIe
PS 3	Si5345	27Mhz	DisplayPort
B128 0	Si5345
B128 1	not used
B228 0	FMC GTCLK 0	User
B228 1	Si5345
B229 0	FMC GTCLK 1	User
B229 1	Si5345	User
B230 0	Si5345	User
B230 1	Si5345

GT CLK Assignment

TE0808 MIO Assignment

MIO	Default	Alternate	Notes
0..12	Dual QSPI	-	Bootable
13..23	SD0: eMMC	-	Bootable
24, 25		CPLD MUXED
26..29	PJTAG0	CPLD MUXED	Bootable JTAG
30		CPLD MUXED
31	PCIe	CPLD MUXED	Same as ZCU102
32		CPLD MUXED
33	PMU	CPLD MUXED	Same as ZCU102
34..37	DPaux	CPLD MUXED
38, 39	I2C0	-
40, 41	CAN1	CPLD MUXED
42, 43	UART0	CPLD MUXED
44	I2C Interrupt	CPLD MUXED
45..51	SD1: SD	-	Bootable SD Card
52..63	USB0	-
64..75	GEM3	-
76, 77	MDIO

MIO Assignment

TE0808 Si5345 PLL Settings

Input/Output	Connected to	Frequency	Used as	Notes
IN0	Oscillator	25MHz	Internal Reference
IN2	SMA	User	External Reference
OUT0	PCIe	100MHz	PCIe REFCLK
OUT1	B230 CLK0	125MHz	FMC GT Clock
OUT2	B229 CLK1	User	FMC GT Clock
OUT3	B228 CLK1	User	FMC GT Clock
OUT4	B505 CLK2	100MHz	PCIe and USB Clock
OUT5	B505 CLK3	27MHz	DisplayPort GT SERDES Clock
OUT6	B128 CLK0	157.6MHz (2 x 78.8)	DP Video Pixel Clock	Seems to be needed for DP to work
OUT7	B230 CLK1	156.25Mhz	SFP Clock
OUT8	Si5338 IN1	25Mhz	Si5338 Reference

Recommended/Default settings for the Si5345

By default Si5345 is not programmed after power on, so if FSBL is executed without proper Si5345 init or if psu_init.tcl is invoked and the design does use PS GT, then FSBL or psu_init.tcl would freeze on SERDES init code. Si5345 init does persist over reset sequence so it is possible to use known good boot files to init Si5345 and then FSBL debugging is also possible.

FMC Slot

FMC Slot is fitted as full FMC HPC.

Note: FMC VADJ maximum voltage is 1.8V (as HP banks do not support more than 1.8V).

Signals	MPSoC PS/PL
FMC LA	HP	Mapped to PL HP Banks
FMC HA	HP/HD	HP/HD banks mixed
FMC HB	HP/HD	HP/HD banks mixed
CLK0	PL Clock	HP Bank
CLK1	PL Clock	HD Bank
CLK2	Clock from Si5345	use as clock input not supported
CLK3	Clock from Si5345	use as clock input not supported
GT CLK0	B228 CLK1
GT CLK1	B229 CLK1
I2C	PS I2C	via I2C multplexer
GA0, GA1	0	Address set to 00

Optional FAN can be mounted below the FMC slot. Ther are no components below the FMC card, so FMC cards with extended component heights can be used.

I2C Buses

Bus #	Device(s)	Addresses	Notes
0	MUX U16
1	Si5338 on base	0x70
2	GPIO Extender	0x26
3	PCIe SMBus
4	SFP
5	SFP
6	GPIO, EEPROM	0x27, 0x50, 0x51, 0x52, 0x54
7	FMC	0x50 FRU EEPROM	other address depend on FMC Card
8	USB3 HUB		For REV 2 - DO NOT SCAN will cause I2C bus freeze!
9	PMOD
10	ADAU1761	0x38
11	FireFly
12	FireFly
13	Si5345	0x69	Access to PLL on TE0808
14	CPLD	-
15	GPIO	0x24
16	PMOD

List of I2C buses and devices (bus numbers as enumerated by Linux).

Do not scan bus 8, this would cause the I2C bus multiplexer to freeze until power off or hardware reset.

To init Si5345 use command

si534x /dev/i2c-13 0x69

DIP Switches

There are two 4 bit DIP Switches on the TEBF0808, they must be used to select some options. On TEBF0808-02 default CPLD-Firmware selects boot from SD-Card, Firmware update is needed for Boot-Mode selection.

1	2	3	4	Description
ON	ON	ON	ON	Default, boot from SD/eMMC, 1.8V FMC VADJ
ON	ON	x	x	Boot from microSD, SD or SPI Flash
OFF	ON	x	x	Boot from eMMC
ON	OFF	x	x	Boot mode PJTAG0
OFF	OFF	x	x	Boot mode main JTAG
x	x	x	ON	FMC VADJ = 1.8V
x	x	x	OFF	FMC VADJ = 1.2V

DIP Switch S5 located close to PWR push-button. This DIP Switch is connected to the two baseboard control CPLD's.

1	2	3	4	Description
OFF	OFF	OFF	ON	Default
ON	x	x	x	PUDC = 0
OFF	x	x	x	PUDC = High

DIP Switch S4 located close to PCIe slot.

LEDs

LED	Position	Description
D4	Green LED near DisplayPort Connector
D5	Red LED near DisplayPort Connector
D6	Green LED near Reset Button
D7	Red LED near Reset Button

Power

ATX Power is supported but special 12V ATX power supply must be used.

System controller RGPIO

Master CPLD Read

Bit	Description
31	'1' - Constant value
30	'0' - Constant value
29	'1' - Constant value
28	'0' - Constant value
27
26
25
24
23
22
21	SCL
20	SDA
19	DP PHD
18	JTAG TMS
17	JTAG TDI
16	JTAG TCK
15	JTAG SRST
14	JTAG TRST
13	FMC CLKDIR
12	FMC TDO
11	PHY LED2
10	PHY LED1
9	PHY LED0
8	CAN Fault
7	MIO29
6	MIO28
5	MIO27
4	MIO26
3	XMOD Button
2	SD WP
1	SW4
0	SW3

Master CPLD Write

Bit	Description
31	'1' - Constant value
30	'0' - Constant value
29	'1' - Constant value
28	'0' - Constant value
27
26
25
24
23
22
21
20
19
18
17
16
15
14	JLED2B
13	JLED2A
12	JLED1
11	SFP_LED3
10	SFP_LED2
9	SFP_LED1
8	SFP_LED0
7	LED1
6	LED0
5	USB HUB MODE1 ('1' for ROM Mode)
4	USB HUB MODE0 ('1' for ROM Mode)
3	Ethernet PHY Reset (Active High)
2	I2C Reset (Active High)
1	USB HUB Reset (Active High)
0	USB PHY Reset (Active High)

Slave CPLD Read

Bit	Description
31	'1' - Constant value
30	'0' - Constant value
29	'1' - Constant value
28	'0' - Constant value
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9	PLL LOL
8	XMOD Button
7	Power OK
6	Fan Senese
5	SD Detect
4	Micro SD Detect
3	Power Button
2	Reset Button
1	SW2
0	SW1

Slave CPLD Write

Bit	Description
31	'1' - Constant value
30	'0' - Constant value
29	'1' - Constant value
28	'0' - Constant value
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11	FAN_EN
10	HDLED_P
9	HDLED_N
8	LED_P
7	LED_N
6	LED3
5	LED2
4	FPGA PROG (Active High)
3	PCIe Reset (Active High)
2	MRESET Reset (Active High)
1	SRST Reset (Active High)
0	PLL Reset (Active High)

Trenz Electronic Documentation