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Overview

The Trenz Electronic TEF0008 is an FMC HPC (FPGA to Mezzanine Card / VITA 57.1) expansion card which offers four SFP+ 10 Gb ports for SFP modules which is intended for FMC HPC carrier usage and can not be used as stand-alone solution. An Altera MAX10 FPGA is onboard for control, management and custom purposes.

Refer to https://trenz.org/tef0008-info for current online available documentation.

Key Features

  • FPGA
    • Altera MAX10 FPGA : 10M08SAU169I7G
    • Temperature Range : I
    • Package :                   U169 - Ultra FineLine BGA 169 pins
  • RAM/Storage
    • FMC FRU EEPROM 32 Kbit
  • On Board
    • Programmable clock generator
    • 1x Crystal and 1x Oscillator for the Clock Generator
  • Interface
    • FMC HPC connector
    • 4x QSFP+ connectors
    • Pin header for JTAG and I2C - optional populated
    • 2x DIP switches - 1x JTAG enable and 1x user definable
    • 1x green LED - Card status
  • Power
    • 2x 3.3 V Rails
    • Variable voltage rail
  • Dimension
    • 69.0 mm x 90.36 mm
    • modified FMC single width expansion module - Consider to check your requirements.

Block Diagram


TEF0008 block diagram


Main Components

TEF0008 main components


  1. Altera MAX10 FPGA, U5
  2. Programmable clock generator, U2
  3. Oscillator, U1
  4. Crystal, Y1
  5. FMC FRU EEPROM, U4
  6. 2x DIP switches - JTAGEN / USR_SW, S1
  7. 3x pin header for PLL I2C, J1
  8. 6x pin header for JTAG, J3
  9. FMC HPC connector, J2
  10. 4x SFP+ connectors, J4, J5, J6, J7
  11. LED green - status adapter, D1

Initial Delivery State

Storage device name

Designator

Content

Notes

Altera MAX10 FPGA

U5

Firmware

For further information see TEF0008 MAX10 Firmware / TEF0008 MAX10.

FMC FRU EEPROM

U4

Not programmed


Clock generator

U2

Programmed


Initial delivery state of programmable devices

Programmable clock generator

The programmable Clock Generator (Si5345A, U2) is programmed according to the table below. 

It can be controlled via the PLL I2C bus (Pin header J1) or via the FPGA (MAX10 U5) as I2C controller.


Programmable Clock Generator

Clock generator

OUT/IN put / Net Name / Destination/Source Device.Pin

IO Standard

Default Frequency in MHz

Notes



Input

XA/XB / XAXB_P/XAXB_N / Y1.3/Y1.1

Analog

54 MHz


IN0 / IN0_P/IN0_N / U1.3/U1.2

LVDS

25 MHz


IN1 / Not used

-

-


IN2 / Not used

-

-


IN3 / CLK2_C_P/CLK_2_N CLK2_P/CLK2_N / J2.K4/J2.K5

LVDS

-

Frequency defined by carrier.



Output

OUT0 / CLKPLL2F_P/CLKPLL2F_N / U5.H6/U5.G5

LVDS 1.8 V

25 MHz


OUT1 / GCLKF_P/GCLKF_N / U5.H4/U5.H5

LVDS 1.8 V

125 MHz


OUT2 / GBTCLK1_P/GBTCLK1_N / J2.B20/J2.B21

LVDS 1.8 V

125 MHz


OUT3 / Not used

-

-


OUT4 / Not used

-

-


OUT5 / Not used

-

-


OUT6 / Not used

-

-


OUT7 / GBTCLK0_P/GBTCLK0_N / J2.D4/J2.D5

LVDS 1.8 V

156¼ MHz


OUT8 / CLK0_P/CLK0_N / J2.H4/J2.H5

LVDS 1.8 V

156¼ MHz


OUT9 / CLK1_P/CLK1_N / J2.G2/J2.G3

LVDS 1.8 V

125 MHz


Signals, Interfaces and Pins

Connectors

Connector Type

Designator

Interface

IO count

Notes

FMC HPC

J2

GPIO

20x SE


FMC HPC

J2

MGT

4x GTX (RX/TX)


FMC HPC

J2

JTAG

4x SE


FMC HPC

J2

I2C

2x SE


SFP+

J4 / J5 / J6 / J7

MGT

1x GTX (RX/TX)


Board connectors

Test Points

Test

Point

REV03

REV02

Signal


Notes

Top

Bottom

Signal

TP1


x

TDI


TP2


x

TCK


TP3


x

TDO


TP4


x

TMS


TP5


x

GND


TP6


x

3P3V


TP7


x

M10_RST


TP8


x

M10_TX


TP9


x

M10_RX


TP10


x

1.8V


TP11


x

VADJ

Not used


TP12


x

3P3VAUX

Not used


Test points information


On-board Peripherals

Chip / Interface

Designator

Connected to

Notes

FPGA

U5

  • Clock generator U2
  • DIP switches S1
  • I2C pin header J1
  • JTAG header J3
  • SFP+ connectors J4, J5, J6, J7
  • FMC HPC connector J2

For further information see TEF0008 MAX10 Firmware / TEF0008 MAX10.

Clock generator

U2

  • FPGA U5
  • Oscillator U1
  • Crystal Y1
  • I2C pin header J1
  • FMC HPC connector J2


FMC FRU EEPROM

U4

  • FMC HPC connector J2


Oscillator

U1

  • CLK Generator U2

25 MHz

Crystal

Y1

  • CLK Generator U2

54 MHz

On-board peripherals


Configuration and System Control Signals

Control signals represent hardware defined logic states, for final state consider the firmware and reference designs.

Control Signals and Buses

Signal Name

Connector.Pin

Direction 1)

Description

I2C ( LA00_P / LA00_N / LA01_P )


J2B.G6 / J2B.G7 / J2B.D8

IN / IN / OUT

3 wire I2C bus. SCL in / SDA in / SDA out.

LA01_N / LA02_P /LA02_N

J2B.D9 / J2B.H7 / J2B.H8

IN

Mux signals to select a SFP I2C canal.

LA03_N / LA04_P

J2B.G10 / J2B.H10

IN

SFP RS0 / RS1 signals.

LA03_P

J2B.G9

IN

SFP TX disable signals.

LA04_N

J2B.H11

OUT

SFP TX fault/error signal.

LA05_N / LA06_N / LA07_N / LA08_N

J2B.D12 / J2B.C11 / J2B.H14 / J2B.G13

OUT

SFP LOS A / LOS B / LOS C / LOS D signals.

LA05_P / LA06_P / LA07_P / LA08_P

J2B.D11 / J2B.C10 / J2B.H13 / J2B.G12

OUT

SFP A/B/C/D Inserted Flag

PG_C2M

J2F.D1

IN

Power good carrier to module.

PG_M2C

J2F.F1

OUT

Power good module to carrier.

JTAG ( TMS / TDI / TDO / TCK )

J3.1 / J3.2 / J3.3 / J3.4
J2F.D33 / J2F.D30 / J2F.D31 / J2F.D29

Signal dependent

JTAG for FPGA MAX10 U5.

I2C ( PLL_SCL / PLL_SDA )

J1.1 / J1.3

Signal dependent

I2C for Programmable Clock Generator U2 and FPGA MAX10 U5.

GA0 / GA1

J2F.C34 / J2F.D35

IN

Geographic addresses of FMC FRU EEPROM.

I2C ( FMC_SCL / FMC_SDA )

J2F.C30 / J2F.C31

Signal dependent

I2C for FMC FRU EEPROM.

 - / LED D1

U5.C2

OUT

Signals that at least one SFP is connected.

1) Direction:

    • IN: Input from the point of view of this board.

    • OUT: Output from the point of view of this board.

    • INOUT: Bidirectional signal.
    • Signal dependent: The signal direction depends on the function within the bus.
Control signals and buses

DIP Switches

DIP switch group

DIP switch

Signal name

Description

S1

S1A

JTAG_EN

Enable/Disable JTAG interface to FPGA U5.


S1B

USR_SW

User definable

DIP switches

Power and Power-On Sequence

Power Rails


Power Rail Name / Schematic Name

Description

Connector.Pin

Direction 1)

Notes

12V

Rail not used on module.

J2G.C35 / J2G.C37

-


3P3V

Main module supply

J2G.D36 / J2G.D38 / J2G.D40 / J2G.C39

J3.6

IN

max. 3 A

VADJ

Adjustable voltage supply rail for FPGA GPIO bank 3.

J2G.H40 / J2G.G39 / J2G.F40 / J2G.E39

IN

max. 4 A

3P3VAUX

Auxiliary supply rail.

J2G.D32

IN

max. 20 mA

1) Direction:

    • IN: Input from the point of view of this board.

    • OUT: Output from the point of view of this board.

Power rails

Recommended Power up Sequencing


Sequence

Net name

Recommended Voltage Range

Pull-up/down

Description

Notes

0

-

-

-

Configuration SoM signal setup.

See Configuration and System Control Signals.


1

3P3V

3.3 V ±5 %

-

Apply main module supply.


VADJ

3.3 V ±5 %

-

Apply adjustable voltage supply.


3P3VAUX

3.3 V ±5 %

-

Apply auxiliary supply.


Power sequencing

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings *)

Warning!

The listed values ONLY reflect this board. Connected Carriers / SoMs / Boards are not considered. 

Power Rail Name / Schematic Name

Description

Min

Max

Unit

Notes

3P3V

Main module supply

-0.5

3.9

V


VADJ

Adjustable voltage supply rail for FPGA GPIO bank 3.

-0.5

3.9

V


3P3VAUX

Auxiliary supply rail

-0.5

6.5

V


Absolute maximum ratings

*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Temperature range

Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.

The categories are:

  • Modules with commercial (C) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
  • Modules with extended (E) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
  • Modules with industrial (I) temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.

These categories do not take into account the entire custom system consisting of:

  • Customer FPGA design. The allowed main FPGA  temperature range is specified from the vendor by junction temperature using corresponding classes (C, E, I). See vendor documentation.
  • Cooling solution, active and or passive cooling.
  • Climate or environmental conditions besides ambient temperature range.
  • Module orientation, neighbouring assemblies, neither other heat sources nor the SoC as heat source to other components.

The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.

Voltage rails

The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).

Power Rail Name/ Schematic Name

Description

Min

Max

Units

Notes

3P3V

Main module supply

3.135

3.465

V


VADJ

Adjustable voltage supply rail for FPGA GPIO bank 3.

0

3.465

V


3P3VAUX

Auxiliary supply rail

3.135

3.465

V


Recommended operating conditions

Physical Dimensions

  • Module size: 69.0 mm x 90.36 mm.  Please download the assembly diagram for exact numbers.

  • PCB thickness: 1.61 mm ±10 %.

Physical dimension


Currently Offered Variants 

Trenz shop TEF0008 overview page
English pageGerman page
Trenz Electronic shop overview


Revision History

Hardware Revision History

The hardware revision number can be found on the PCB together with the module's model number, separated by a dash.

Board hardware revision number

Date

Revision

Changes

Documentation Link

2025-07

03

  1. Serial number S/N1 removed.
  2. PM1 - PM6 FIDU-DOT-small changed to FIDU-DOT-mini.
  3. ESD, UKCA, ADDRESS, ROHS logos added.
  4. Legal Notices page added.
  5. Page numbering changed.
  6. C35 , C41 , C47 , C53 , C38 , C44 , C50 , C56 10uF changed to 22uF. L4 - L11 1uH changed to 4.7uH according SFP+ power filter specification.
  7. TP11 , TP12 added.
  8. U6 EP53A7HQI (EOL) changed to MPM3834.
  9. U5A 10M08SAU169C7G (commercial grade) changed to 10M08SAU169I7G (industrial grade).
  10. Added a second MAX10 differential clock input:
    • new net "GCLKF" connected between PLL U2 pin 28, 27 and MAX10 U5B pin H4, H5.
    • U5B pin L1 connected to reference voltage 0.9V.
    • U2 Pin 26 connected to "PLL_VDD_1V8" and added decoupling capacitor C61.
    • added termination circuit R43 - R47 ,C62 , C63.
    • "CLK OVERVIEW" page changed. Added clock GCLKF.
  11. Added possibility to control a state of JTAG_EN pin. Nets "JTAG_EN" and "USR_SW" added. Switch S1A S1B added. R48 added.
  12. EEPROM U4 24LC128-I/ST (128 kbit) changed to M24C32-RDW6TP (32 kbit) according VITA 57.1 standard.
  13. EEPROM addressing changed according VITA 57.1 standard. R38 - R41 added.
  14. System Overview added.
  15. Power diagram added.
  16. Net PG_1V8 added for DCDC U6. R49 added. Added possibility to use net PG_1V8 as PG_M2C signal.

REV03

PCN

2018-07

02

  1. Removed I2C from FMC EEPROM to MAX10 FPGA.

REV02

PCN
PCN

2018-05

01

Initial revision

-

Hardware revision history


Document Change History

DateRevisionContributorDescription

  • Updated to TRM template 4.3.9

2026-07-016

v.44

Kilian Jahn

  • JTAG Interface / FMC connector - Altered information about JTAG access / Removed entry JTAG_EN

2026-04-14

v.43

Martin Rohrmüller

  • Removed wrong size of EEPROM from Main Components table

2025-10-29

v.42

Maksim Tserabei

  • add default CLK values also to SI section
  • changes on document change history style
2025-10-29

v.41

Maksim Tserabei 

updated according new REV03
2018-08-24v.38Martin Rohrmüller
  • Updated Table 15 and 17 to Rev02.

  • Added FMC connector pin assignment (Table 8).

2018-06-15


v.32


Martin Rohrmüller

  • Initial document.
---

all

  • ---
Document change history

Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Product Disclaimer

Products (incl. Software and Firmware) are exclusively designed, manufactured, and distributed for industrial applications. They are not intended, authorized, or certified for use in critical safety applications, medical devices, aerospace, nuclear, life-support, traffic-control, military, or other environments where malfunction or failure could result in personal injury, death, or significant property or environmental damage.

Trenz Electronic GmbH (“Manufacturer”) excludes any liability for inappropriate use in such contexts. The Customer bears all responsibility for verifying suitability and compliance with applicable regulations when deploying in any critical-use scenario. The Customer also agrees to indemnify and hold harmless the Manufacturer from any third-party claims or liabilities arising from such use.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.




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