Table of contents
Overview
TE0729 Basic-System with Watchdog example via VIO Interface.
Key Features
- PetaLinux
- SD
ETH (1 x 1 GBit 2 x 100 MBit)
- USB
- I2C
- RTC
- Watchdog Test example over VIO
- optional Special FSBL to select eMMC instead of SD
- Special FSBL for QSPI programming
Revision History
Date | Vivado | Project Built | Authors | Description |
---|---|---|---|---|
2018-07-16 | 2018.2 | TE0729-test_board-vivado_2018.2-build_02_20180716161110.zip TE0729-test_board_noprebuilt-vivado_2018.2-build_02_20180716161138.zip | John Hartfiel | initial release |
Release Notes and Know Issues
Issues | Description | Workaround | To be fixed version |
---|---|---|---|
No known issues | --- | --- | --- |
Requirements
Software
Software | Version | Note |
---|---|---|
Vivado | 2018.2 | needed |
SDK | 2018.2 | needed |
PetaLinux | 2018.2 | needed |
Hardware
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | Others | Notes |
---|---|---|---|---|---|---|
TE0729-02-2IF | 2if | REV02, REV01 | 512MB | 32MB | 2IF-K is the same with head sink | |
TE0729-02-2IR | 2ir | REV02 | 512MB | 32MB | PL ETHs, RTC are no assembled | external ISSI Flash configuration only with SDK possible on 18.2 |
Design supports following carriers:
Carrier Model | Notes |
---|---|
TEB0729 | Used as reference carrier. |
Additional HW Requirements:
Additional Hardware | Notes |
---|---|
USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct typ |
XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
Type | Location | Notes |
---|---|---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
SDK/HSI | <design name>/sw_lib | Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI |
PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
Additional Sources
Type | Location | Notes |
---|---|---|
init.sh | <design name>/misc/init_script | Additional Initialization Script for Linux |
Prebuilt
File | File-Extension | Description |
---|---|---|
BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Use TE Template from /os/petalinux
- HDF is exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
Launch
Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0729" possible - Copy image.ub on SD-Card
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Insert SD-Card
SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- I2C 0 Bus type: i2cdetect -y -r 1
- ETH0 works with udhcpc
- ETH1 must be configured manually
- ifconfig eth1 up
- ifconfig eth1 <ip>
- ETH1 must be configured manually
- ifconfig eth1 up
- ifconfig eth1 <ip>
- RTC check: dmesg | grep rtc
- USB: insert USB Stick or lsusb
Vivado HW Manager
- Open Vivado Hardware Manager with auto connect.
- Use probe specification (*.ltx) from prebuilt folder.
- Add VIO signals to dashboard.
- Set radix for "fm_*" signals to unsigned integer.
- "fm_*" shows some clk frequencies (unit Hz). Note: inaccurate Reference CLK is used for frequency measurement.
- "WDI_EN" and "WDI_HIT_*_EN_CLK" enables FPGA watchdog control.
- Force WD to system reboot:
- Check on Hardware window VIO status is ok. (right click on vio symbol and click "commit output values to VIO core" for update).
- Enable one of the "WDI_HIT_*_EN_CLK" signals
- Enable "WDI_EN"
- To force system to reboot, disable WDI_HIT clocks.
System Design - Vivado
Block Design
R Variant:
PS Interfaces
Typ | Note |
---|---|
DDR | |
QSPI | MIO |
SD0 | MIO |
I2C0 | MIO |
I2C1 | MIO |
UART0 | MIO |
GPIO0 | MIO |
SWDT0 | |
TTC0..1 | |
ETH00 | MIO |
USB0 | MIO |
PL-PS IRQ |
Constrains
Basic module constrains
# # Common bitgen related settings # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] #set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
# # Set unused pin pullup: PULLNONE, PULLUP, PULLDOWN # set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] #set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] #set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDONE [current_design]
Design specific constrain
set_property PACKAGE_PIN F16 [get_ports {FPGA_IO[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {FPGA_IO[0]}] set_property PACKAGE_PIN H15 [get_ports {WDI_EN[0]}] set_property IOSTANDARD LVCMOS25 [get_ports {WDI_EN[0]}] set_property PACKAGE_PIN R15 [get_ports {WD_HIT[0]}] set_property IOSTANDARD LVCMOS25 [get_ports {WD_HIT[0]}]
Software Design - SDK/HSI
For SDK project creation, follow instructions from:
Application
Source location: \sw_lib\sw_apps
zynqmp_fsbl
TE modified 2018.2 FSBL. Xilinx default FSBL on default setup. eMMC selection with FSBL possible.
Changes:
- Optional define for eMMC selection with FSBL (default SD selected)
- uncomment #define USE_EMMC on fsbl_hooks.c to select eMMC instead of SD
- See: fsbl_hooks.c, main.c
zynqmp_fsbl_flash
TE modified 2018.2 FSBL
Changes:
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0729
Hello TE0729 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
For PetaLinux installation and project creation, follow instructions from:
Config
No changes.
U-Boot
Change platform-top.h
#include <configs/platform-auto.h> #define CONFIG_SYS_BOOTM_LEN 0xF000000 #define DFU_ALT_INFO_RAM \ "dfu_ram_info=" \ "setenv dfu_alt_info " \ "image.ub ram $netstart 0x1e00000\0" \ "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" #define DFU_ALT_INFO_MMC \ "dfu_mmc_info=" \ "set dfu_alt_info " \ "${kernel_image} fat 0 1\\\\;" \ "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \ "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0" /*Required for uartless designs */ #ifndef CONFIG_BAUDRATE #define CONFIG_BAUDRATE 115200 #ifdef CONFIG_DEBUG_UART #undef CONFIG_DEBUG_UART #endif #endif /*Define CONFIG_ZYNQ_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */ #ifdef CONFIG_ZYNQ_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */ #define CONFIG_SYS_I2C_MUX_ADDR 0x74 #define CONFIG_SYS_I2C_MUX_EEPROM_SEL 0x4 #endif
Device Tree
Note: for R assembly variant, remove ETH1, ETH2 and RTC
/include/ "system-conf.dtsi" / { }; /* QSPI PHY */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* ETH PHY */ &gem0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { compatible = "marvell,88e1510"; device_type = "ethernet-phy"; reg = <0>; }; }; }; /* AXI ETH PHY0 */ &axi_ethernetlite_0 { local-mac-address = [00 0a 35 00 22 02]; phy-handle = <&phy1>; xlnx,has-mdio = <0x1>; mdio { #address-cells = <1>; #size-cells = <0>; phy1: phy@1 { device_type = "ethernet-phy"; reg = <1>; }; }; }; /* AXI ETH PHY1 */ &axi_ethernetlite_1 { local-mac-address = [00 0a 35 00 22 03]; phy-handle = <&phy2>; xlnx,has-mdio = <0x1>; mdio { #address-cells = <1>; #size-cells = <0>; phy2: phy@1 { device_type = "ethernet-phy"; reg = <1>; }; }; }; /* RTC */ &i2c0 { rtc@6F { // Real Time Clock compatible = "isl12022"; reg = <0x6F>; }; }; /* USB PHY */ /{ usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; //compatible = "usb-nop-xceiv"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { dr_mode = "host"; //dr_mode = "peripheral"; usb-phy = <&usb_phy0>; };
Kernel
Activate:
- RTC_DRV_ISL12022 (Not needed for R assembly variant, remove)
Rootfs
Activate:
- i2c-tools
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Additional Software
No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | Authors | Description |
---|---|---|---|
| |||
2018-07-13 | v.1 |
| |
All |
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