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The Trenz Electronic TEB0724-01 is a developement carrier board for the TE0724 and compatible modules. It facilitates easy access to all on the module available features.
Table 1: TE0724-01 main components.
Not programmed.
Storage device name | Content | Notes |
---|---|---|
FTDI Configuration EEPROM U3 | Empty | Not programmed. |
Table 2: Initial delivery state of programmable devices on the baseboard.
The boot device is selected by the mode jumpers on pin header J6. Placing a jumper at pin 13-14 sets Mode0 to low level. Mode1 is set to low level by jumper on over pin 15-16. Boot modes are further described at the corresponding section of the modules, e.g. Table 2, Boot mode selection of TE0724 TRM. Default with no jumpers is boot from SD-Card.
I/O signals connected to the B2B connector:
B2B Connector | Interfaces | Count of IO's | Notes |
---|---|---|---|
J1 | User IO | 72 single ended or 36 differential | 9x Pmod |
6 LED | red | ||
2 Push Button | - | ||
7 MIO | J7 (not assembled), TE0724: 3.3V | ||
2 MIO | J9 (not assembled), TE0724: 1.8V | ||
1 MIO LED | green | ||
1 MIO Push Button | - | ||
I²C | 2 | 1x Pmod | |
SD IO | 7 | - | |
UART | 2 | - | |
CAN | 2 | - | |
GbE PHY_MDIO + PHY_LEDs | 10 | - | |
JTAG | 4 | - | |
Power GPIO | 2 | - | |
Power/Reset/Fuse programming | 3 | - | |
Bootmode | 2 | - |
Table 3: General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.
The TEB0724 carrier board supplies the attached module with 5V DC. All power rails on the module and the baseboard are generated from this at the module and routed back the carrier. For detailed information about the pin out, please refer to the Pin-out Tables.
There is no device with JTAG port on the baseboard. JTAG access to the module is provided through B2B connector J1. This is routed to the carriers USB to JTAG/UART bridge.
JTAG Signal | B2B Connector Pin |
---|---|
TCK | J1-147 |
TDI | J1-151 |
TDO | J1-145 |
TMS | J1-149 |
Table 4: JTAG interface signals.
Pin Name | Function | Routed to | B2B Connector Pin | Note |
---|---|---|---|---|
Mode0 | bootdevice selection | jumper pins J6-13 J6-14 | J1-4 | TE0724: pulled up at module |
Mode1 | bootdevice selection | jumper pins J6-15 J6-16 | J1-2 | TE0724: pulled up at module |
ONKEY | module power signal | push button S1 and pin J6-9 | J1-148 | TE0724: pulled up at module |
RESETREQ | module reset | push button S3 and pin J6-12 | J1-150 | TE0724: pulled up at module |
PWR_GPIO2 | - | J6-8 | J1-143 | User power sequenzing IO |
PWR_GPIO4 | - | J6-10 | J1-141 | User power sequenzing IO |
Table 5: System Control I/O pins.
Connected To | Signal Name | Notes |
---|---|---|
J1-34 | SD-CD | Card detect switch, pulled up, low if card inserted. |
J1-24 | SD-D0 | |
J1-22 | SD-CMD | |
J1-20 | SD-CCLK | |
J1-26 | SD-D1 | |
J1-28 | SD-D2 | |
J1-30 | SD-D3 |
Table 6: SD Card interface signals and connections.
The TEB0724 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J3) with two LEDs. On-board Ethernet MagJack pins are routed to B2B connector J1 via MDI. LEDs are also routed to the B2B connector.
Ethernet PHY connection
MagJack | Signal | B2B |
---|---|---|
J3-2 | PHY_MDI0_P | J1-7 |
J3-3 | PHY_MDI0_N | J1-9 |
J3-4 | PHY_MDI1_P | J1-13 |
J3-5 | PHY_MDI1_N | J1-15 |
J3-6 | PHY_MDI2_P | J1-19 |
J3-7 | PHY_MDI2_N | J1-21 |
J3-8 | PHY_MDI3_P | J1-25 |
J3-9 | PHY_MDI3_N | J1-27 |
J3B | PHY_LED0 | J1-10 |
J3C | PHY_LED1 | J1-12 |
Table 7: Ethernet MagJack
On-board I2C bus is accaessable with the following pins:
SDA | SCL | Notes |
---|---|---|
J1-144 | J1-142 | B2B |
J6-7 | J6-5 | In-Circuit Programming |
J21-10, J21-4 | J21-9, J21-3 | Pmod |
Table 8: I2C pins.
There are no I2C devices on the base board. Pullup resistors have to be provided by the module.
The GPIOs of the 10 Pmods (J10 to J17, J20, J21) are connected with 100 Ohm differential routing to the B2B connector. J21 is a pure I2C compatible Pmod, without additional signals. The other 9 are GPIO Pmods where despite J20 all others can be used as dual Pmods. By default VCCIO_35 is connected with a 0 Ohm resistor to 3.3V. De-soldering this resistor and using not fitted pin header J19 instead, the variable bank power VCCIO_35 for the Pmods J10, J11, J12, J13, J14, J16 can be selected.
J10 | J11 | J12 | J13 | J14 | J15 | J16 | J17 | J20 | J21 | |||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
PIN | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B | Signal | B2B |
1 | PA0_P | J1-56 | PB2_N | J1-70 | PC2_P | J1-57 | PD2_P | J1-77 | PE2_N | J1-90 | PG2_N | J1-110 | PF2_P | J1-97 | PH2_P | J1-115 | PI2_P | J1-133 | NC | - |
2 | PA0_N | J1-58 | PB2_P | J1-72 | PC2_N | J1-55 | PD2_N | J1-75 | PE2_P | J1-92 | PG2_P | J1-112 | PF2_N | J1-95 | PH2_N | J1-113 | PI2_N | J1-131 | NC | - |
3 | PA3_P | J1-46 | PB0_N | J1-76 | PC0_P | J1-51 | PD0_P | J1-71 | PE0_N | J1-96 | PG0_P | J1-114 | PF0_P | J1-91 | PH0_P | J1-111 | PI0_P | J1-129 | I2C_SCL | J1-142 |
4 | PA3_N | J1-48 | PB0_P | J1-78 | PC0_N | J1-49 | PD0_N | J1-69 | PE0_P | J1-98 | PG0_N | J1-116 | PF0_N | J1-89 | PH0_N | J1-109 | PI0_N | J1-127 | I2C_SDA | J1-144 |
5 | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - |
6 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 |
7 | PA1_N | J1-62 | PB3_P | J1-68 | PC3_N | J1-59 | PD3_N | J1-79 | PE3_P | J1-88 | PG3_P | J1-108 | PF3_N | J1-99 | PH3_N | J1-117 | PI3_N | J1-135 | NC | - |
8 | PA1_P | J1-60 | PB3_N | J1-66 | PC3_P | J1-61 | PD3_P | J1-81 | PE3_N | J1-86 | PG3_N | J1-106 | PF3_P | J1-101 | PH3_P | J1-119 | PI3_P | J1-137 | NC | - |
9 | PA2_N | J1-52 | PB1_P | J1-82 | PC1_N | J1-45 | PD1_N | J1-65 | PE1_P | J1-102 | PG1_N | J1-120 | PF1_N | J1-85 | PH1_N | J1-105 | PI1_N | J1-123 | I2C_SCL | J1-142 |
10 | PA2_P | J1-50 | PB1_N | J1-80 | PC1_P | J1-47 | PD1_P | J1-67 | PE1_N | J1-100 | PG1_P | J1-121 | PF1_P | J1-87 | PH1_P | J1-107 | PI1_P | J1-125 | I2C_SDA | J1-144 |
11 | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - | GND | - |
12 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | VCCIO_35 | J1-54 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 | 3.3V | J1-74, J1- 43 |
Table 9: Pmod connections.
The TEB0724 carrier board has on-board microUSB 2.0 (J4) high-speed to UART/FIFO IC FT2232H (U1) from FTDI. Channel A can be used as JTAG Interface (MPSSE) to program on module JTAG devices. Channel B can be used as UART Interface routed to via a level shifter to the 1.8V section of the B2B connector, usually connected to the PS of the SoM. There is also a 256-byte serial EEPROM connected to the FT2232H chip pre-programmed with license code to support Xilinx programming tools.
Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.
The CAN bus is routed to screw terminal J2.
PIN | Signal | B2B |
---|---|---|
J2-1 | CAN0_N | J1-1 |
J2-2 | GND | |
J2-3 | CAN0_P | J1-3 |
Table 10: CAN bus connection.
Jumpers on J22-1 to J22-3 and J22-2 to J22-4 connect proper split termination resistors to the CAN bus.
The module has the following reference clock signals provided by on-board oscillators:
Clock Source | Schematic Name | Frequency | Clock Destination |
---|---|---|---|
SiTime SiT8008AI oscillator, U4 | OSCI | 12.000000 MHz | U1, pin 3. |
Table 11: Reference clock signals.
LED | Color | Signal | Description and Notes |
---|---|---|---|
D1 | green | VIN | power indicator |
D2-D7 | red | ULED1..6 | User LED |
D8 | green | MIO9 | MIO user LED |
J3B | green | PHY_LED0 | Ethernet status |
J3C | yellow | PHY_LED1 | Ethernet status |
Table 12: On-board LEDs.
Button | Signal | B2B | Description and Notes |
---|---|---|---|
S1 | ONKEY | J1-148 | Power Button, pulled up, on push de-asserted |
S3 | RESETREQ | J1-150 | User LED pulled up, on push de-asserted |
S2 | S2 | J1-124 | PL user button, pulled up, on push de-asserted |
S4 | S4 | J1-126 | PL user button, pulled up, on push de-asserted |
S5 | MIO51 | J1-42 | PS MIO user button, pulled up, on push de-asserted |
Table 13: On-board Push Buttons.
Pin Header J6 provides access to power functions, bootmode selection and PMIC In-Circuit Programming.
PIN | Signal | B2B |
---|---|---|
J6-1 | VIN | J1-154, J1-156, J1-158, J1-160 |
J6-2 | VIN | J1-154, J1-156, J1-158, J1-160 |
J6-3 | GND | |
J6-4 | GND | |
J6-5 | I2C_SCL | J1-142 |
J6-6 | VBAT | J1-152 |
J6-7 | I2C_SDA | J1-144 |
J6-8 | PWR_GPIO2 | J1-143 |
J6-9 | ONKEY | J1-148 |
J6-10 | PWR_GPIO4 | J1-141 |
J6-11 | PWR_TP | J1-146 |
J6-12 | RESETREQ | J1-150 |
J6-13 | MODE0 | J1-2 |
J6-14 | GND | |
J6-15 | MODE1 | J1-4 |
J6-16 | GND |
Table 14: Pin Header J6.
For voltage selection VCCIO_35 (SoM TE0724, Bank 35) other than 3.3V the header J19 can optionaly assembled. Therefore 0 Ohm resistor R45 has to be removed!
PIN | Signal | B2B |
---|---|---|
J19-1 | VLDO1 | J1-83 |
J19-2 | GND | |
J19-3 | VCCIO_35 | J1-54 |
J19-4 | VLDO2 | J1-94 |
J19-5 | VLDO34 | J1-53 |
J19-6 | GND |
Table 15: Optional Pin Header J19.
Optional fitted headers J7, J8 and J9 are to provide full access to the Pins at the B2B connector, especially for testing and extension purposes. Description follows below.
PL Button and LED IOs are additionally routed to optionally assembled pin header J8.
PIN | Signal | B2B |
---|---|---|
J8-1 | 3.3V | J1-43, J1-74 |
J8-2 | GND | |
J8-3 | S4 | J1-126 |
J8-4 | S2 | J1-124 |
J8-5 | ULED5 | J1-130 |
J8-6 | ULED6 | J1-128 |
J8-7 | ULED3 | J1-134 |
J8-8 | ULED4 | J1-132 |
J8-9 | ULED1 | J1-138 |
J8-10 | ULED2 | J1-136 |
Table 16: Optional Pin Header J8.
Optional pin header J7 gives access to otherwise not used PS MIO IOs at a 3.3V bank.
PIN | Signal | B2B |
---|---|---|
J7-1 | 3.3V | 43, 74 |
J7-2 | GND | |
J7-3 | GND | |
J7-4 | MIO8 | J1-14 |
J7-5 | MIO10 | J1-31 |
J7-6 | MIO11 | J1-33 |
J7-7 | MIO12 | J1-35 |
J7-8 | MIO13 | J1-37 |
J7-9 | MIO14 | J1-39 |
J7-10 | MIO15 | J1-41 |
Table 17: Optional Pin Header J7.
Optional pin header J9 gives access to otherwise not used PS MIO IOs at a 1.8V bank.
PIN | Signal | B2B |
---|---|---|
J9-1 | 1.8V | J1-63 |
J9-2 | GND | |
J9-3 | GND | |
J9-4 | MIO_46 | J1-32 |
J9-5 | MIO_50 | J1-40 |
J9-6 | MIO_PB | J1-42 |
Table 18: Optional Pin Header J9.
The maximum power consumption depends on the attached module the design running on the module and additional peripherals.
Xilinx provide a power estimator excel sheets to calculate power consumption for FPGAs. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.
Power Input | Typical Current |
---|---|
VIN | TBD* |
Table 19: Typical power consumption.
* TBD - To Be Determined soon with reference design setup.
Power supply with minimum current capability of 3A for system startup is recommended.
User should also check related module documentation and Xilinx data sheet, respectively.
The power-on sequence is solely controlled by the attached module. Optional sequenzing signals for integration of additional hardware are PWR_GPIO2 and PWR_GPIO4. If the attached module uses the adjustable bank power VCCIO_35, this has to be powered up after the modules SOCs powerrails are up and before any other signal is applied to the bank IOs. The 1.8V and 3.3V power rails are used for the SD Card level shifter U13. The datasheet states to first power up 1.8V and then 3.3V, this has to be taken into account when reconfiguring the power circuit of the attached SoM.
Power Rail Name | B2B J1 Pins | Direction on B2B | Notes |
---|---|---|---|
VIN | 154, 156, 158, 160 | Output | External main supply voltage. |
3.3V | 43, 74 | Input | |
1.8V | 63 | Input | |
VCCIO_35 | 54 | Output | |
VLDO1 | 83 | Input | |
VLDO2 | 94 | Input | Used to enable UART level shifter. Therefore fix at 1.8V. |
VLDO34 | 53 | Input | |
VBAT | 152 | Input/Output | Reserved for PMIC backup battery and charger. |
Table 20 : Board power rails.
The TEB0724 base board has a 160-pin double-row REF-192552-01 connector on the top side.
Order | REF Number | Samtec Number | Type | Mated Height | Data sheet | Comment |
---|---|---|---|---|---|---|
- | REF-192552-01 | SS5-80-3.50-L-D-K-TR | Baseboard connector | 4 mm | http://suddendocs.samtec.com/catalog_english/ss5.pdf | Standard connector used on board |
27220 | REF-192552-02 | ST5-80-1.50-L-D-P-TR | Module connector | 4 mm | http://suddendocs.samtec.com/catalog_english/st5.pdf | Standard connector used on module |
Table 21: Connectors for module and base board.
Trenz shop TEB0724 overview page | |
---|---|
English page |
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | -0.3 | 5.5 | V | Depends mostly on attached SoM, values here are for TE0724 PMIC, da9062_3v4.pdf. |
Storage temperature | -30 | 80 | °C | Push buttons datasheet. |
Table 20: Board absolute maximum ratings.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN supply voltage | 0 | 5.5 | V | Depends mostly on attached SoM, values here are for TE0724 PMIC, da9062_3v4.pdf. |
Operating temperature | -25 | 70 | °C | Push buttons datasheet. |
Table 21: Board recommended operating conditions.
Commercial grade: 0°C to +70°C.
Extended grade: 0°C to +85°C.
Industrial grade: -40°C to +85°C.
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Module size: 105 mm × 100 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 4 mm.
PCB thickness: 1.6 mm.
Highest part on PCB: approx. 13.5 mm. Please download the step model for exact numbers.
All dimensions are given in millimeters.
Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
- | 01 | Prototypes |
Table 22: Module hardware revision history.
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Date | Revision | Contributors | Description |
---|---|---|---|
| |||
v.23 | John Hartfiel |
| |
2018-07-10 | v.19 |
|
Table 23: Document change history.
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