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The Trenz Electronic TEF1002-02 is a baseboard in PCIe x1 form factor. It is a carrier for Trenz Electronic 4 x 5 SoMs, refer to page 4 x 5 SoM Carriers for more information about the SoMs supported by this carrier.
It hosts a FPGA Mezzanine Card (FMC LPC), a SFP+, CRUVI HS, RJ45 Ethernet and SATA socket. A USB OTG port and a JTAG/IO bridge together with additional JTAG headers and a System Controller complete this development platform.
Refer to https://trenz.org/tef1002-info for current online available documentation.
Storage device name | Designator | Content | Notes |
|---|---|---|---|
System Controller | U11 | Firmware | For further information see TEF1002 CPLD Firmware / TEF1002 SC CPLD MAX10. |
EEPROM | U6 | Programmer configuration | Do not overwrite! |
Connector Type | Designator | Interface | IO count | Notes |
|---|---|---|---|---|
B2B | JB3 | MGT SATA | 1x MGT (RX/TX) | |
SATA | J31 | MGT SATA | 1x MGT (RX/TX) | |
B2B | JB3 | MGT PCIe x1 | 1x MGT (RX/TX) | |
B2B | JB3 | MGT PCIe x1 | 1x MGT CLK | |
PCIe x1 slot | J3 | MGT PCIe x1 | 1x MGT (RX/TX) | |
PCIe x1 slot | J3 | MGT PCIe x1 | 1x MGT CLK | |
B2B | JB3 | MGT SFP+ | 1x MGT (RX/TX) | |
SFP+ | J12 | MGT SFP+ | 1x MGT (RX/TX) | |
B2B | JB3 | MGT FMC | 1x MGT (RX/TX) | |
B2B | JB3 | MGT FMC | 1x MGT CLK | |
B2B | JB3 | IO FMC | 12x SE/ 6x DIFF | |
B2B | JB3 | IO FMC CLK | 2x DIFF | |
B2B | JB2 | IO FMC | 56x SE/ 28x DIFF | |
FMC LPC | J1 | MGT FMC | 1x MGT (RX/TX) | |
FMC LPC | J1 | MGT FMC | 1x MGT CLK | |
FMC LPC | J1 | IO FMC | 12x SE/ 6x DIFF | |
FMC LPC | J1 | IO FMC CLK | 2x DIFF | |
FMC LPC | J1 | IO FMC | 56x SE/ 28x DIFF | |
B2B | JB1 | SDIO | 6x SE | |
MicroSD card | J8 | SDIO | 6x SE | |
B2B | JB1 | IO CRUVI | 24x SE / 12x DIFF | |
CRUVI HS | J11 | IO CRUVI | 24x SE / 12x DIFF | |
B2B | J1 | JTAG SC | 4x SE | |
Pin header 2.54 mm | J19 | JTAG SC | 4x SE | |
B2B | JB1 | ETH MDI | 4x DIFF | |
RJ45 | J9 | ETH MDI | 4x DIFF | |
B2B | JB1 | UART | 2x SE | |
Micro USB type B | J10 | JTAG / UART / IO | 1x DIFF | |
B2B | JB3 | USB OTG | 1x DIFF | |
Micro USB type B | J16 | USB OTG | 1x DIFF | |
Pin header 2.54 mm | J5 | JTAG / UART / Reset | 7x SE |
Test Point | REV03 | REV02 Signal | Notes | ||
|---|---|---|---|---|---|
Top | Bottom | Signal | |||
TP1 | x | 5V0 | |||
TP2 | x | 3V3_PER | Not used | ||
TP3 | x | DDR_PWR | |||
TP4 | x | 3V3IN | |||
TP5 | x | PG_3V3FMC | Not used | ||
TP6 | x | VREF_JTAG | |||
TP7 | x | VCCIOA | |||
TP8 | x | U10.PG | Not used | ||
TP9 | x | M3.3VOUT | |||
TP10 | x | M1.8VOUT | |||
TP11 | x | PSBATT | FMC_VADJ | ||
TP12 | x | 5V0 | Not used | ||
TP13 | x | USR_DIFIO1_N | Not used | ||
TP14 | x | USR_DIFIO1_P | Not used | ||
TP15 | x | 12V | |||
TP16 | x | VADJ_CRUVI | Not used | ||
TP17 | x | M3.3VOUT | |||
TP18 | x | FMC_VADJ | |||
TP19 | x | 3V3FMC | |||
TP20 | x | VCCA_SD | |||
TP21 | x | 3.3V_SD | |||
TP22 | x | 3.3V_SD | Not used | ||
TP23 | x | FMC_VADJ | Not used | ||
TP24 | x | U9.PGOOD | Not used | ||
TP25 | x | 3V3_PER | |||
TP26 | x | PG_VADJ_CRUVI | Not used | ||
TP27 | x | 3V3FMC | Not used | ||
TP28 | x | VADJ_CRUVI | Not used | ||
TP29 | x | 3V3IN | Not used | ||
TP30 | x | PSBATT | Not used | ||
TP31 | x | 12V | Not used | ||
TP32 | x | 12V_FAULTn | Not used | ||
TP33 | x | PG_FMC_VADJ | Not used | ||
TP34 | x | 5V_FAN | Not used | ||
TP35 | x | 5V_FAN | Not used | ||
TP36 | x | M1.8VOUT | Not used | ||
TP37 | x | VCCA_SD | Not used | ||
Chip / Interface | Designator | Connected to | Notes |
|---|---|---|---|
System Controller | U11 |
| For further information see TEF1002 CPLD Firmware / TEF1002 SC CPLD MAX10. |
USB 2.0 bridge | U4 |
| |
EEPROM Programmer Configuration | U6 |
| Do not overwrite! |
Oscillator | U7 |
| 12 MHz |
Control signals represent hardware defined logic states, for final state consider the firmware and reference designs.
Signal Name | Connector.Pin | Direction 1) | Description 2) |
|---|---|---|---|
EN1 | JB1.27 | OUT | Enable SoM power. |
PGOOD | JB1.29 | IN | Power Good signal for monitoring SoM voltages. |
MODE | JB1.31 | OUT | SoM Boot Mode selection. |
NOSEQ | JB1.8 | OUT | Influence SoM System Controller power management. |
VBUS_V_EN / USB-VBUS | JB3.54 / JB3.56 | IN / OUT | USB OTG VBUS control signals. |
RESIN | JB2.17 | OUT | Reset signal to SoM. |
M10_RST | J5.6 | IN | Reset System Controller. |
M_JTAGEN | JB1.90 | OUT | Select SoM JTAG target. |
UART ( UART_RX / UART_TX ) | JB1.86 / JB1.91 | Signal dependent | SoM UART. |
JTAG ( M_TMS / M_TDI / M_TDO / M_TCK ) | JB2.94 / JB2.96 / JB2.98 / JB2.100 | Signal dependent | SoM JTAG. |
JTAG ( TCK / TDO / TMS / TDI ) | J5.1 / J5.3 / J5.5 / J5.9 | Signal dependent | JTAG System Controller. |
UART ( M10_TX / M10_RX ) | J5.7 / J5.8 | Signal dependent | UART System Controller. |
JTAG ( PJTAG_TCK / PJTAG_TDO / PJTAG_TDI / PJTAG_TMS ) | J19.1 / J19.2 / J19.3 / J19.4 | Signal dependent | JTAG SoM. |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
2) Refer to TEF1002 SC CPLD MAX10 for further information.
Jumper header | Net name / Connector.pin | Notes | |
|---|---|---|---|
Output | Input | ||
J4 | M3.3VOUT / J4.1 | Set voltage for SoM IO. | |
VCCIOA / J4.2 | |||
M1.8VOUT / J4.3 | |||
J7 | M3.3VOUT / J7.1 | Set voltage for SDIO. | |
VCCA_SD / J7.2 | |||
M1.8VOUT / J7.3 | |||
Button | Signal | Voltage level | Function | |
|---|---|---|---|---|
Low | high | |||
S1 | BUTTON | pressed | unpressed | Manual reset signal for SoM. |
DIP switch group | DIP switch | Signal name / Connector.pin | Description |
|---|---|---|---|
| S2A | VID0 / S2.1 | Set voltage FMC_VADJ, refer to TEF1002 CPLD Firmware - FMC VADJ Power for further information. |
S2B | VID1 / S2.2 | ||
S2C | VID2 / S2.3 | ||
S2D | JTAGEN / S2.4 | Muxing of JTAG signals, refer to TEF1002 CPLD Firmware - JTAG MUX for further information. | |
S2E | M_JTAGEN / S2.5 | ||
S2F | FMC_JTAG / S2.6 | ||
S2G | CM0 / S2.7 | Set SoM control signals, refer to TEF1002 CPLD Firmware - Module control for further information. | |
S2H | CM1 / S2.8 | ||
| S3A | CM2 / S3.A | |
S3B | USR0 / S3.B | User definable signal |
Power Rail Name / Schematic Name | Connector.Pin | Description | Notes |
|---|---|---|---|
12V_input_A | J15.1 / J15.2 / J15.3 | Carrier supply via PCIe 6 pin connector. | |
M3.3VOUT | JB2.9 / JB2.11 | Auxiliary IO supply input from SoM. | |
M3.3VOUT | J1E.D32 / J4.1 / J7.1 | Auxiliary IO Supply output from SoM. | |
M3.3VOUT | J19.6 | Supply for external IO/JTAG device. | |
M1.8VOUT | J4.3 / J7.3 | Auxiliary IO Supply output from SoM. | |
PSBATT | J6.2 | Backup supply input. | SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
M1.8VOUT | JB1.40 | Auxiliary IO Supply from SoM. | SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
VREF_JTAG | JB2.92 | JTAG IO voltage. | SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
DDR_PWR | JB2.20 | SoM DDR voltage reference. | SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
5V0 | JB1.2 / JB1.4 / JB1.6 / JB2.1 / JB2.3 / JB2.5 / JB2.7 | SoM supply | |
VCCIOA | JB1.10 / JB1.12 | SoM IO bank supply | |
PSBATT | JB1.80 | SoM backup supply | |
FMC_VADJ | JB2.2 / JB2.4 / JB2.6 / JB2.8 / JB2.10 / J1E.G39 / J1E.H40 | SoM FMC voltage supply. | |
3V3IN | JB1.14 / JB1.16 J5.4 | JTAG IO voltage reference. |
1) Direction:
Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
|---|---|---|---|---|---|
0 | - | - | - | Configuration SoM signal setup. | |
1 | VIN | 11.4 V to 12.6 V | - | Apply Main Carrier supply. |
These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.
4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.
When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height
| Order number | Connector on baseboard | compatible to | Mating height |
|---|---|---|---|
| 23836 | REF-189016-01 | LSHM-150-02.5-L-DV-A-S-K-TR | 6.5 mm |
| LSHM-150-03.0-L-DV-A-S-K-TR | LSHM-150-03.0-L-DV-A-S-K-TR | 7.0 mm | |
| 23838 | REF-189016-02 | LSHM-150-04.0-L-DV-A-S-K-TR | 8.0 mm |
| LSHM-150-06.0-L-DV-A-S-K-TR | LSHM-150-06.0-L-DV-A-S-K-TR | 10.0mm | |
| 26125 | REF-189017-01 | LSHM-130-02.5-L-DV-A-S-K-TR | 6.5 mm |
| LSHM-130-03.0-L-DV-A-S-K-TR | LSHM-130-03.0-L-DV-A-S-K-TR | 7.0 mm | |
| 24903 | REF-189017-02 | LSHM-130-04.0-L-DV-A-S-K-TR | 8.0 mm |
| LSHM-130-06.0-L-DV-A-S-K-TR | LSHM-130-06.0-L-DV-A-S-K-TR | 10.0mm |
The module can be manufactured using other connectors upon request.
The LSHM connector speed rating depends on the stacking height; please see the following table:
| Stacking height | Speed rating |
|---|---|
| 12 mm, Single-Ended | 7.5 GHz / 15 Gbps |
| 12 mm, Differential | 6.5 GHz / 13 Gbps |
| 5 mm, Single-Ended | 11.5 GHz / 23 Gbps |
| 5 mm, Differential | 7.0 GHz / 14 Gbps |
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).
| File | Modified | |
|---|---|---|
| PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File lshm_dv.pdf LSHM catalog page | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189016-01.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189016-02.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189017-01.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189017-02.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File tc0929--2611_qua(1).pdf Shock and vibration report | Apr 07, 2016 by Thorsten Trenz | |
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Warning!
The listed values ONLY reflect this board. Connected Carriers / SoMs / Boards are not considered.
Power Rail Name / Schematic Name | Description | Min | Max | Unit | Notes |
|---|---|---|---|---|---|
12V_input_A | Carrier supply via PCIe 6 pin connector. | -25 | +25 | V | |
M3.3VOUT | Auxiliary IO Supply from SoM. | -0.3 | 6.3 | V | |
M1.8VOUT | Auxiliary IO Supply from SoM. | - | - | V | SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
VREF_JTAG | JTAG IO voltage. | -0.5 | 3.9 | V | SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
PSBATT | Backup supply input | - | - | V | SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
DDR_PWR | SoM DDR voltage reference. | - | - | V | SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.
The categories are:
These categories do not take into account the entire custom system consisting of:
The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.
The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).
Parameter | Min | Max | Units | Reference Document |
|---|---|---|---|---|
12V_input_A | 11.4 | 12.6 | V | Schematic |
M3.3VOUT | 3.201 | 3.399 | V | Schematic |
M1.8VOUT | 1.746 | 1.854 | V | SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
VREF_JTAG | 1.0 | 3.465 | V | MAX10 FPGA datasheet. SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
PSBATT | - | - | V | SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
DDR_PWR | - | - | V | SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs . |
Module size: 98.4 mm x 167.65 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8.0 mm.
| Trenz shop TEF1002 overview page | |
|---|---|
| English page | German page |
The hardware revision number can be found on the PCB board together with the module's model number, separated by a dash.
Date | Revision | Changes | Documentation Link |
|---|---|---|---|
2025-09 | 03 |
| |
2019-12 | 02 |
| |
2019-05 | 01 |
|
| Date | Revision | Contributor | Description |
|---|---|---|---|
| |||
2025-10-20 | v.35 | Maksim Tserabei |
|
| 2020-01-29 | v.28 | Martin Rohrmüller |
|
| 2019-09-06 | v.25 | Martin Rohrmüller |
|
-- | all |
|
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
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