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The Trenz Electronic TE0720 is an industrial-grade SoM (System on Module) based on AMD Zynq-7000 SoC with DDR3/DDR3L SDRAM, SPI flash memory, Gigabit Ethernet PHY transceiver, USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via high-speed stacking connections.
Refer to http://trenz.org/te0720-info for current online available documentation.
Power Supervisor with Watchdog Timer
Storage device name | Content | Notes |
|---|---|---|
| System Controller, U19 | standard firmware | Visit TE0720 CPLD Firmware for further information. |
| eMMC, U15 | not programmed | |
SPI Flash, U7 | not programmed | |
| 2 kBit EEPROM, U17 | not programmed besides factory programmed MAC address |
| Connector Type | Designator | Interface | IO CNT | Notes |
|---|---|---|---|---|
| B2B | JM1 | HR IO | 48 | |
| B2B | JM1 | PS IO | 6 | Bank 501 voltage level is 1.8 V. SDIO or optional MIO (MIO40/.../MIO45). |
| B2B | JM1 | PS IO | 4 | Bank 500 voltage level is 3.3 V (MIO0/MIO9/MIO12/MIO13). |
| B2B | JM1 | UART | 2 | Bank 500/SC Bank 2 voltage level is 3.3 V. UART or MIO (MIO14/MIO15). |
| B2B | JM1 | I2C | 2 | Bank 500 voltage level is 3.3 V . I²C or optional MIO (MIO10/MIO11). |
| B2B | JM1 | VBat | 1 | |
| B2B | JM1 | ETH MDI | 8 | |
| B2B | JM2 | HR IO | 50 | |
| B2B | JM2 | HR IO | 18 | |
| B2B | JM2 | JTAG | 4 | |
| B2B | JM3 | ETH MDI | 4 | |
| B2B | JM3 | USB OTG | 3 | |
| B2B | JM3 | USB OTG VBus | 2 | |
| B2B | JM3 | HR IO | 36 |
| Test Point | Signal | Notes |
|---|---|---|
| TP1 | 1V | |
| TP2 | VIN | |
| TP3 | 1.5V | |
| TP4 | 1.8V | |
| TP5 | VTT | |
| TP6 | VTTREF | |
| TP7 | 3.3VIN | |
| TP8 | 3.3V | |
| TP9 | VCCIO13 | |
| TP10 | VCCIO33 | |
| TP11 | VCCIO34 | |
| TP12 | VCCIO35 | |
| TP13 | AVCC | |
| TP14 | AVREF | |
| TP15 | AGND | |
| TP16 | GND | |
| TP17 | GND | |
| TP18 | GND | |
| TP19 | GND | |
| TP20 | GND | |
| TP21 | PS-RST | |
| TP22 | PROG_B | |
| TP23 | PS-CLK | |
| TP24 | PS-CS | |
| TP25 | SPI-SCK/M4 | |
| TP26 | SPI-DQO/MO | |
| TP27 | SPI-DQ3/M3 | |
| TP28 | SPI-DQ2/M2 | |
| TP29 | SPI-DQ1/M1 | |
| TP30 | VBATT | |
| TP31 | PS-POR-B | |
| TP32 | PS-RST |
| Chip/Interface | Designator | Connected to | Notes |
|---|---|---|---|
SoC | U5 |
| |
RAM | U12, U13 |
| |
Quad SPI | U7 |
| |
e.MMC | U15 |
| |
USB 2.0 ULPI PHY | U18 |
| |
ETH PHY | U8 |
| |
SC | U19 |
| Visit TE0720 CPLD Firmware for further information. |
MAC EEPROM | U17 |
| Contains pre-programmed globally unique 48-bit node address. |
RTC Real time clock | U20 |
| Battery backed functionality via VBat pin. I²C adresses: Registers 0x6F/RAM 0x57. |
Crypto Element | U10 |
| |
eCompass | U22 |
| I²C adresses: 0x1D |
Power Supervisor | U26 |
| |
Power Supervisor | U27 |
| |
Oscillator | U6 |
| 33.3 MHz |
Oscillator | U14 |
| 25 MHz |
Oscillator | U9 |
| 52 MHz |
| Signal Name | Connector.Pin | Direction1) | Description |
|---|---|---|---|
| NOSEQ | JM1.7 | INOUT | Module Power management 2) 3) 4). |
| EN1 | JM1.28 | IN | Power enable signal 2) 3) 4). |
| PGOOD | JM1.30 | INOUT | Power good and/or Boot mode select signal 2) 4) |
| MODE | JM1.32 | IN | Boot mode select signal 2) 3) 4). |
| JTAGMODE | JM1.89 | IN | Select JTAG target on the SoM 2) 3) 4). |
| RESIN | JM2.18 | IN | Reset signal 4). |
VBUS_V_EN | JM3.53 | OUT | Enables USB Host Bus Voltage |
| USB-VBUS | JM3.55 | IN | Detects USB Host Bus Voltage |
| MIO14/MIO15 | JM1.92 / JM1.85 | INOUT | UART to SoC and SC 2) |
| MIO10/MIO11 | JM1.95 / JM1.93 | INOUT | I²C SoC to B2B |
| X5 / X7 | U5C.P22 / U5C.N22 U19D.J1 / U19D.M1 | INOUT | I²C SC to SoC |
| SDA / SCL | U22.6 / U22.4 U20.12 / U20.11 U10.1 U16C.P7 / U16C.P8 | INOUT | I²C SC to RTC, eCompass and Crypto Element |
1) Direction:
2) Firmware dependent. Refer to TE0720 CPLD Firmware for further information.
3) Do not leave floating.
4) For more information refer to 4 x 5 SoM Integration Guide.
| Power Rail Name / Schematic Name | Connector.Pin | Direction 1) | Note |
|---|---|---|---|
| VIN | JM1.1 / JM1.3 / JM1.5 / JM2.4 / JM2.4 / JM2.6 / JM2.8 | IN | Supply voltage from carrier. |
| 3.3VIN | JM1.13 / JM1.15 | IN | Supply voltage from carrier. |
| 3.3VIN / VREF_JTAG | JM2.91 | OUT | JTAG reference voltage. |
| VCCIO13 | JM2.7 / JM2.9 | IN | SoC IO Bank supply from carrier. |
| VCCIO33 | JM2.5 | IN | SoC IO Bank supply from carrier. |
| VCCIO34 | JM2.1 / JM2.3 | IN | SoC IO Bank supply from carrier. VCCIO34 must be connected to power even if this bank is not used. |
| VCCIO35 | JM1.9 / JM1.11 | IN | SoC IO Bank supply from carrier. |
| VBAT_IN | JM1.79 | IN | RTC battery buffer supply |
| 3.3V | JM2.10 / JM2.12 | OUT | |
| 1.8V | JM1.39 | OUT | |
| 1.5V 2) | JM2.19 | OUT |
1) Direction:
2) For SoM variants with DDR3L RAM, this voltage is reduced to 1.35 V. On these variants, resistor R39 has a value of 120 kΩ instead of 100 kΩ for 1.5 V variants.
| Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
|---|---|---|---|---|---|
| 1 | - | - | - | Configuration signal setup. | |
3.3VIN VIN | - 1) | - - | Main Power supply. | ||
| 2 | EN1 | 3.3 V (± 5 %) | - 2) | Enable SoM.3) |
|
| 3 | 3.3V or 1.8V | - 1) | - | Module generated output voltages. | SoM's internal power-on sequence is complete when these voltages reach their nominal values. |
| 4 | VCCIO35 | - 1) | - | Supply module bank voltages. 4) | |
| 5 | PGOOD | 3.3 V (± 5 %) | - 3) | SoM power good signal. | All power sources are stable. |
1) Refer to Recommended Operating Conditions.
2) Firmware dependent. Refer to TE0720 CPLD Firmware for further information.
3) Do not assert signal before input power supply reached 90 % of nominal value.
4) VCCIO34 needs to be connected to power even if bank is not used, to setup startup parameters.
For more information refer to DS187.
These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.
4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.
When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height
| Order number | Connector on baseboard | compatible to | Mating height |
|---|---|---|---|
| 23836 | REF-189016-01 | LSHM-150-02.5-L-DV-A-S-K-TR | 6.5 mm |
| LSHM-150-03.0-L-DV-A-S-K-TR | LSHM-150-03.0-L-DV-A-S-K-TR | 7.0 mm | |
| 23838 | REF-189016-02 | LSHM-150-04.0-L-DV-A-S-K-TR | 8.0 mm |
| LSHM-150-06.0-L-DV-A-S-K-TR | LSHM-150-06.0-L-DV-A-S-K-TR | 10.0mm | |
| 26125 | REF-189017-01 | LSHM-130-02.5-L-DV-A-S-K-TR | 6.5 mm |
| LSHM-130-03.0-L-DV-A-S-K-TR | LSHM-130-03.0-L-DV-A-S-K-TR | 7.0 mm | |
| 24903 | REF-189017-02 | LSHM-130-04.0-L-DV-A-S-K-TR | 8.0 mm |
| LSHM-130-06.0-L-DV-A-S-K-TR | LSHM-130-06.0-L-DV-A-S-K-TR | 10.0mm |
The module can be manufactured using other connectors upon request.
The LSHM connector speed rating depends on the stacking height; please see the following table:
| Stacking height | Speed rating |
|---|---|
| 12 mm, Single-Ended | 7.5 GHz / 15 Gbps |
| 12 mm, Differential | 6.5 GHz / 13 Gbps |
| 5 mm, Single-Ended | 11.5 GHz / 23 Gbps |
| 5 mm, Differential | 7.0 GHz / 14 Gbps |
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).
| File | Modified | |
|---|---|---|
| PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File lshm_dv.pdf LSHM catalog page | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189016-01.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189016-02.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189017-01.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File REF-189017-02.pdf Technical Drawing | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report | Apr 07, 2016 by Thorsten Trenz | |
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| PDF File tc0929--2611_qua(1).pdf Shock and vibration report | Apr 07, 2016 by Thorsten Trenz | |
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This TRM is generic for all variants.
Variants of modules are described here: Article Number Information. Please contact us to inquire options.
| Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
|---|---|---|---|---|
| VIN | Supply voltage from carrier. | -0.3 | 6 | V |
| 3.3VIN | Supply voltage from carrier. | -0.5 | 3.6 | V |
| VCCIO13 | SoC IO Bank supply from carrier. | -0.5 | 3.6 | V |
| VCCIO33 | SoC IO Bank supply from carrier. | -0.5 | 3.6 | V |
| VCCIO34 | SoC IO Bank supply from carrier. | -0.5 | 3.6 | V |
| VCCIO35 | SoC IO Bank supply from carrier. | -0.5 | 3.6 | V |
| VBAT_IN | RTC battery buffer supply. | -0.3 | 6 | V |
*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
This TRM is generic for all variants. Temperature range can be different in dependence to the assembly variant. The voltage ranges should not be affected by assembly variants (exceptions are possible, depending on custom request).
Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.
The categories are:
These categories do not take into account the entire custom system consisting of:
This SoM is capable of being operated at industrial-grade temperatures, which cover at least the range of -40 °C to 85 °C.
The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components.
The Operating temperature range depends also on customer design and cooling solution. Consult Cooling Solutions for more information.
| Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
|---|---|---|---|---|
| VIN | Supply voltage from carrier. | 3.15 | 5.25 | V |
| 3.3VIN | Supply voltage from carrier. | 3.15 | 3.45 | V |
| VCCIO13 | SoC IO Bank supply from carrier. | 1.14 | 3.465 | V |
| VCCIO33 | SoC IO Bank supply from carrier. | 1.14 | 3.465 | V |
| VCCIO34 | SoC IO Bank supply from carrier. | 1.425 | 3.465 | V |
| VCCIO35 | SoC IO Bank supply from carrier. | 1.14 | 3.465 | V |
| VBAT_IN | RTC battery buffer supply. | 2.5 | 5.0 | V |
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.6 mm ±10 %.
All dimensions are given in millimeters.

| Trenz shop TE0720 overview page | |
|---|---|
| English page | German page |
The hardware revision number is on the PCB adjacent to the module identifier, separated by a dash.
| Date | Revision | Changes | Documentation Links |
|---|---|---|---|
| 2022-03 | 04 | 1. Revised power supply circuit, replaced next components: 14. Added note regarding VCCIO34, page B2B-Connectors | |
| 2015-01 | 03 | 1. Bootmode is now latched on Reset 2. Fixed Xilinx "AR# 65240" . Added supervisor TPS3106K33DBVR (U26) according to Xilinx recommendations. 7. Change eMMC from MTFC32GAKAECN-3M to IS21ES32G-JCLI 8. Change DDR3 RAM (U12, U13) from IM4G16D3FABG-125I to IS43TR16256BL-125KBLI Firmware changes: 22. Change eMMC (U15) from IS21ES08G-JCLI / IS21ES32G-JCLI to SDINBDG4-8G-XI2 / SDINBDG4-32G-XI2 | PCN-202106 |
| 2014-09 | 02 | 1. JTAG only boot mode is now supported 2. Winbond W25Q256FV SPI Flash memory replaced with Spansion S25FL256 3. Texas Instruments TPS51200 Sink/Source DDR Termination Regulator replaced with TPS51206 4. Changed MDIO pullup from 10k to 4k7 5. Changed eMMC core supply from switched 3.3Vout to 3.3Vin 6. MAC EEPROM power changed from 3.3V to 1.8V 7. I²C Multiplexing no longer needed (to select between RTC and MEMS), all I2C devices are on the same bus. 8. ST LSM303DLM (e-compass: 3D accelerometer and 3D magnetometer) MEMS is no longer assembled in standard assembly variants 9. Removed test pads on top layer 10. Increased component clearance from mounting holes on bottom layer 11. System Controller in-system programming via B2B JTAG pins 12. JM1 pin 89 has new function that enables System Controller JTAG Chain no impact for old designs that connect this pin to GND | |
| - | 01 | Prototypes | REV01 |
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Date | Revision | Contributors | Description |
|---|---|---|---|
| |||
2025-05-23 |
| ||
| 2025-05-13 | v.104 | Kilian Jahn |
|
| 2021-11-15 | v.95 | John Hartfiel |
|
| 2021-06-21 | v.93 | Mohsen Chamanbaz |
|
| 2019-02-05 | v.92 | John Hartfiel |
|
2018-07-05 | v.89 | John Hartfiel |
|
| 2017-11-10 | v.85 | John Hartfiel |
|
| 2017-09-07 | v.84 | John Hartfiel |
|
| 2017-08-31 | v.83 | Jan Kumann |
|
-- | all |
|
Table 25: Document change history table.
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