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Overview

The Trenz Electronic TE0803 is an industrial grade MPSoC SOM integrating an AMD Zynq UltraScale+, DDR4 SDRAM with 64-Bit width data bus connection, SPI Boot Flash memory for configuration and operation, transceivers (SoC/Variant-dependent) and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking connections in a compact 5.2 cm x 7.6 cm form factor.

Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.

Key Features

  • SoC
    • Device: ZU1 / ZU2 / ZU3 / ZU4 / ZU5 1)
    • Engine: CG / EG / EV 1)
    • Speedgrade: -1 / -1L / -2 / -2L / -3 1)
    • Temperature Range: Extended / Industrial 1)
    • Package: SFVC784
  • RAM/Storage
    • 4 GByte DDR4 SDRAM 2) 3)
    • 2 x 64 MByte Serial Flash 3)
    • EEPROM with MAC address
  • On Board
    • Clock Generator
    • Oscillator
  • Interface
    • 4 x B2B Connector (ST5)
      • up to 204 PL IO

        • HP: 156
        • HD: 0 / 48  3)
      • up to 65 PS MIO

      • 4 GTR
      • 4 GTH (with ZU3T, ZU4 and higher)
      • I2C, JTAG, CONFIG
  • Power
    • 3.3 V power supply via B2B Connector needed 5).
  • Dimension
    • 76 mm x 52 mm
  • Notes
    1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
    2) Up to 8 GByte are possible with a maximum bandwidth of 2400 MBit/s.
    3) Please, take care of the possible assembly options.
    5) Dependent on the assembly option a higher input voltage may be possible.

Block Diagram

TE0808 block diagram

Main Components

TE0803 main components
  1. SoC, U1
  2. DDR4, U2, U3, U9, U12
  3. Quad SPI Flash, U7, U17
  4. Connector, J1, J2, J3, J4
  5. EEPROM, U28
  6. Clock Generator, U5
  7. Oscillator, U6, U32
  8. Done LED D1

Initial Delivery State

Storage device name

Content

Notes

Quad SPI Flash

not programmed


EEPROMnot programmed besides factory programmed MAC address
DDR4 SDRAMnot programmed
Programmable Clock Generatornot programmed
Initial delivery state of programmable devices on the module

Signals, Interfaces and Pins

Connectors

Connector TypeDesignatorInterfaceIO CNTNotes
B2BJM1MGT PLup to 4 x MGT (RX/TX)Assembly option dependent.
B2BJM1HP52 SE / 24 DIFF
B2BJM2MGT PS2 x MGT CLK
B2BJM2CLK2 x DIFF CLKPLL, 1 x Input, 1 x Output
B2BJM2MGT PS4 x MGT (RX/TX)
B2BJM2CFG1)1x JTAG
B2BJM2CFG1)4x MODE
B2BJM2CFG1)1 x I2CPLL, EEPROM
B2BJM2CFG1)29 CTRL/Status
B2BJM3HDup to 48 SE / 24 DIFFAssembly option dependent.
B2BJM3MGT PLMGT CLK
B2BJM3MIO65 GPIO
B2BJM4HP104 SE / 48 DIFF

1) see Configuration and System Control Signals

Board Connectors


Test Points

Test PointSignalNotes1)
TP1PLL_SCLpulled-up to PS_1V8
TP2PLL_SDApulled-up to PS_1V8
TP3GND
TP4GND
TP5GND
TP6PL_1V8
TP7GND
TP8GND
TP9PL_VCCINT_IO
TP10GND
TP11PL_VCCINT
TP12PL_VCU_0V9
TP13FP_0V85
TP14PS_1V8
TP15GND
TP16DDR_2V5
TP17DDR_PLL
TP18DDR_1V2
TP20MGTAVTT
TP21VTT
TP22PL_GT_1V05
TP23VREFA
TP24MGTVCCAUX
TP25MGTAVCC
TP27PS_PLL
TP28PS_AVTT
TP29LP_0V85
TP30PS_AUX
TP31PS_AVCC
TP32PS_CLK
TP34POR_Bpulled-up to PS_1V8

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Test Points Information

On-board Peripherals

Chip/InterfaceDesignatorConnected ToNotes

DDR4 SDRAM

U2, U3, U9, U12SoC - PS

Quad SPI Flash

U7, U17SoC - PSBooting.

EEPROM

U28B2B - J2

Clock Generator

U5B2B - J2
SoC -MGT

Oscillator

U6Clock Generator25 MHz

Oscillator

U32SoC33.333333 MHz
On board peripherals

Configuration and System Control Signals

Connector+Pin

Signal Name

Direction1)Description
J2-82PG_PSGTOUTGTR transceivers powered-up.
J2-83MRINManual reset.
J2-84EN_PSGTINEnable GTR transceiver power-up.
J2-86ERR_STATUSOUTPS error status 2).
J2-88ERR_OUTOUTPS error indication 2).
J2-90PLL_SCLINI2C clock. Pulled up to PS_1V8.
J2-91PG_GT_ROUTRight GTH Transceivers powered-up.
J2-92PLL_SDAIN/OUTI2C data. Pulled up to PS_1V8.
J2-95EN_GT_RINEnable right GTH transceiver power-up.
J2-96SRST_BINSystem reset 2). Pulled-up to PS_1V8.
J2-97PG_VCUOUTVCU powered-up.
J2-98INIT_BIN/OUTInitialization completion indicator after POR 2). Pulled-up to PS_1V8.
J2-100PROG_BIN/OUTPower-on reset 2). Pulled-up to PS_1V8.
J2-101EN_PLINEnable programable logic power-up.
J2-102EN_FPDINEnable full-power domain power-up.
J2-103 / J2-105 / J2-107 / J2-109MODE3..0INBoot mode selection 2):
  • JTAG
  • QUAD-SPI (32 Bit)
  • SD1 (2.0)
  • eMMC (1.8 V)
  • SD1 LS (3.0)

Supported Modes depends also on used Carrier.

J2-104PG_PLOUTProgrammable logic powered-up. Pulled-up to PL_DCIN.
J2-106LP_GOODOUTLow-power domain powered-up. Pulled up to LP_DCDC.
J2-108EN_LPDINEnable low-power domain power-up.
J2-110PG_FPDOUTFull-power domain powered-up. Pulled-up to DCDCIN.
J2-112EN_DDRINEnable DDR power-up.
J2-114PG_DDROUTDDR power supply powered-up. Pulled-up to DCDCIN.
J2-116DONEOUTPS done signal 2). Pulled-up to PS_1V8.
J2-119 / J2-121DX_P / DX_N-SoC temperatur sensing diode pins 2).
J2-120 / J2-122 /
J2-124 / J2-126
TCK / TDI / TDO / TMSSignal-dependent

JTAG configuration and debugging interface.

JTAG reference voltage: PS_1V8

J2-125PSBATTINPS RTC Battery supply voltage 2) 3).
J2-127PUDC_BINConfiguration pull-ups setting 2). Pulled-up to PL_1V8.

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.

2) See UG1085 for additional information.

3) See Recommended Operating Conditions.

Controller signal.

Power and Power-On Sequence

Power Rails

Power Rail Name/ Schematic NameConnector + PinDirection1)Notes
VCCO_66J1-90 / J1-120IN
VREF_66J1-108IN

PL_1V8

J1-91 / J1-121OUT
PL_DCINJ1-151 / J1-153 / J1-155 / J1-157 / J1-159IN
LP_DCDCJ2-138 / J2-140 / J2-142 / J2-144IN
DCDCINJ2-153 / J2-154 / J2-155 / J2-156 / J2-157 / J2-158 / J2-159 / J2-160IN
PS_1V8J2-99 / J3-147 / J3-148OUT
PS_BATTJ2-125IN
DDR_1V2J2-135OUT
VCCO_25J3-15 / J3-16IN
VCCO_26J3-43 / J3-44IN
GT_DCDCJ3-157 / J3-158 / J3-159 / J3-160IN
VCCO_64J4-58 / J4-106IN
VREF_64J4-88IN
VCCO_65J4-69 / J4-105IN
VREF_65J4-15IN

1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Module power rails.

Recommended Power up Sequencing


SequenceNet nameRecommended Voltage RangePull-up/downDescriptionNotes
0---Configuration signal setup.See Configuration and System Control Signals.
1 1)PSBATT1.2 V ... 1.5 V-Battery connection.Battery Power Domain usage. When not used, tie to GND.
2Processing System (PS):

Procedure for PS starting.
2.1Low-power domain:Bring-up for low-power domain PS.
2.1.1LP_DCDC3.3 V (± 5 %) 2)-Low-power domain power supply.Main module power supply for low-power domain. 5.5 A recommended. Power consumption depends mainly on design and cooling solution.
2.1.2EN_LPD--Low-power domain power enable.
2.1.3LP_GOOD-PU 3), LP_DCDCLow-power domain power good status.Module power-on sequencing for low-power domain finished.
2.2Full-power domain:Bring-up for full-power domain PS.Full-power PS domain needs powered low-power PS domain.
2.2.1DCDCIN3.3 V (± 5 %) 2)
Full-power domain and GTR transceiver power supply.Main module power supply for full-power domain. 7 A recommended. Power consumption depends mainly on design and cooling solution.
2.2.2EN_FPDDCDCIN-Full-power domain power enable.
2.2.3PG_FPD-PU 3), DCDCINFull-power domain power good status.Module power-on sequencing for full-power domain finished.
2.2.4EN_DDRDCDCIN-DDR memory power enable.
2.2.5PG_DDR-PU 3), DCDCINDDR memory power good status.Module power-on sequencing for DDR memory finished.

2.3

GTR TransceiverProcedure for GTR transceiver starting.PS transceiver usage needs powered PS (low- and full-power domain).
2.3.1EN_PSGTDCDCIN-GTR transceiver power enable.
2.3.2PG_PSGT--GTR transceiver power good status.Module power-on sequencing for GTR transceiver finished.
2Programmable Logic (PL)Procedure for PL starting.PL usage needs powered PS low-power domain.
2.1PL_DCIN3.3 V (± 5 %) 2)-Programmable logic power supply.Main module power supply for programmable logic. 12 A recommended. Power consumption depends mainly on design and cooling solution.
2.2EN_PL-PU 3), PL_DCINProgrammable logic power enable.
2.3PG_PL-PU 3), PL_DCINProgrammable logic power good status.Module power-on sequencing for programmable logic finished. Periphery and variable bank voltages can be enabled on carrier.
2.4PG_VCU-PU 3), PL_DCINVideo codec unit power good status.Assembly variant dependent.
2.5VCCO_25 / VCCO_26 / VCCO_64 / VCCO_65 / VCCO_66 4)-Module bank voltages.Enable bank voltages after PG_PL deassertion.
3GTH / GTY TransceiverProcedure for GTH / GTY transceiver starting.PL transceiver usage needs powered PL and low-power PS domain.
3.1GT_DCDC3.3 V (± 5 %) 2)-GTH transceiver power supply.Main module power supply for GTH transceiver. 5 A recommended. Power consumption depends mainly on design and cooling solution.
3.2EN_GT_RGT_DCDC-GTH right transceiver power enable.
3.3PG_GT_R--GTH transceiver power good status.
4MR

Manual ResetLow active release after all needed power domains are enabled. 

1) Optional

2) Dependent on the assembly option a higher input voltage may be possible. 

3) On module

4) See DS925 for additional information.

Baseboard Design Hints

Board to Board Connectors

5.2 x 7.6 cm UltraSoM+ modules use four Samtec Razor Beam LP Terminal Strip (ST5) on the bottom side.
  • 4x REF-192552-02 (160-pins)
    • ST5 Mates with SS5

5.2 x 7.6 cm UltraSoM+ carrier use four Samtec Razor Beam LP Socket Strip (SS5) on the top side.

  • 4x REF192552-01 (160-pins)
    • SS5 Mates with ST5
Features
  • Board-to-Board Connector 160-pins, 80 contacts per row
  • Ultrafine .0197" (0.50 mm) pitch
  • Narrow body design saves space on board
  • Lead style -03.5
  • Samtec 28+ Gbps Solution
  • Mates with: ST5
  • Insulator Material: Liquid Crystal Polymer, schwarz
  • Operating Temperature Range: -55°C bis +125°C
  • Lead-Free Solderable: Yes
  • RoHS Konform: Yes


Connector Stacking height

When using the standard type on baseboard and module, the mating height is 5 mm.

Other mating heights are possible by using connectors with a different height:

Order numberREF numberSamtec NumberTypeContribution to stacking heightComment
27219REF192552-01SS5-80-3.50-L-D-K-TRBaseboard connector3.5mm

Standard connector used on carrier

27018REF-189545-02 SS5-80-3.00-L-D-K-TRBaseboard connector3 mm 

Assembly option on request

27220REF-192552-02 ST5-80-1.50-L-D-P-TRModule connector1.5 mm

Standard connector used on modules

27017REF-189545-01 ST5-80-1.00-L-D-P-TRModule connector1 mm

Assembly option on request

Connectors.


The module can be manufactured using other connectors upon request.

Current Rating

Current rating of Samtec Razor Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 1.5 A per pin (1 pin powered per row).

Connector Speed Ratings

The connector speed rating depends on the stacking height:

Stacking height

Speed rating

4 mm, Single-Ended13GHz/26Gbps
4 mm, Differential13.5GHz/27Gbps
5 mm, Single-Ended13.5GHz/27Gbps
5 mm, Differential20GHz/40 Gbps
Speed rating.

The SS5/ST5 series board-to-board spacing is currently available in 4mm (0.157"), 4.5mm (0.177") and 5mm (0.197") stack heights.

The data in the reports is applicable only to the 4mm and 5mm board-to-board mated connector stack height.

Manufacturer Documentation

  File Modified
PDF File hsc-report-sma_st5-ss5-04mm_web.pdf 30 05, 2017 by Susanne Kunath
PDF File hsc-report-sma_st5-ss5-05mm_web.pdf 30 05, 2017 by Susanne Kunath
PDF File REF-192552-01.pdf 13 11, 2017 by John Hartfiel
PDF File REF-192552-02.pdf 13 11, 2017 by John Hartfiel
PDF File ss5.pdf 13 11, 2017 by John Hartfiel
PDF File ss5-st5.pdf 13 11, 2017 by John Hartfiel
PDF File ss5-xx-x.xx-x-d-k-tr-mkt.pdf 13 11, 2017 by John Hartfiel
PDF File st5.pdf 13 11, 2017 by John Hartfiel
PDF File st5-xx-x.xx-x-d-p-tr-mkt.pdf 13 11, 2017 by John Hartfiel


Technical Specifications

Absolute Maximum Ratings *)

Power Rail Name/ Schematic NameDescriptionMinMaxUnit
LP_DCDCMicromodule Power-0.3004.0V
DCDCINMicromodule Power-0.3006.5V
GT_DCDCMicromodule Power-0.3006.0V
PL_DCINMicromodule Power-0.300

4.0

V
PS_BATTRTC / BBRAM-0.5002.000V
VCCO_25HD IO Bank power supply-0.5003.400V
VCCO_26HD IO Bank power supply-0.5003.400V
VCCO_64HP IO Bank power supply-0.5002.000V

VCCO_65

HP IO Bank power supply-0.5002.000V
VCCO_66HP IO Bank power supply-0.5002.000V
VREF_64Bank input reference voltage-0.5002.000V
VREF_65Bank input reference voltage-0.5002.000V
VREF_66Bank input reference voltage-0.5002.000V
Absolute maximum ratings

*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
   or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version.  Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

  • Variants of modules are described here: Article Number Information
  • Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
  • Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
  • Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
  • The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.


ParameterMinMaxUnitsReference Document
LP_DCDC 1)3.1353.465V
DCDCIN 1)3.1353.465V
GT_DCDC 1)3.1353.465V
PL_DCIN 1)3.135

3.465

V
PS_BATT1.2001.500VSee FPGA datasheet.
VCCO_251.1403.400VSee FPGA datasheet.
VCCO_261.1403.400VSee FPGA datasheet.
VCCO_640.9501.900VSee FPGA datasheet.

VCCO_65

0.9501.900VSee FPGA datasheet.
VCCO_660.9501.900VSee FPGA datasheet.
VREF_640.61.2VSee FPGA datasheet.
VREF_650.61.2VSee FPGA datasheet.
VREF_660.61.2VSee FPGA datasheet.

1) Higher values may possible. For more information consult schematic and according datasheets.

Recommended operating conditions.


Physical Dimensions

  • Module size: 76 mm × 52 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm.

PCB thickness: 1.740 mm (± 10 %).

Physical Dimension

Currently Offered Variants 

Trenz shop TE0803 overview page
English pageGerman page
Trenz Electronic Shop Overview

Revision History

Hardware Revision History

Board hardware revision number.


DateRevisionChangesDocumentation Link
2020-12-1504
  • Revised PL_VCCINT power supply. EN63A0QI replaced by TPS548A28RWWR. PCB: revised routing and components placement;
  • Added support of wide SDRAM DDR4 packages. PCB: revised routing and components placement;
  • Added option to select POR_OVERRIDE level (R12 and R93)
  • VCCO pins for unused Bank 44 connected together. Same for unused Bank 24 (UG583 recomendation)
  • PCB: updated signal trace lengths.
  • PCB: updated silkscreen. Added company address, CE and WEEE symbols;
  • PCB: added module orientation rectangle pointer
  • Changed resistor values of R29, R31, R35, R39, R44-R47 (BOM optimization)
  • Removed traceability part (Obsolete component)
  • Changed capacitor C92 for all variants from 100 nF to 1 nF.
  • U4 can be either TPS548A28RWWR or MPQ8633BGLE-Z which is up to Trenz Electronic GmbH.
TE0803-04
2019-03-1803
  • Added support of DDP DDR4
  • Added support of Low power FPGA (-L1/L2).
  • Revised testpoints
  • Revised J1-J4 connectors net label style
TE0803-03
2018-07-1902
  • Added LDO to DDR_PLL
  • All differential pairs length matched with tollerance 0.1mm (excluding package delays)
  • Added MAC EEPROM U28
  • VPS_MGTRAVCC set to 0.85V
  • Added pull-up resistors R68, R69
TE0803-02
2016-12-2301First production releaseTE0803-01
Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

DateRevisionContributorDescription

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  • Review and publishing
2024-10-15


V.56

KJ

  • Repaired DrawIO objects "Main Components" and "Physical Dimensions"

2023-10-06

v.52

ED

  • Updated to new TRM style
  • Updated for REV04

2022-05-19

v.51

ED

  • Added note regarding DCDC U4.
2022-02-25


v.50


John Hartfiel


  • Add Note to PLL
2022-02-08v.46John Hartfiel
  • Correction on Power section
  • Correction GTH Clock connection
2021-05-17v.41John Hartfiel
  • typo correction in DDR section
2021-03-11v.40John Hartfiel
  • typo
  • fixed MGT Lanes RX/TX order
2019-07-15v.36John Hartfiel
  • correction SPLL section
2019-07-02v.35John Hartfiel
  • add eeprom section
  • update PCB Revision section
2019-06-19v.33John Hartfiel
  • update links
  • correction flash section

2018-08-20

v.29John Hartfiel
  • power section: add missing PS_1V8 output pin

2018-08-06

v.28John Hartfiel
  • typo correction
2017-11-13v.23Ali Naseri
  • updated B2B connector max. current rating per pin

2017-11-13

v.19

John Hartfiel
  • rework B2B section
2017-10-19

v.18

John Hartfiel
  • Removed ES1 Note
2017-08-15v.17Vitali Tsiukala
  • Changed Signals Count in the table B2B-connectors

2017-08-07

v.14

Jan Kumann
  • New smaller images.
  • New QSPI Flash MIO mapping table.
  • Temperature information changes.
  • Few corrections.

2017-05-17

V.4


Ali NaseriCurrent TRM release.
2017-05-10v.1Ali NaseriInitial document.

--

all

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  • --
Document change history.

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Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

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Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

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To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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Ambiguous method overloading for method jdk.proxy244.$Proxy3578#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]


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