TE0865 Test Board

Overview

Design Example with Petalinux.

Refer to http://trenz.org/te0865-info for the current online version of this manual and other available documentation.

Key Features

• Vitis/Vivado 2023.2
• Linux
• DDR PS and PL
• USB (with CPLD Firmware REV03)
• ETH
• MAC from EEPROM
• SD
• I2C
• QSPI
• Modified FSBL
  

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and usage of the reference design, see Project Delivery - AMD devices

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0865 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   _create_win_setup.cmd/_create_linux_setup.sh

   ------------------------Set design paths----------------------------
   -- Run Design with: _create_win_setup
   -- Use Design Path: <absolute project path>
   --------------------------------------------------------------------
   -------------------------TE Reference Design---------------------------
   --------------------------------------------------------------------
   -- (0)  Module selection guide, project creation...prebuilt export...
   -- (1)  Create minimum setup of CMD-Files and exit Batch
   -- (2)  Create maximum setup of CMD-Files and exit Batch
   -- (3)  (internal only) Dev
   -- (4)  (internal only) Prod
   -- (c)  Go to CMD-File Generation (Manual setup)
   -- (d)  Go to Documentation (Web Documentation)
   -- (g)  Install Board Files from Xilinx Board Store (beta)
   -- (a)  Start design with unsupported Vivado Version (beta)
   -- (x)  Exit Batch (nothing is done!)
   ----
   Select (ex.:'0' for module selection guide):

2. Press 0 and enter to start "Module Selection Guide"
3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
   

   • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note: Select correct one, see also Vivado Board Part Flow

4. Create hardware description file (.xsa file) and export to prebuilt folder

   run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")

   TE::hw_build_design -export_prebuilt

   Using Vivado GUI is the same, except file export to prebuilt folder.

5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the "<plnx-proj-root>/images/linux" directory

6. (Optional) Configure the boot.scr file as needed, see Distro Boot with Boot.scr

7. Generate Programming Files with Vitis (recommended)
   1. Copy PetaLinux build image files to prebuilt folder

      • copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
        

        "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

   2. Generate Programming Files with Vitis
      run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")

      TE::sw_run_vitis -all
      TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

8. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select create and open delivery binary folder

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   run on Vivado TCL (Script programs BOOT.bin on QSPI flash)

   TE::pr_program_flash -swapp hello_te0865

SD-Boot mode

1. Copy image.ub, boot.scr and Boot.bin on SD
   
   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)

3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

   Note: See TRM of the Carrier, which is used.

   Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
   The boot options described above describe the common boot processes for this hardware; other boot options are possible.
   For more information see Distro Boot with Boot.scr

4. Power On PCB

   boot process

   1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

   2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

   3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

Linux

1. Open Serial Console (e.g. putty)
   
   • Speed: 115200

   • select COM Port

     Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

2. Linux Console:
   

   # password disabled
   

   Note: Wait until Linux boot finished

3. You can use Linux shell now.
   

   i2cdetect -y -r 0	(check I2C 0 Bus)
   dmesg | grep rtc	(RTC check)
   udhcpc				(ETH0 check)
   lsusb				(USB check)

4. Optional Features

   • Webserver to get access to ZynqMP
     • insert IP on web browser to start web interface
   • init.sh scripts
     • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

• Control: -
  
• Monitoring: Status of PL DDR4
  

  

  Vivado Hardware Manager

System Design - Vivado

Block Design

Block Design

PS Interfaces

Activated interfaces:

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
set_property PACKAGE_PIN G26 [get_ports diff_clock_rtl_clk_p]

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

hello_te0865

Hello TE0865 is a Xilinx Hello World example as endless loop instead of one console output.

Software Design -  PetaLinux

For PetaLinux installation and project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• select SD default instead of eMMC:
  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
• add new flash partition for bootscr and sizing
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xE00000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x3000000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
  • CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_OFFSET=0xE00000
  • CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_SIZE=0x3000000
• Identification
  • CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
  • CONFIG_SUBSYSTEM_PRODUCT="TE0865"

U-Boot

Start with petalinux-config -c u-boot

Changes:

• MAC from eeprom together with uboot and device tree settings:
  
  • CONFIG_ENV_OVERWRITE=y
  • CONFIG_NVMEM=y
  • CONFIG_DM_RTC=y    (needed for nvmem driver because of bug in uboot)
• Boot Modes:
  • CONFIG_QSPI_BOOT=y
  • CONFIG_SD_BOOT=y
  • CONFIG_ENV_IS_IN_FAT is not set
  • CONFIG_ENV_IS_IN_NAND is not set
  • CONFIG_ENV_IS_IN_SPI_FLASH is not set
  • CONFIG_BOOT_SCRIPT_OFFSET=0x3E40000
• Identification
  • CONFIG_IDENT_STRING=" TE0865"

Change platform-top.h:

#no changes

Device Tree

/include/ "system-conf.dtsi"


/*-------------------- SD0 eMMC ----------------*/
&sdhci0 {
    // 1.8V
    bus-width = <8>;
    
};

/*-------------------- SD1 sd2.0 ----------------*/
&sdhci1 {
    // 3.3V
    disable-wp;
    no-1-8-v;
};

/*-------------------- USB 2.0 only ----------------*/
&usb0 {
    status = "okay";
    clock-names = "bus_clk";
    clocks = <&zynqmp_clk USB0_BUS_REF>;
    assigned-clocks = <&zynqmp_clk USB0_BUS_REF>;
};


&dwc3_0 {
    dr_mode = "host";
};


/*------------------ ETH PHY --------------------*/
&gem3 {
    phy-handle = <&phy0>;

    nvmem-cells = <ð0_addr>;
    nvmem-cell-names = "mac-address";

    //required otherwise petalinux gives a static address here
    /delete-property/ local-mac-address;

    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};


/*-------------------- QSPI ---------------------*/
&qspi {
    num-cs = <2>;

    flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0>, <1>;
        parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 2* 16MB --> dummy for all types of this QSPI type */

        spi-rx-bus-width = <4>;
        spi-tx-bus-width = <4>;
        spi-max-frequency = <166000000>; //166MHz max. frequency
        
        #address-cells = <1>;
        #size-cells = <1>;
    };
};


/*------------------ I2C --------------------*/
&i2c0 {

    // needs a special wakeup sequence, i2c-detect and similar will not work
    // https://github.com/Infineon/optiga-trust-m/
    // optiga: optiga@30 {
    //     compatible = "";
    //     reg = <0x30>;
    // };

    //MAC EEPROM
    eeprom: eeprom@53 {
        compatible = "microchip,24aa025", "atmel,24c02";
        reg = <0x53>;
            
            #address-cells = <1>;
            #size-cells = <1>;
            eth0_addr: eth-mac-addr@FA {
              reg = <0xFA 0x06>;
            };
        };

    //not tested
    //ltm4700@5a {
    //    compatible = "lltc,ltm4700";
    //    reg = <0x5a>;
    //    regulators {
    //        vout0 {
    //            regulator-name = "FPGA-0.85V_VCCINT";
    //        };
    //        vout2 {
    //            regulator-name = "FPGA-0.85V_VCCINT";
    //        };
    //    };
    //};    
    
    // needs a special wakeup sequence, i2c-detect and similar will not work
    // crypto: crypto@60 {
    //     compatible = "atmel,atecc508a", "atmel,atecc608a";
    //     reg = <0x60>;
    // };        

};

Kernel

Start with petalinux-config -c kernel

Changes:

• Only needed to fix JTAG Debug issue:
  
  • CONFIG_CPU_FREQ is not set

Rootfs

Start with petalinux-config -c rootfs

Changes:

• For web server app:
  • CONFIG_busybox-httpd=y
• For additional test tools only:
  • CONFIG_i2c-tools=y
  • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
• For auto login:
  • CONFIG_imagefeature-serial-autologin-root=y

FSBL patch (alternative for vitis fsbl trenz patch)

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

Boot.scr patch

Petalinux template with Trenz debug log prints, see "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\u-boot"

Enabled USB voltage via I2C (SC_EXT_2 output signal from CPLD):

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for ZynqMP access. Need busybox-httpd

Additional Software

No additional software is needed.

Appx. A: Change History and Legal Notices

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