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The TE0960 is a development board for AMD Versal AI Edge Gen 2 SoCs which supports three LPDDR5 chips, UFS storage and QSPI flash. It supports a M.2 M key device, a microSD card, two Ethernet PHYs via RJ45 connectors and offers three USB Type C for high speed data exchange, DisplayPort over USB, High Speed Debug Port and USB 2.0/OTG.
Additional IOs are accessible via SFC / FPC connectors, Pmods and pin headers. It offers a PWM Fan header for cooling and multiple DIP switches, buttons and LEDs.
Refer to https://trenz.org/te0960-info for current online available documentation.
Notes
1) Only on SoC 35xx variants
Storage device name | Designator | Content | Notes |
|---|---|---|---|
SoC | U1 | Not programmed | |
UFS | U15 | Not programmed | |
QSPI Flash | U22 | Not programmed | |
TPM 2.0 | U44 | Firmware by the manufacturer. | |
Programmable PLL | U42 | Programmed - I2C overwriting possible | OUT0 : 156¼ MHz |
EEPROM with MAC | U23 / U25 / U29 | MAC is burned-in by the manufacturer. | |
EEPROM | U6 | Not programmed | |
EEPROM | U51 | Programmer configuration. | Do not overwrite! |
Connector Type | Designator | Interface | IO count | Notes |
|---|---|---|---|---|
2x17 pin header | J1 | HDIO | 6x SE / 3x DIFF | Only on 35xx SoC variants. 3.3 V - Bank 401. |
2x17 pin header | J1 | HDIO | 14x SE / 7x DIFF | Only on 35xx SoC variants. 3.3 V - Bank 403 |
CRUVI GTX | J9 | HS / X5IO | 24x SE / 12x DIFF | Only on 35xx SoC variants. 1.2 V - Bank 706 |
FFC / FPC | J13 | X5IO | 10x SE / 5x DIFF / 5x MIPI lanes | Only on 35xx SoC variants. 1.2 V - Bank 707 |
FFC / FPC | J13 | HDIO | 2x SE | Only on 35xx SoC variants. 3.3 V - Bank 403 |
FFC / FPC | J13 | I2C / HDIO | 2x SE | Only on 35xx SoC variants. 3.3 V - Bank 403 |
FFC / FPC | J14 | X5IO | 10x SE / 5x DIFF / 5x MIPI lanes | Only on 35xx SoC variants. 1.2 V - Bank 707 |
FFC / FPC | J14 | HDIO | 2x SE | Only on 35xx SoC variants. 3.3 V - Bank 403 |
FFC / FPC | J14 | I2C / HDIO | 2x SE | Only on 35xx SoC variants. 3.3 V - Bank 403 |
Pmod | J21 | HDIO | 8x SE / 4x DIFF | Only on 35xx SoC variants. 3.3 V - Bank 401 |
Pmod | J22 | HDIO | 8x SE / 4x DIFF | Only on 35xx SoC variants. 3.3 V - Bank 401 |
USB type C | J2 | USB 3.x / MGT | 4x GTR (RX/TX) | Bank 504 |
USB type C | J2 | USB 2.0 | 1x DIFF | Bank 504 |
USB type C | J2 | USB SBU | 2x SE | Bank 504 |
USB type C | J2 | USB CC | 2x SE | Bank 504 |
| 3x pin header | J4 | FUSE programming | 1x SE | |
zSFP+ | J5 | MGT | 1x GTYP (RX/TX) | Bank 105 |
zSFP+ | J5 | I2C | 2x SE | |
RJ45 | J6 | Ethernet | 4x DIFF | |
RJ45 | J7 | Ethernet | 4x DIFF | |
USB type C | J8 | USB 2.0/MIO | 1x DIFF | |
CRUVI GTX | J9 | LS / HDIO | 8x SE | 3.3 V - Bank 401/402 1) |
CRUVI GTX | J9 | MGT | 4x GTYP (RX/TX) | Bank 203/205 |
CRUVI GTX | J9 | MGT CLK | 1x DIFF | Bank 203/205 |
CRUVI GTX | J9 | I2C / HDIO | 2x SE | 3.3 V - Bank 401/402 1) |
CRUVI GTX | J10 | HS/X5IO | 24x SE / 12x DIFF | 1.2 V - Bank 706/708 1) |
CRUVI GTX | J10 | LS / HDIO | 8x SE | 3.3 V - Bank 400 |
CRUVI GTX | J10 | I2C / HDIO | 2x SE | 3.3 V - Bank 400 |
FFC / FPC | J11 | X5IO | 10x SE / 5x DIFF / 5x MIPI lanes | 1.2 V - Bank 707/709 1) |
FFC / FPC | J11 | HDIO | 2x SE | 3.3 V - Bank 400 |
FFC / FPC | J11 | I2C / HDIO | 2x SE | 3.3 V - Bank 400 |
FFC / FPC | J12 | X5IO | 10x SE / 5x DIFF / 5x MIPI lanes | 1.2 V - Bank 707/709 1) |
FFC / FPC | J12 | HDIO | 2x SE | Bank 400 |
FFC / FPC | J12 | I2C / HDIO | 2x SE | Bank 400 |
µSD socket | J15 | SDIO | 6x SE | Bank 500 |
2x5 box header | J16 | CAN | 1x DIFF | Bank 501 |
2x5 box header | J17 | CAN | 1x DIFF | Bank 501 |
M.2 M key | U19 | PCIe | 2x GTYP (RX/TX) | Bank 105 |
4x pin header | J23 | PWM fan | GND / 12 V / Speed / PWM | |
USB type C | J24 | HSDP / MGT | 1x GTYP (RX/TX) | Bank 105 |
USB type C | J24 | JTAG | USB 2.0 | Bank 503 |
USB type C | J24 | UART | USB 2.0 | Bank 501 |
Notes
1) Bank number depends on SoC assembly variant.
Test Point | REV01 | |||
|---|---|---|---|---|
Top | Bottom | Signal | Notes | |
TP1 | x | 12V0_IN | ||
TP2 | x | 12V0_IN | ||
TP3 | x | 12V_IN_FUSED | ||
TP4 | x | 12V_IN_FUSED | ||
TP5 | x | 12V0 | ||
TP6 | x | 12V0 | ||
TP7 | x | 12V0_FAN | ||
TP8 | x | 12V0_FAN | ||
TP9 | x | 5V0 | ||
TP10 | x | 5V0 | ||
TP11 | x | 5V0_VIN_FTDI | ||
TP12 | x | 5V0_VIN_FTDI | ||
TP13 | x | 5V0_VBUS_FTDI | ||
TP14 | x | 5V0_VBUS_FTDI | ||
TP15 | x | 5V0_USB | ||
TP16 | x | 5V0_USB | ||
TP17 | x | USB2_5V0 | ||
TP18 | x | USB2_5V0 | ||
TP19 | x | 3V3_PS | ||
TP20 | x | 3V3_PS | ||
TP21 | x | 3V3_PL | ||
TP22 | x | 3V3_PL | ||
TP23 | x | 3V3_VDD_FTDI | ||
TP24 | x | 3V3_VDD_FTDI | ||
TP25 | x | 2V5 | ||
TP26 | x | 2V5 | ||
TP27 | x | V_SD_IO | ||
TP28 | x | V_SD_IO | ||
TP29 | x | 1V8 | ||
TP30 | x | 1V8 | ||
TP31 | x | 1V8_LPDDR5 | ||
TP32 | x | 1V8_LPDDR5 | ||
TP33 | x | 1V5 | ||
TP34 | x | 1V5 | ||
TP35 | x | 1V5_A | ||
TP36 | x | 1V5_A | ||
TP37 | x | 1V2 | ||
TP38 | x | 1V2 | ||
TP39 | x | 1V2_A | ||
TP40 | x | 1V2_A | ||
TP41 | x | 1V1 | ||
TP42 | x | 1V1 | ||
TP43 | x | 1V0XX_LPDDR5 | ||
TP44 | x | 1V0XX_LPDDR5 | ||
TP45 | x | 1V0 | ||
TP46 | x | 1V0 | ||
TP47 | x | 0V92 | ||
TP48 | x | 0V92 | ||
TP49 | x | 0V8_VCCRAM | ||
TP50 | x | 0V8_VCCRAM | ||
TP51 | x | VCC_LPD | ||
TP52 | x | VCC_LPD | ||
TP53 | x | VCC_FPD | ||
TP54 | x | VCC_FPD | ||
TP55 | x | VCC_SOC | ||
TP56 | x | VCC_SOC | ||
TP57 | x | VCCINT | ||
TP58 | x | VCCINT | ||
TP59 | x | VCC_AIE | ||
TP60 | x | VCC_AIE | ||
TP61 | x | 0V5_LPDDR5 | ||
TP62 | x | 0V5_LPDDR5 | ||
TP63 | x | VCC_BATT | ||
TP64 | x | VCC_BATT | ||
TP65 | x | O2 | ||
TP66 | x | O1 | ||
TP67 | x | O3 | ||
TP68 | x | SEL | ||
TP69 | x | CON_DET | ||
TP70 | x | F_UART_TX | ||
TP71 | x | F_UART_RX | ||
TP72 | x | FAULT_n | ||
Chip / Interface | Designator | Connected to | Notes |
|---|---|---|---|
SoC | U1 |
| |
QSPI Flash | U5 |
| |
LPDDR5 | U2, U3, U4 |
| |
UFS storage | U15 |
| |
µSD socket | J15 |
| |
USB 3.x port controller | U14 |
| |
Ethernet PHYs | U24 / U28 |
| |
USB 2.0/OTG PHY | U31 |
| |
USB 2.0 to JTAG/UART bridge | U49 |
| |
EEPROM | U6 |
| |
EEPROM with MAC | U23 / U25 / U29 |
| |
EEPROM for programmer | U51 |
| |
Programmable PLL | U42 |
|
|
PCIe common OSC | U22 |
| Both 100 MHz |
Oscillator | U52 |
| 12 MHz |
Oscillator | U43 |
| 24 MHz |
Oscillator | U18 |
| 26 MHz |
Oscillator | U7 |
| 26 MHz |
Oscillator | U8 |
| 33⅓ MHz |
Oscillator | U32 |
| 52 MHz |
Oscillator | U26 |
| 25 MHz |
Notes
1) Only on SoC 35xx variants
2) Bank number SoC variant dependent. 33xx / 35xx
Control signals represent hardware defined logic states, for final state consider the firmware and reference designs.
Signal Name | Connector.Pin | Direction 1) | Description |
|---|---|---|---|
GTX_EN_EXT_PWR | J9.D14 | OUT | External IO device power enable signal. |
GTX_PG_EXT_PWR | J9.D15 | IN | External IO device power good signal. |
GTX_RFU1 / GTX_RFU2 | J9.D16 / J9.C18 | - | Reserved for future use. - Can be used as IO. |
GTX_EN_EXT_PWR | J10.D14 | OUT | External IO device power enable signal. |
GTX_PG_EXT_PWR | J10.D15 | IN | External IO device power good signal. |
GTX_RFU1 / GTX_RFU2 | J10.D16 / J10.C18 | - | Reserved for future use. - Can be used as IO. |
CAN ( CAN0_N / CAN0_P ) | J16.3 / J16.4 | INOUT | |
CAN ( CAN1_N / CAN1_P ) | J17.3 / J17.4 | INOUT | |
I2C ( PLL_I2C_SDA/I2C3_SDA / PLL_I2C_SCL/I2C3_SCL ) | J20.3 / J20.1 | Signal dependent | Pay attention to REV01 patch. |
I2C ( I2C2_SDA / I2C2_SCL ) | J3.4 / J3.2 | Signal dependent | |
I2C ( GTX_SDA_LS / GTX_SCL_LS ) | J9.C20 / J9.C19 | Signal dependent | |
I2C ( CSI1_SDA / CSI1_SCL ) | J11.2 / J11.3 | Signal dependent | |
I2C ( CSI2_SDA / CSI2_SCL ) | J12.2 / J12.3 | Signal dependent | |
I2C ( CSI3_SDA / CSI3_SCL ) | J13.2 / J13.3 | Signal dependent | |
I2C ( CSI4_SDA / CSI4_SCL ) | J14.2 / J14.3 | Signal dependent | |
LEDs ( USER_LED1 / USER_LED2 / USER_LED3 / USER_LED4 ) / D1, D2, D3, D4 | - | OUT | User definable, green |
LED ( USB1_OC_n ) / D9 | - | OUT | USB J8 bus over current signal, red. |
LED ( 3V3_VDD_FTDI ) / D20 | - | OUT | Power indication LED, green. |
LEDs ( F_UART_RX_LED / F_UART_TX_LED ) / D18, D19 | - | OUT | Receive / Transmit indication LEDs, green |
LED ( 12V0 ) / D22 | - | OUT | Board Main Power Indication LED, green. |
LED ( ERROR_OUT ) / D5 | - | OUT | SoC Error State Indication LED, red. |
LED ( DONE ) / D6 | - | OUT | SoC Boot Indication LED, green. |
LED ( POR_B_n ) / D7 | - | OUT | Power-On Reset Indication LED, green. |
LED ( M2_LED ) / D8 | - | OUT | M.2 Activity Indication LED, green. |
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
Jumper header | Net name / Connector.pin | ||
|---|---|---|---|
Output | Input | Notes | |
J3 | I2C_V / J3.3 | Set I2C bus I2C2 voltage. | |
1V8 / J3.1 | Set I2C2 bus voltage to 1.8 V. | ||
3V3_PS / J3.5 | Set I2C2 bus voltage to 3.3 V. | ||
J4 | VCC_FUSE / J4.2 | Set the SoC voltage for eFUSE programming. | |
1V8 / J4.1 | Enable eFUSE programming. | ||
GND / J4.3 | Disable eFUSE programming. | ||
J18 | CAN0_N / J18.3 | Set CAN termination for signal CAN0_N. | |
No net name / J18.1 | Connect to termination. | ||
CAN0_P / J18.4 | Set CAN termination fro signal CAN0_P. | ||
No net name / J18.2 | Connect to termination. | ||
J19 | CAN1_N / J19.3 | Set CAN termination for signal CAN1_N. | |
No net name / J19.1 | Connect to termination. | ||
CAN1_P / J19.4 | Set CAN termination for signal CAN1_P. | ||
No net name / J19.2 | Connect to termination. | ||
Voltage level | ||||
|---|---|---|---|---|
Button | Signal | Low | high | Function |
S3/S4 | USER_PB1 | pressed | unpressed | User definable. |
S5/S6 | USER_PB2 | pressed | unpressed | User definable. |
S8 | TPM_PP | unpressed | pressed | Trusted platform module 2.0 presence detection. |
S10/S11 | MR_RC_n | pressed | unpressed | Manuel board reset. |
DIP switch group | DIP switch | Signal name / Connector.pin | Description |
|---|---|---|---|
S1 | S1A | PWR_OFF / S1.8 | Disable module / assert U55 (Input protection) state. |
S1B | USER_DIP2 / S1.7 | S1B is parallel to S2B. S1C is parallel to S2A. User definable. | |
S1C | USER_DIP1 / S1.6 | ||
S1D | No net name / S1.5 | Not connected / No function. | |
S2 | S2A | USER_DIP1 / S2.4 | S1B is parallel to S2B. S1C is parallel to S2A. User definable. S2 intended for enclosure usage. |
S2B | USER_DIP2 / S2.3 | ||
S7 | S7A | BOOT_SEL0# / S7.1 |
|
S7B | BOOT_SEL1# / S7.2 | ||
S7C | BOOT_SEL2# / S7.3 | ||
S7D | BOOT_SEL3# / S7.4 | ||
S9 | S9A | PWR_OFF / S9.4 | Disable module / assert U55 (Input protection) state. S1A is parallel to S9A. S9A intended for enclosure usage. |
S9B | No net name / S9.3 | Not connected / No function. |
Power Rail Name / Schematic Name | Description | Connector.Pin | Direction 1) | Notes |
|---|---|---|---|---|
12V0_in / 12V_IN_FUSED | Board Power Supply | J25.1 / J25.2 / J25.3 | IN | Pay attention to connector pinout! |
VBATT | Backup supply (CR1220 / 3.0 Lithium) for SoC RTC | B1 | IN | |
12V0_FAN | Supply for 12 V PWM fan. | J23.2 | OUT | |
3V3_PL | 3.3 V for external IO devices/reference voltage. | J1.33 / J1.34 2) | OUT | |
3V3_PS | 3.3 V for external IO devices/reference voltage. | J3.5 / J20.4 | OUT | Dependent on resistor R259 assembly. |
Notes
1) Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.
2) Only on SoC 35xx variants.
| Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
|---|---|---|---|---|---|
| 0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. |
| 1 | 12V0_IN | 12.0 V (± 5 %) | - | Power supply. | Carrier power supply. |
| 2 | PWR_OFF | - | - | Release signal Power_OFF via DIP switch S1A or S9A. |
Warning!
The listed values ONLY reflect this board. Connected Carriers / SoMs / Boards are not considered.
Power Rail Name / Schematic Name | Description | Min | Max | Unit | Notes |
|---|---|---|---|---|---|
12V0_IN / 12V_IN_FUSED | Board Power Supply. | -0.3 | 50 | V | |
VBATT | Backup supply for SoC RTC. | –0.3 | 6.3 | V |
*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.
The categories are:
These categories do not take into account the entire custom system consisting of:
Classification of the module can be looked up here: Article Number Information i.e.: TExxxx-xx-xx'I'xx, the 'I' indicates that all components are at least in Industrial temperature class.
The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.
The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).
Power Rail Name / Schematic Name | Min | Max | Units | Notes |
|---|---|---|---|---|
12V0_IN / 12V_IN_FUSED | 11.4 | 12.6 | V | |
VBATT | - | 3.0 | V |
Module size: 150.0 mm x 200.0 mm. Please download the assembly diagram for exact numbers.
Trenz shop TE0960 overview page * | |
|---|---|
*) Module article name encoding table: AMD Versal based modules
The hardware revision number can be found on the PCB board together with the module's model number, separated by a dash.
Date | Revision | Changes | Documentation Link |
|---|---|---|---|
2026-09 | 01 | Initial Release |
| Date | Revision | Contributor | Description |
|---|---|---|---|
| |||
-- | all |
|
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