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Template Revision 2.9 - on construction Design Name always "TE Series Name" + optional CPLD Name + "CPLD" - Change List 1.9.1 to 2.0
- add fix table of content
- add table size as macro
- removed page initial creator
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Overview
Lattice MachXO2-4000HC is a CPLD chip, that is used in TEB0912 board as a system management controller. The system controller implements power management same as power sequencing, . Rather than power management is the system controller responsible for reset generation, zynq initial configuration. System controller contains of some additional features same as debouncing the power button and displaying the power status with LEDs. The JTAG and UART interfaces are routed in the firmware of CPLD from FTDI chip to FPGA.
Feature Summary
- Power Management
- Reset Management
- JTAG Routing
- Boot Mode
- User IOs
- LED and power state display
- UART
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
In this board the CPLD is responsible for controlling and monitoring of power supply of the board. There are various DC-DC converter or regulators , one input current sensor and six temperature sensors. To control every converter chip or regualtor monitors CPLD power good outputs of regulators or DC-DC converters continuously to avoid over-voltage in the power system. System controller reads the measured temperature of all temperature sonsors continuously to avoid over-temperature in regulators or DC-DC converter chips. The firmware of CPLD contains of various subsystems same as i2c master and i2c slave subsystems. I2c master reads the data of current sensor and 6 temperature sensors , that measure the temperature of DC-DC converter chips. I2c slave is responsible for communicating with FPGA to read register addresses and write the measured data in FPGA.
Feature Summary
- Power Management
- Reset Management
- JTAG Routing
- Boot Mode
- User IOs
- LED and power state display
- UART
- I2C Slave
- I2C Master
- I2C to GPIO
- RAM Memory
- Data Management State Machine
- Temperature Sensor TMP461
- Current Sensor INA219AIDCNR
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
Name / opt. VHDL Name | Direction | Pin | Pullup/Down (HW) | Bank Power | Description |
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ALERT_N | in | B33 | --- (UP) | +3.3V_STB | Digital output . Interrupt or SMBus alert output of temperature sensors (TMP461AIRUNT- U43,U47,U52,U57,U4) and temperature sensor with integrated fan control (LM96163-U61) /currently_not_used |
CPLD_DEBUG0 | inout | A41 | NONE (UP) |
Name / opt. VHDL Name | Direction | Pin | Pullup/Down | Bank Power | Description |
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ALERT_N | in | B33 | UP | +3.3V_STB | Digital output . Interrupt or SMBus alert output of temperature sensors (TMP461AIRUNT- U43,U47,U52,U57,U4) and temperature sensor with integrated fan control (LM96163-U61) /currently_not_used |
CPLD_DEBUG0 | inout | A41 | UP | +3.3V_STB | CPLD debug pin 0 |
CPLD_DEBUG1 | inout | A2 | UP | +3.3V_STB | CPLD debug pin 1 /currently_not_used |
CPLD_DEBUG2 | inout | B1 | UP | +3.3V_STB | CPLD debug pin 2 /currently_not_used |
CPLD_DEBUG3 | inout | A3 | NONE | +3.3V_STB | CPLD debug pin 3 /currently_not_used |
CPLD_HD0 | inout | B3 | UP | +3.3V_STB | High density IOs select 0 /currently_not_used |
CPLD_HD1 | inout | B28 | UP | +3.3V_STB | High density IOs select 1 /currently_not_used |
EN_VCCINT | out | B22 | DOWNEnable for +.85V DC-DC converter (LTM4630EY-U42A) |
CPLD_DEBUG1 | inout | A2 | UP (UP) |
EN_VTT_DDR | out | A22 | DOWNEnable pin for 2A Peak Sink/Source DDR Termination Regulator (TPS51206-U2, U3) | EN+0.85V_GT_AVCC_PS/ EN_0V85_GT_AVCC_PS | out | B21 | CPLD debug pin 1 --→ For monitoring of I2C master clock (SCL) |
CPLD_DEBUG2 | inout | B1 | UP (UP) |
DOWNEnable pin for 1.5A low-dropout linear regulator (TPS74801DRC-U45) | EN+0.9V_GT_AVCC/ EN_0V9_GT_AVCC | out | B14 | CPLD debug pin 2 --→ For monitoring of I2C master data (SDA) |
CPLD_DEBUG3 | inout | A3 | --- (NONE) | +3.3V_STB | CPLD debug pin 3 /currently_not_used |
CPLD_HD0 | inout | B3 | UP (UP) |
DOWNEnable pin for quad DC-DC microModule regulator with configurable 4A output array for +0.9V output voltage (LTM4644EY-U44) | High density IOs select 0 |
CPLD_HD1 | inout | B28 | UP (UP) |
EN+1.0V/ EN_1V0 | out | A46 | DOWNEnable pin for 1.5A low-dropout linear regulator with +1.0V output voltage (TPS74801DRC-U13) | EN+1.2V_DDR/ EN_1V2_DDR | out | A34 | High density IOs select 1 |
EN_VCCINT | out | B22 | NONE (DOWN) |
DOWN quad microModule regulator with configurable 4A output array for +1.2V output voltage (LTM4644EY-U53converter (LTM4630EY-U42A) |
EN |
+1.2VGT_AVTT/ EN_1V2_GT_AVTTB16A22 | NONE (DOWN) | +3.3V_STB | Enable pin for |
quad DC-DC microModule regulator with configurable 4A output array for +1.2V output voltage (LTM4644EY-U482A Peak Sink/Source DDR Termination Regulator (TPS51206-U2, U3) |
EN+ |
12VPLL1V2PLLA15B21 | NONE (DOWN) | +3.3V_STB | Enable pin for 1.5A low-dropout linear regulator (TPS74801DRC- |
U4613VMGTPS1V3PSB15B14 | NONE (DOWN) | +3.3V_STB | Enable pin for quad DC-DC microModule regulator with configurable 4A output |
array 137V 9V output voltage (LTM4644EY-U44) |
8V1V8B13A46 | NONE (DOWN) | +3.3V_STB | Enable pin for |
quad DC-DC microModule regulator with configurable 4A output array for 1.5A low-dropout linear regulator with +1. |
8V LTM4644EYU538VAUX1V8AUXA30A34 | NONE (DOWN) | +3.3V_STB | Enable pin for |
1.5A low-dropout linear regulator with quad DC-DC microModule regulator with configurable 4A output array for +1. |
8V voltage TPS74801DRC-U49,U50,U518V_PS1V8_PSB20B16 | NONE (DOWN) | +3.3V_STB | Enable pin for |
1.5A low-dropout linear regulator with quad DC-DC microModule regulator with configurable 4A output array for +1. |
8V voltage TPS74801DRCU5425VDDR2V5DDRA44A15 | NONE (DOWN) | +3.3V_STB | Enable pin for 1.5A low-dropout linear regulator |
with +2.5V output voltage U55, U562V2V0A21B15 | NONE (DOWN) | +3.3V_STB | Enable pin for quad DC-DC microModule regulator with configurable 4A output |
array 20V 37V output voltage (LTM4644EY- |
U4833V3V3B18B13 | NONE (DOWN) | +3.3V_STB | Enable pin for quad DC-DC microModule regulator with configurable 4A output array for + |
33V 8V output voltage (LTM4644EY- |
U15VBIAS5VVBIASA17A30 | NONE (DOWN) | +3.3V_STB | Enable pin for 1.5A low-dropout linear regulator with + |
5V voltage ADP7102ACPZ-U58)TPS74801DRC-U49,U50,U51) |
EN+1.8V_GT_AVTT_PS/ EN_1V8_GT_AVTT_PS | out | B20 | NONE (DOWN) |
EXT_STATUS_LED_G | out | B9 | NONEExternal status LED green (J40-Pin2) /currently_not_used | Enable pin for 1.5A low-dropout linear regulator with +1.8V output voltage (TPS74801DRC-U54) |
EN+2.5V_DDR/ EN_2V5_DDR | out | A44 | NONE (DOWN) |
EXT_STATUS_LED_R | out | A25 | NONEExternal status LED red (J40-Pin3) /currently_not_used | Enable pin for 1.5A low-dropout linear regulator with +2.5V output voltage (TPS74801DRC-U55, U56) |
EN+2V_MGT_PS/ EN_2V0_GT_PS | out | A21 | NONE (DOWN) |
FAN_EN | out | B29 | UPEnables a smart high-side power switch to drive the FAN (BTS41411N-U60) | Enable pin for quad DC-DC microModule regulator with configurable 4A output array for +2.0V output voltage (LTM4644EY-U48) |
EN+3.3V/ EN_3V3 | out | B18 | NONE (DOWN) |
FPGA_DONE | in | A24 | UPFPGA PL configuration done indicator | FTDI_PWR_EN_N | in | A36 | Enable pin for quad DC-DC microModule regulator with configurable 4A output array for +3.3V output voltage (LTM4644EY-U1) |
EN+5V_BIAS/ EN_5V_VBIAS | out | A17 | NONE (DOWN) |
UPActive low power enable output of FTDI chip (FT2232H56Q-U38) | Enable pin for low dropout linear regulator with +5V output voltage (ADP7102ACPZ-U58) |
EXT_STATUS_LED_G | out | B9 | --- (NONE) |
FTDI_RX | out | A35 | NONEUART RXD of FTDI chip (FT2232H56Q-U38) | External status LED green (J40-Pin2) /currently_not_used |
EXT_STATUS_LED_R | out | A25 | --- (NONE) |
FTDI_TCK | in | A45 | NONEFTDI JTAG clock pin (FT2232H56Q-U38) | FTDI_TDI | in | A47 | External status LED red (J40-Pin3) /currently_not_used |
FAN_EN | out | B29 | NONE (UP) |
NONEFTDI JTAG data input pin (FT2232H56Q-U38) | FTDI_TDO | out | A48 | Enables a smart high-side power switch to drive the FAN (BTS41411N-U60) |
FPGA_DONE | in | A24 | NONE (UP) |
NONEFTDI JTAG data output pin (FT2232H56Q-U38)FPGA PL configuration done indicator |
FTDI_ |
TMSB34FTDI JTAG mode select pin Active low power enable output of FTDI chip (FT2232H56Q-U38) |
FTDI_ |
TXinB27A35 | NONE (NONE) | +3.3V_STB | UART |
TXD RXD of FTDI chip (FT2232H56Q-U38) |
I2C_SCL_CPLD | inout | B32 | UPI2C clock pin that connected to all temperature sensors and current sensor /currently_not_used | FTDI JTAG clock pin (FT2232H56Q-U38) |
FTDI_TDI | in | A47 | UP (NONE) |
I2C_SDA_CPLD | inout | A42 | UPI2C pin that connected to all temperature sensors and current sensor /currently_not_usedJTAGEN | in | B30 | input pin (FT2232H56Q-U38) |
FTDI_TDO | out | A48 | NONE (NONE) |
DOWN enable input pin of CPLD (Dip switch S4-1) If logical low, JTAG routed to FPGA. If logical high, CPLD access. data output pin (FT2232H56Q-U38) |
FTDI_TMS | in | B34 | NONE (NONE) | +3.3V_STB | FTDI JTAG mode select pin (FT2232H56Q-U38) |
FTDI_TX | in | B27 | UP (NONE) | +3.3V_STB | UART TXD of FTDI chip (FT2232H56Q-U38) |
I2C_SCL_CPLD | inout | B32 | NONE (UP) | +3.3V_STB | I2C clock pin that connected to all temperature sensors and current sensor |
I2C_SDA_CPLD | inout | A42 | NONE (UP) | +3.3V_STB | I2C data pin that connected to all temperature sensors and current sensor |
JTAGEN | in | B30 | --- (DOWN) | +3.3V_STB | JTAG enable input pin of CPLD (Dip switch S4-1) If logical low, JTAG routed to FPGA. If logical high, CPLD access. |
MIO30 / MIO30_UART0_RXD | out | A8 | NONE (NONE) | +1.8V | MIO30 pin of FPGA (XCZU11EG-1FFVC1760I- U30R) |
MIO31 /MIO31_UART0_TXD | in | A9 | UP (NONE) | +1.8V | MIO31 pin of FPGA (XCZU11EG-1FFVC1760I- U30R) |
MIO32 / MIO32_UART1_TXD | in | B8 | --- (NONE) | +1.8V | MIO32 pin of FPGA (XCZU11EG-1FFVC1760I- U30R) /currently_not_used |
MIO33 / MIO33_UART1_RXD | out | B7 | --- (NONE) | +1.8V | MIO33 pin of FPGA (XCZU11EG-1FFVC1760I- U30R) /currently_not_used |
MR | out | A26 | UP (UP) | +3.3V_STB | Manual-reset that connected to MR pin of ultralow supply-current voltage monitor chip (TPS3106K33DBVR-U73) |
NetU68_B2 |
| B2 | --- |
| /currently_not_used |
PG_VCCINT | in | B23 | NONE (UP) |
MIO30 / MIO30_UART0_RXD | out | A8 | NONE | +1.8V | MIO30 pin of FPGA (XCZU11EG-1FFVC1760I- U30R) |
MIO31 /MIO31_UART0_TXD | in | A9 | NONE | +1.8V | MIO31 pin of FPGA (XCZU11EG-1FFVC1760I- U30R) |
MIO32 / MIO32_UART1_TXD | in | B8 | NONE | +1.8V | MIO32 pin of FPGA (XCZU11EG-1FFVC1760I- U30R) /currently_not_used |
MIO33 / MIO33_UART1_RXD | out | B7 | NONE | +1.8V | MIO33 pin of FPGA (XCZU11EG-1FFVC1760I- U30R) /currently_not_used |
MR | out | A26 | UP | +3.3V_STB | Manual-reset that connected to MR pin of ultralow supply-current voltage monitor chip (TPS3106K33DBVR-U73) |
NetU68_B2 | B2 | /currently_not_used | PG_VCCINT | in | B23 | UP | +3.3V_STB | Power good pin for +0.85V DC-DC converter (LTM4630EY-U42A) |
PG+0.85V_GT_AVCC_PS/ PG_0V85_GT_AVCC_PS | in | B12 | UP | +3.3V_STB | Power good pin for 1.5A low-dropout linear regulator for +0.85V output voltage (TPS74801DRC-U45) |
PG+0.9V_GT_AVCC/ PG_0V9_GT_AVCC | in | A18 | UP | +3.3V_STB | Power good pin for quad DC-DC microModule regulator with configurable 4A output array for +0.9V output voltage (LTM4644EY-U44) |
PG+1.0V/ PG_1V0 | in | B35 | UP | +3.3V_STB | Power good pin for 1.5A low-dropout linear regulator with +1.0V output voltage (TPS74801DRC-U13) |
PG+1.2V_DDR/ PG_1V2_DDR | in | A33 | UP | +3.3V_STB | Power good pin for quad DC-DC microModule regulator with configurable 4A output array for +1.2V output voltage (LTM4644EY-U53) |
PG+1.2V_GT_AVTT/ PG_1V2_GT_AVTT | in | A11 | UP | +3.3V_STB | Power good pin for |
quad microModule regulator with configurable 4A output array for +1.2V output voltage (LTM4644EY-U48converter (LTM4630EY-U42A) |
PG+ |
12VPLL1V2PLLPSA28B12 | NONE (UP) | +3.3V_STB | Power good pin for 1.5A low-dropout linear regulator for + |
12V 85V output voltage (TPS74801DRC- |
U4613VMGTPS1V3MGTPSA20A18 | NONE (UP) | +3.3V_STB | Power good pin for quad DC-DC microModule regulator with configurable 4A output array for +0.9V output voltage (LTM4644EY-U44) |
PG+1. |
8V1V8B25B35 | NONE (UP) | +3.3V_STB | Power good pin for |
quad DC-DC microModule regulator with configurable 4A output array for 1.5A low-dropout linear regulator with +1. |
8V LTM4644EYU538VAUX1V8AUXA27A33 | NONE (UP) | +3.3V_STB | Power good pin for |
1.5A low-dropout linear regulator with quad DC-DC microModule regulator with configurable 4A output array for +1. |
8V voltage TPS74801DRCU508VAUXPS1V8AUXPSB10A11 | NONE (UP) | +3.3V_STB | Power good pin for |
1.5A low-dropout linear regulator with quad DC-DC microModule regulator with configurable 4A output array for +1. |
8V voltage TPS74801DRCU518VGTAUX1V8GTAUXA13A28 | NONE (UP) | +3.3V_STB | Power good pin for 1.5A low-dropout linear regulator |
with 8V voltage U498VGTAVTT_1V8GT_AVTTA16A20 | NONE (UP) | +3.3V_STB | Power good pin for |
1.5A low-dropout linear regulator with +1.8V output voltage (TPS74801DRC-U54quad DC-DC microModule regulator with configurable 4A output array for +0.9V output voltage (LTM4644EY-U44) |
PG+ |
25V_DDR2V5_DDRA32B25 | NONE (UP) | +3.3V_STB | Power good pin for |
1.5A low-dropout linear regulator with +2.5V output voltage (TPS74801DRC-U55quad DC-DC microModule regulator with configurable 4A output array for +1.8V output voltage (LTM4644EY-U53) |
PG+ |
25VPL_DDR2V5PL_DDRA38A27 | NONE (UP) | +3.3V_STB | Power good pin for 1.5A low-dropout linear regulator with + |
25V 8V output voltage (TPS74801DRC- |
U562VMGT2VMGTA1B10 | NONE (UP) | +3.3V_STB | Power good pin for |
quad DC-DC microModule regulator with configurable 4A output array for +2.0V output voltage (LTM4644EY-U481.5A low-dropout linear regulator with +1.8V output voltage (TPS74801DRC-U51) |
PG+ |
3.3V3V3A23A13 | NONE (UP) | +3.3V_STB | Power good pin for |
quad DC-DC microModule regulator with configurable 4A output array with +3.3V output voltage (LTM4644EY-U1)1.5A low-dropout linear regulator with +1.8V output voltage (TPS74801DRC-U49) |
PG+1.8V_GT_AVTT_PS/ PG_1V8_GT_AVTT_PS | in | A16 | NONE (UP) |
PWR_BTN | in | A12 | UP button input (J40-Pin1)PWR_STAT_GRN | out | B24 | good pin for 1.5A low-dropout linear regulator with +1.8V output voltage (TPS74801DRC-U54) |
PG+2.5V_DDR/ PG_2V5_DDR | in | A32 | NONE (UP) |
NONERed LED for power status display ( D11-Red) | Power good pin for 1.5A low-dropout linear regulator with +2.5V output voltage (TPS74801DRC-U55) |
PG+2.5V_PL_DDR/ PG_2V5_PL_DDR | in | A38 | NONE (UP) |
PWR_STAT_RED | out | A31 | NONEGreen LED for power status display (D12-Green) | Power good pin for 1.5A low-dropout linear regulator with +2.5V output voltage (TPS74801DRC-U56) |
PG+2V_MGT_PS/ PG_2V_MGT_PS | in | A1 | NONE (UP) | +3.3V_STB | Power good pin for quad DC-DC microModule regulator with configurable 4A output array for +2.0V output voltage (LTM4644EY-U48) |
PG+3.3V/ PG_3V3 | in | A23 | NONE (UP) | +3.3V_STB | Power good pin for quad DC-DC microModule regulator with configurable 4A output array with +3.3V output voltage (LTM4644EY-U1) |
PWR_BTN | in | A12 | UP (UP) | +3.3V_STB | Power button input (J40-Pin1) |
PWR_STAT_GRN | out | B24 | NONE (NONE) |
SRST_B | inout | B5 | UP | +1.8V | PS software reset (Active Low) (XCZU11EG-1FFVC1769I- U30S) |
TCK | out | A5 | NONE | +1.8V | Zynq JTAG clock pin (XCZU11EG-1FFVC1760I- U30S) |
TDI | out | B4 | NONE | +1.8V | Zynq JTAG data input pin (XCZU11EG-1FFVC1760I- U30S) |
TDO | in | A6 | NONE | +1.8V | Zynq JTAG data output pin (XCZU11EG-1FFVC1760I- U30S) |
THERM_N | in | A40 | UPOvertemperature termal shutdown pin of temperature sensors ( TMP461, U43,U47,U52,U57,U4) and temperature sensor with integrated fan control (LM96163-U61) /currently_not_used | TMS | out | A7 | NONERed LED for power status display ( D11-Red) |
PWR_STAT_RED | out | A31 | NONE (NONE) | +3.3V_STB | Green LED for power status display (D12-Green) |
SRST_B | inout | B5 | NONE (UP) | +1.8V |
Zynq JTAG mode select pin PS software reset (Active Low) (XCZU11EG- |
1FFVC1760I Functional DescriptionJTAG
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA is multiplexed via JTAGEN pin of CPLD (B30) (logical one for CPLD, logical zero for FPGA).
CPLD JTAGEN (Dip switch S4-1) | Description |
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0 | FPGA access |
1 | CPLD access |
Boot Mode
TEB0912 supports JTAG, QSPI and SD card boot modes. Boot mode depends on the logic state of S2 dip switch pins that are connected with FPGA boot mode configuration pins.
S2-4 | S2-3 | S2-2 | S2-1 | Boot Mode |
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OFF | OFF | OFF | OFF | PS JTAG |
OFF | OFF | ON | OFF | Quad-SPI (32b) |
ON | ON | ON | OFF | SD1 LS (3.0) |
Power
In this board the CPLD is responsible for controlling and monitoring of power supply of the board. There are various DC-DC converter or regulators. To control every converter chip or regualtor the CPLD monitors power good outputs of regulators or DC-DC converters continuously to avoid over-voltage in the power system.
Enable Signal | Power Good Signal | Domain | Schematic Page | Input power Net | Regulator/ DC-DC Converter | Output power Net |
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A5 | NONE (NONE) | +1.8V | Zynq JTAG clock pin (XCZU11EG-1FFVC1760I- U30S) |
TDI | out | B4 | NONE (NONE) | +1.8V | Zynq JTAG data input pin (XCZU11EG-1FFVC1760I- U30S) |
TDO | in | A6 | NONE (NONE) | +1.8V | Zynq JTAG data output pin (XCZU11EG-1FFVC1760I- U30S) |
THERM_N | in | A40 | --- (UP) | +3.3V_STB | Overtemperature termal shutdown pin of temperature sensors ( TMP461, U43,U47,U52,U57,U4) and temperature sensor with integrated fan control (LM96163-U61) /currently_not_used |
TMS | out | A7 | NONE (NONE) | +1.8V | Zynq JTAG mode select pin (XCZU11EG-1FFVC1760I- U30S) |
Functional Description
JTAG
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA is multiplexed via JTAGEN pin of CPLD (B30) (logical one for CPLD, logical zero for FPGA).
Scroll Title |
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title-alignment | center |
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title | CPLD access |
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CPLD JTAGEN (Dip switch S4-1) | Description |
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0 | FPGA access | 1 | CPLD access |
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Boot Mode
TEB0912 supports JTAG, QSPI and SD card boot modes. Boot mode depends on the logic state of S2 dip switch pins that are connected with FPGA boot mode configuration pins.
Scroll Title |
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title-alignment | center |
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title | Boot Mode table |
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S2-4 | S2-3 | S2-2 | S2-1 | Boot Mode |
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OFF | OFF | OFF | OFF | PS JTAG | OFF | OFF | ON | OFF | Quad-SPI (32b) | ON | ON | ON | OFF | SD1 LS (3.0) |
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Power
In this board the CPLD is responsible for controlling and monitoring of output voltage and temperature of regulators and DC-DC converters. To control every converter chip or regualtor the CPLD monitors power good signal of regulators or DC-DC converters continuously to avoid over-voltage in the power system.
Scroll Title |
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title-alignment | center |
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title | PG and EN Signals |
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Enable Signal | Power Good Signal | Schematic Page | Input power Net | Regulator/ DC-DC Converter | Designator | Output power Net |
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EN+1.0V | PG+1.0V | PCIe_Switch_PWR | +1.37V | TPS74801DRC | U13 | +1.0V | EN+2.5V_DDR | PG+2.5V_DDR PG+2.5V_PL_DDR | POWER3 POWER3 | +3.3V +3.3V | TPS74801DRC TPS74801DRC | U55 U56 | +2.5V_DDR +2.5V_PL_DDR | EN+1.8V | PG+1.8V | POWER3 | +12V | LMT4644EY | U54 | +1.8V | EN+1.2V_DDR | PG+1.2V_DDR | POWER3 | +12V | LMT4644EY | U53 | +1.2V_DDR | EN+1.8V_AUX | PG+1.8V_AUX PG+1.8V_GT_AUX PG+1.8V_AUX_PS | POWER2 POWER2 POWER2 | +2V_MGT_PS +2V_MGT_PS +2V_MGT_PS | TPS74801DRC TPS74801DRC TPS74801DRC | U50 U49 U51 | +1.8V_AUX +1.8V_GT_AUX +1.8V_AUX_PS | EN+1.2V_PLL_PS | PG+1.2V_PLL_PS | POWER1 | +1.37V | TPS74801DRC | U46 | +1.2V_PLL_PS | EN+0.85V_GT_AVCC_PS | PG+0.85V_GT_AVCC_PS | POWER1 | +1.37V | TPS74801DRC | U45 | +0.85V_GT_AVCC_PS | EN+1.8V_GT_AVTT_PS | PG+1.8V_GT_AVTT_PS | POWER3 | +2V_MGT_PS | TPS74801DRC | U54 | +1.8V_GT_AVTT_PS | EN+1.2V_GT_AVTT | PG+1.2V_GT_AVTT | POWER2 | +12V | LTM4644EY | U48 | +1.2V_GT_AVTT | EN+5V_BIAS | -- | POWER6 | +12V | ADP7102ACPZ-5.0-R7 | U58 | +5V_BIAS | EN+0.9V_GT_AVCC | PG+0.9V_GT_AVCC | POWER1 | +12V | LTM4644EY | U44 | +0.9V_GT_AVCC | EN+1.3V_MGT_PS | PG+1.3V_MGT_PS | POWER1 | +12V | LTM4644EY | U44 | +1.37V | EN+2V_MGT_PS | PG+2V_MGT_PS | POWER2 | +12V | LTM4644EY | U48 | +2V_MGT_PS | EN_VTT_DDR_PL EN_VTT_DDR_PS | --- --- | POWER4 POWER4 | +3.3V +3.3V | TPS51206DSQ TPS51206DSQ | U2 U3 | VTT_DDR_PL VTT_DDR_PS | EN+3.3V | PG+3.3V | POWER4 | +12V | LTM4644EY | U1 | +3.3V | EN_VCCINT | PG_VCCINT | POWER0 | +12V | LTM4630EY | U42A | +0.85V_VCCINT |
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title | Power Sequencing State Machine |
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diagramName | TEB0912_Power_Sequencing_Flowchart |
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title | Power sequencing table |
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Sequence | Power Net Name | Correspondent Net Name on Board | Regulator | Enable Signal | PG Signal | Description |
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1 | ----- VCC_PSINTLP VCC_PSINTFP VCCINT ----- ----- | +5V_BIAS +0.85V_VCCINT +0.85V_VCCINT +0.85V_VCCINT +1.37V +2V_MGT_PS | U58 U42 U42 U42 U44 U48 | EN_5V_VBIAS EN_VCCINT EN_VCCINT EN_VCCINT EN_1V3_GT_PS EN_2V0_GT_PS | ---- PG_VCCINT PG_VCCINT PG_VCCINT PG_1V3_GT_PS PG_2V_MGT_PS | - +5V_BIAS pin is connected to bias pin of +1.8V_GT_AUX , +1.8V_AUX, +1.8V_AUX_PS , +1.8V_GT_AVTT_PS , +0.85V_GT_AVCC_PS and +1.2V_PLL_PS regulator bias pins.
- +1.37V pin is connected to regulator inputs for +0.85V_GT_AVCC_PS and +12V_PLL_PS voltages.
- +2V_MGT_PS pin is connected to regulator inputs for +1.8V_AUX , +1.8V_GT_AUX , +1.8V_AUX_PS, +1.8V_GT_AVTT_PS voltages.
| 2 | VCC_PSAUX VCC_PSADC VCCO_PSIO VCC_PSPLL VPS_MGTRAVCC VCC_PSDDR_PLL VCCINT_IO VCCBRAM VCCAUX VCCAUX_IO VMGTAVCC ---- | +1.8V_AUX_PS +1.8V +1.8V +1.2V_PLL_PS +0.85V_GT_AVCC_PS +1.8V_AUX_PS +0.85V_VCCINT +0.85V_VCCINT +1.8V_AUX +1.8V_AUX +0.9V_GT_AVCC +3.3V | U51 U53 U53 U46 U45 U51 U42 U42 U50 U50 U44 U1 | EN_1V8_AUX EN_1V8 EN_1V8 EN_1V2_PLL_PS EN_0V85_GT_AVCC_PS EN_1V8_AUX EN_VCCINT EN_VCCINT EN_1V8_AUX EN_1V8_AUX EN_0V9_GT_AVCC EN_3V3 | PG_1V8_AUX PG_1V8 PG_1V8 PG_1V2_PLL_PS PG_0V85_GT_AVCC_PS PG_1V8_AUX PG_VCCINT PG_VCCINT PG_1V8_AUX PG_1V8_AUX PG_0V9_GT_AVCC PG_3V3 | - 3.3V pin is connected to DDR regulator inputs. ( +2.5V_PL_DDR , +2.5V_DDR , VTT_DDR_PS and VTT_DDR_PL)
| 3 | VPS_MGTRAVTT VCCO_PSDDR VMGTAVTT | +1.8V_GT_AVTT_PS +1.2V_DDR +1.2V_GT_AVTT | U54 U53 U48 | EN_1V8_GT_AVTT_PS EN_1V2_DDR EN_1V2_GT_AVTT | PG_1V8_GT_AVTT_PS PG_1V2_DDR PG_1V2_GT_AVTT | - +1.2V_DDR is connected to DDR_PL and DDR_PS regulator inputs.
| 4 | ---- ---- ---- | VTT_DDR_PL , VTT_DDR_PS +2.5V_PL_DDR , +2.5V_DDR +1.0V | U2,U3 U55,U56 U13 | EN_VTT_DDR EN_2V5_DDR EN_1V0 | ---- PG_2V5_DDR , PG_2V5_PL_DDR PG_1V0 | - +1.0V is for PCIe switch.
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I2C
The main interface in the system is I2C interface. The user can input the data in the system through i2c slave subsystem. The entered data is stored in RAM memory. The state machine reads the stored data and communicates with corresponding sensor through i2c master subsystem and stores the feedback data again in RAM memory. The user can read back reported data for example temperature value.
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title | I2C |
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diagramName | TEB0912_CPLD_I2C |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 1539 |
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revision | 1 |
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Internal Registers
Ram memory is a 16x8 Byte Memory.
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title | Registers |
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Register Name | Register address | Bits | CPLD | FPGA |
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config_reg | 0x00 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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0 | 0 | 0 | 0 | 0 | read_bit | write_bit | start_bit |
| Read | Write | sensor_addr | 0x01 | 8-bits | Read | Write | pointer_reg_byte | 0x02 | 8-bits | Read | Write | data_to_write | 0x03 | 8-bits | Read | Write | Reserved | 0x04 | 8-bits |
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| Reserved | 0x05 | 8-bits |
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| Reserved | 0x06 | 8-bits |
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| Reserved | 0x07 | 8-bits |
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| state register | 0x08 |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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0 | 0 | 0 | 0 | 0 | 0 | 0 | data_trans_busy |
| Write | Read | data_to_read | 0x09 | 8-bits | Write | Read | Reserved | 0x0A | 8-bits |
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| Reserved | 0x0B | 8-bits |
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| Reserved | 0x0C | 8-bits |
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| Reserved | 0x0D | 8-bits |
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| Reserved | 0x0E | 8-bits |
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| Reserved | 0x0F | 8-bits |
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The memory consists of the following registers:
- config_reg
- sensor_addr
- pointer_reg_byte
- data_to_write
- state_reg
- data_to_read
Sensor_addr register consists of sensor address that the temperature should be read from. Pointer_reg_byte is sensor internal register address that is to be written to or read from. Data_to_write register consists of data that in pointer_reg_byte will be written. The readed data from sensor is saved in data_to_read register. As long as state machine is busy , it will be state_teg value equal to 0x01. Config_reg consists of control bits. To start data transfer in state machine start_bit must be set to 1. If write_bit set to one, the inhalt of data_to_write will be written in pointer_reg_byte register of sensor . To read the inhalt of pointer_reg_byte register of sensor the read_bit must be set to 1.
Transfer state machine
To manage data transfer between RAM memory and i2c master subsystem that is connected with sensors, it is necessary to design a state machine. This state machine will be controlled with control bits of config_reg register. If start_bit is activated, state machine begins to transfer data between RAM memory and i2c master subsystem. If write_bit is set to one, saved data in RAM memory will be written in temperature sensor. If read_bit is set to one, temperature value will be readed from sensor and will be saved in RAM memory. Every state in the state machine consists of a state machine to manage i2c master communications.
In the following diagram this state machine construction is shown:
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title | Data Transfer State Machine |
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diagramName | TEB0912_CPLD_Data_Transfer_SM_Flowchart |
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simpleViewer | false |
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Sensors on board
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title | Sensors |
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Sensor Name | Sensor I2C address | connection | Description | Chip Name | Description |
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+12V, Current sensor | 0x40 | CPLD | Currently not suppported | INA219 | For more information refer to Datasheet | Temperature sensor of +0.85V_VCCINT DC-DC | 0x48 | CPLD | Supported | TMP461 | For more information refer to Datasheet | Temperature sensor of DDR power and +1.8V | 0x4A | CPLD | Supported | TMP461 | --- | Temperature sensor of +3.3V | 0x4B | CPLD | Supported | TMP461 | --- | Temperature sensor with integrated fan controller | 0x4C | CPLD | Supported | TMP461 | --- | Temperature sensor of +1.2V_GT_AVTT | 0x4D | CPLD | Supported | TMP461 | --- | Temperature sensor of +0.9V_GT_AVCC | 0x4E | CPLD | Supported | TMP461 | --- |
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All temperature sensors are TMP461 of texas instruments. When this sensor is in shutdown mode, a single conversion is started by writing any value in one_shot_start register ( poniter address 0x0F). The device returns to shutdown mode when the conversion and cycle completes. The result value is saved in high and low byte of Local/ Remote temperature registers. The high byte consists of temperature integer value and low byte consists of fraction part of temperature value. (Pointer addresses 0x00,0x15 for local temperature register and pointer addresses 0x01,0x10 for remote temperature register). The channel enable register (read address 16h, write address 16h) enables or disables the temperature conversion of remote and local temperature sensors. LEN (bit 0) of the channel enable register enables/disables the conversion of local temperature. REN (bit 1) of the channel enable register enables/disables the conversion of remote temperature. Both LEN and REN are set to 1 (default), this enables the ADC to convert both local and remote temperatures.
The TMP461 device is a digital temperature sensor that combines a local temperature measurement channel and a remote-junction temperature measurement channel in a single WQFN-10 package. The device is two-wire and SMBus-interface-compatible with nine pin-programmable bus address options, and is specified over a temperature range of –40°C to 125°C. The TMP461 device also contains multiple registers for programming and holding configuration settings, temperature limits, and temperature measurement results. In the following it is listed important registers of this sensor:
STATUS REG---------------------------------------Addr ---> 0x02 (read only) (Default N/A)
Local temperature register MSB 8 bits---------Addr ---> 0x00 (read only) (Default 0x00)
Local temperature register LSB 4 bits----------Addr ---> 0x15 (read only) (Default 0x00)
Remote temperature register MSB 8 bits------Addr ---> 0x01 (read only) (Default 0x00)
Remote temperature register LSB 4 bits-------Addr ---> 0x10 (read only) (Default 0x00)
Configuration register---------------------------Addr ---> 0x03 (read/write) (Default 0x00)
Channel enable register-------------------------Addr ---> 0x16 (read/write) (Default 0x03)
Conversion rate register------------------------Addr ---> 0x04 (read/write) (Default 0x08)
One-shot start register--------------------------Addr ---> 0x0F (read/write) (Default N/A)
The INA219 is a high-side current shunt and power monitor with an I2C interface. The INA219 monitors both shunt drop and supply voltage, with programmable conversion times and filtering. A programmable calibration value, combines with an internal multiplier, enables direct readouts in amperes. An additional multiplying register calculates power in watts. The I2C interface features 16 programmable accesses.
To access these sensors through ZynqMP can be executed the following instructions in linux console consecutively:
- Write device address
- Write register address
- Write data that should be written in the register
- Start to write data
- Stop writing data
- Start to read data
- Stop reading data
- Read data_to_read register
For example to read a temperature sensor it is necessary to give the following commands in linux console:
i2cset -y 2 0x20 0x01 <sensor address> --> Writing device address
i2cset -y 2 0x20 0x02 0x0F --> Writing One-shot register address
i2cset -y 2 0x20 0x03 0xFF --> Writing any value in the register to start converting of ADC in sensor
i2cset -y 2 0x20 0x00 0x03 --> Start to write these values
i2cset -y 2 0x20 0x00 0x00 --> To turn i2c master data transfer off
i2cset -y 2 0x20 0x02 0x00 --> Writing address of local temperature high byte register that consists of the temperature value
i2cset -y 2 0x20 0x00 0x03 --> Start to write these values
i2cset -y 2 0x20 0x00 0x00 --> To turn i2c master data transfer off
i2cset -y 2 0x20 0x00 0x05 --> Start to read temperature value of sensor and save it in data_to_read register
i2cset -y 2 0x20 0x00 0x00 --> To turn i2c master data transfer off
i2cget -y 2 0x20 0x09 --> Reading temperature value from data_to_read register
i2cset -y 2 0x20 0x02 0x15 --> Writing address of local temperature low byte register that consists of fraction of the temperature value
i2cset -y 2 0x20 0x00 0x03 --> Start to write these values
i2cset -y 2 0x20 0x00 0x00 --> To turn i2c master data transfer off
i2cset -y 2 0x20 0x00 0x05 --> Start to read temperature value of sensor and save it in data_to_read register
i2cset -y 2 0x20 0x00 0x00 --> To turn i2c master data transfer off
i2cget -y 2 0x20 0x09 --> Reading temperature fraction value from data_to_read register
If the following shell script is executed in linux console it can be read all temperatures of all temperature sensors on the board. This script file will be executed automatically while booting, if this file is copied to SD card.
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#!/bin/sh
set sensor_addr=0 # Temperature = Temp+Fraction*16^-1 °C for example 50+1*16^-1 = 50.0625 °C
Temp=0 # 8bits
Fraction=0 # 4bits
i=0
n1=0
n2=0
for sensor_addr in 0x48 0x4A 0x4B 0x4C 0x4D 0x4E
do
echo "Sensor Address $sensor_addr:"
echo "Reading Sensor $i:"
i2cset -y 2 0x20 0x01 $sensor_addr # Write sensor address in RAM memory address 0x01
i2cset -y 2 0x20 0x02 0x0F # Write one-shot-start register address in 0x02 of RAM
i2cset -y 2 0x20 0x03 0xFF # Write 0xFF value in 0x03 address of RAM
i2cset -y 2 0x20 0x00 0x03 # Writing in sensor
i2cset -y 2 0x20 0x00 0x00 # Stop writing
i2cset -y 2 0x20 0x02 0x00 # Write 0x00 value (local temperature register high byte address) in 0x02 of RAM memory
i2cset -y 2 0x20 0x00 0x03 # Writing in sensor
i2cset -y 2 0x20 0x00 0x00 # Stop writing
i2cset -y 2 0x20 0x00 0x05 # Reading sensor
i2cset -y 2 0x20 0x00 0x00 # Stop reading
Temp=`i2cget -y 2 0x20 0x09` # Read temperature value stored in 0x09 address of RAM memory
#echo $Temp
n1=$(($Temp))
#echo $n1
i2cset -y 2 0x20 0x02 0x15 # Write 0x15 value (local temperature register low byte address) in 0x02 of RAM memory
i2cset -y 2 0x20 0x00 0x03 # Writing in sensor
i2cset -y 2 0x20 0x00 0x00 # Stop writing
i2cset -y 2 0x20 0x00 0x05 # Reading sensor
i2cset -y 2 0x20 0x00 0x00 # Stop reading
Fraction=`i2cget -y 2 0x20 0x09` # Read temperature value stored in 0x09 address of RAM memory
#echo $Fraction
n2=$((Fraction>>4)) # Shift bits 4 times
#echo $n2
echo "-----------------------------"
#printf "Sensor %d Temperature = %d Celsius \n" $i $Temp
#printf "Sensor %d Fraction = %d \n" $i $Fraction
echo "Sensor $i Temperature = "
awk "BEGIN {print $n1+$n2*16**-1}"
echo "Celsius"
echo "-----------------------------"
let i++
done |
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Image Added |
LED
Green LED
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title | Green LED States |
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EN+1.0V | PG+1.0V | PCIe_Switch_PWR | +1.37V | TPS74801DRC | +1.0V | EN+2.5V_DDR | PG+2.5V_DDR PG+2.5V_PL_DDR | POWER3 POWER3 | +3.3V +3.3V | TPS74801DRC TPS74801DRC | +2.5V_DDR +2.5V_PL_DDR | EN+1.8V | PG+1.8V | POWER3 | +12V | LMT4644EY | +1.8V | EN+1.2V_DDR | PG+1.2V_DDR | POWER3 | +12V | LMT4644EY | +1.2V_DDR | EN+1.8V_AUX | PG+1.8V_AUX PG+1.8V_GT_AUX PG+1.8V_AUX_PS | POWER2 POWER2 POWER2 | +2V_MGT_PS +2V_MGT_PS +2V_MGT_PS | TPS74801DRC TPS74801DRC TPS74801DRC | +1.8V_AUX +1.8V_GT_AUX +1.8V_AUX_PS | EN+1.2V_PLL_PS | PG+1.2V_PLL_PS | POWER1 | +1.37V | TPS74801DRC | +1.2V_PLL_PS | EN+0.85V_GT_AVCC_PS | PG+0.85V_GT_AVCC_PS | POWER1 | +1.37V | TPS74801DRC | +0.85V_GT_AVCC_PS | EN+1.8V_GT_AVTT_PS | PG+1.8V_GT_AVTT_PS | POWER3 | +2V_MGT_PS | TPS74801DRC | +1.8V_GT_AVTT_PS | EN+1.2V_GT_AVTT | PG+1.2V_GT_AVTT | POWER2 | +12V | LTM4644EY | +1.2V_GT_AVTT | EN+5V_BIAS | -- | POWER6 | +12V | ADP7102ACPZ-5.0-R7 | +5V_BIAS | EN+0.9V_GT_AVCC | PG+0.9V_GT_AVCC | POWER1 | +12V | LTM4644EY | +0.9V_GT_AVCC | EN+1.3V_MGT_PS | PG+1.3V_MGT_PS | POWER1 | +12V | LTM4644EY | +1.37V | EN+2V_MGT_PS | PG+2V_MGT_PS | POWER2 | +12V | LTM4644EY | +2V_MGT_PS | EN_VTT_DDR | --- | POWER4 | +3.3V +3.3V | TPS51206DSQ TPS51206DSQ | VTT_DDR_PL VTT_DDR_PS | EN+3.3V | PG+3.3V | POWER4 | +12V | LTM4644EY | +3.3V | EN_VCCINT | PG_VCCINT | POWER0 | +12V | LTM4630EY | +0.85V_VCCINT | Scroll Title |
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title | State Machine Diagram |
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diagramName | TEB0912_Power_Swquencing_Diagram |
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LED
Green LED |
State | Blink sequence | Comment |
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IDLE | OFF | Power sequencing can not be started. Power button is not pushed or is not pushed correctly. | STAGE1 | ooooooo* |
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Power good signal PG_VCCINT is faulty.The following power good signals are faulty. PG_VCCINT PG_1V3_MGT_PS PG_2V_MGT_PS | STAGE2 | oooooo** | The following power good signals are faulty. The error may be due to a problem in a corresponding DC-DC converter or regulator. PG_0V9_GT_AVCC PG_ |
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1V3_MGT_PSPG_0V85_GT_AVCC0V85_GT_AVCC_PS PG_1V2_PLL_PS PG_1V8 PG_3V3 PG_1V8_AUX PG_1V8_AUX_PS PG_ |
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1V2PLLPSAUX | STAGE3 | ooooo*** | The following power good signals are faulty. The error may be due to a problem in a corresponding DC-DC converter or regulator. PG_ |
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2V_MGT_PSPG_1V8_AUXPG_1V8_AUX_PS_AUXPG1V8_GT_STAGE4 | oooo****Power good signal is faulty.STAGE5ooo* power Power good signals are faulty.The error may be due to a problem in a corresponding DC-DC converter or regulator. |
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PG_1V83V3PG_1V2_DDRPG_1V0 | WAIT_RDY | ******** | The state machine remains in this stage as soon as a counter is not overflowed. After overflowing the counter the state machine will jump in the next stage. | RDY | ON | Power is ok and the FPGA is configured successfully. |
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RED LED
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title | Red LED States |
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Status | Blink sequence | Comment |
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pg_all = '0' | ******** | One of the power good signals are faulty. The error may be due to a problem in a DC-DC converter or regulator. | MR = '0' | *****ooo | Reset button is pushed. | SRST_B ='0' | ****oooo | PS software reset (Active Low) is activated. | FPGA_DONE ='0' | ***ooooo | FPGA PL is not configured. | FPGA_DONE ='0' | **oooooo | FPGA PL is not configured. | FTDI_PWR_EN_N='1' | *ooooooo | FTDI chip USB SUSPEND mode or device |
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has not been has not been configured. | else | OFF |
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Appx. A: Change History and Legal Notices
Revision Changes
- Changes REV02 to REV03:
Added i2c slave to communicate with FPGA
Added i2c master to read and write temperature sensors value
Added i2c master state machine to manage communication between CPLD and temp. sensors
Added a 8x16 byte RAM to save data in RAM
- Correction of power sequencing
- Changes
configured.else | OFF | Appx. A: Change History and Legal NoticesRevision Changes
- Changes REV01 to REV02:
- Power Management
- FAN enable
- LED blink sequencing
- Changes REV00 to REV01:
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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| REV02REV03 | REV02, REV03 | Page info |
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infoType | Modified by |
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type | Flat |
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| - REV03 release
- Firmware release (SC-PGM-TEB0912-0302_SC0912-03_20210622.zip)
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2021-02-16 | v.39 | REV02 | REV02, REV03 | Mohsen Chamanbaz | - REV02 release
- Firmware release (SC-PGM-TEB0912-02_SC0912-02_20191127.zip)
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| All |
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infoType | Modified users |
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type | Flat |
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Legal Notices
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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