Page History
HTML |
---|
<!--
Template Revision 1.68
(HTML comments will be not displayed in the document, no need to remove them. For Template/Skeleton changes, increase Template Revision number. So we can check faster, if the TRM style is up to date).
--> |
HTML |
---|
<!--
General Notes:
If some section is CPLD firmware dependent, make a note and if available link to the CPLD firmware description. It's in the TE shop download area in the corresponding module -> revision -> firmware folder.
--> |
HTML |
---|
<!--
General Notes:
Designate all graphics and pictures with a number and a description. For example "Figure 1: TE07xx-xx Block Diagram" or "Table 1: Initial delivery state". "Figure x" and "Table x" have to be formatted to bold.
--> |
HTML |
---|
<!--
Link to the base folder of the module (remove de/ or en/ from the URL): for example:
https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0703/
--> |
...
Scroll pdf ignore | |
---|---|
Table of Contents
|
Overview
The Trenz Electronic TE0820 is an industrial-grade 4 x 5 cm MPSoC SoM (System on Module) module integrating a Xilinx Zynq UltraScale+ with up to 4 GByte 32-Bit DDR4 SDRAM, max. 128 MByte SPI Boot Flash memory for configuration and operation and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via rugged high-speed stacking strips. All Trenz Electronic SoMs in 4 x 5 cm form factor are mechanically compatible.
HTML |
---|
<!--
Use short link the Wiki Ressource page: for example:
http://trenz.org/te0720-info
List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects
--> |
Scroll Only (inline) |
---|
Refer to http://trenz.org/te0820-info for the current online version of this manual and other available documentation.
|
Key Features
- Xilinx Zynq UltraScale+ MPSoC (XCZU2CG / XCZU2EG, XCZU3CG / XCZU3EG or XCZU4CG / XCZU4EV)
- Quad-core or dual-core Cortex-A53 64-bit ARM v8 application processing unit (APU) (depends on assembly variant CG,EG,EV)
- Dual Cortex-R5 32-bit ARM v7 real-time processing unit (RPU)
Four high-speed serial I/O (HSSIO) interfaces supporting following protocols:
- PCI Express® interface version 2.1 compliant
- SATA 3.1 specification compliant interface
DisplayPort source-only interface with video resolution up to 4k x 2k
- USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
- 1 GB/s serial GMII interface
- 132 x HP PL I/Os (3 banks)
- 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
- 4 x serial PS GTR transceivers
- 2 GByte DDR4 SDRAM, 32bit databus-width
- 128 MByte QSPI boot Flash in dual parallel mode
- 8 GByte eMMC
- Programmable quad PLL clock generator PLL for PS GTR clocks (optional external reference)
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Plug-on module with 2 x 100-pin and 1 x 60-pin high-speed hermaphroditic strips
- All power supplies on board
- Size: 50 x 40 mm
...
Block Diagram
HTML |
---|
<!--
Rules for all diagrams:
1. All diagrams are wrapped in the "Scroll Title" macro.
- The title has to be named with the diagrams name
- The anchor has the designation figure_x, whereby x is the number of the diagram
2. The Draw.IO diagram has to be inserted in the "Scroll Ignore" macro
- Border has to be switched off in the macro edit
- Toolbar has to be hidden in the macro edit
3. A PNG Export of the diagram has to be inserted in the "Scroll Only" macro
The workaround with the additional PNG of the diagram is necessary until the bug of the Scroll PDF Exporter, which cuts diagram to two pages, is fixed.
IMPORTANT NOTE: In case of copy and paste the TRM skeleton to a new Wiki page, delete the Draw.IO diagrams and the PNGs, otherwise due to the linkage of the copied diagrams every change in the TRM Skeleton will effect also in the created TRM and vice versa!
See page "Diagram Drawing Guidelines" how to clone an existing diagram as suitable template for the new diagram!
--> |
...
anchor | Figure_1 |
---|---|
title | Figure 1: TE0820-03 block diagram |
...
Scroll Only |
---|
Main Components
...
anchor | Figure_2 |
---|---|
title | Figure 2: TE0820-03 main components |
...
Scroll Only |
---|
...
Initial Delivery State
...
Content
...
Notes
...
SPI Flash OTP Area
...
Empty, not programmed
...
Except serial number programmed by flash vendor.
...
SPI Flash Quad Enable bit
...
Programmed
...
SPI Flash main array
...
Not programmed
...
eFUSE USER
...
Not programmed
...
eFUSE Security
...
Not programmed
...
Table 1: Initial delivery state of programmable devices on the module
Boot Process
Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.
...
Table 2: Boot mode pin description
For more information refer to the TE0820 CPLD - BootMode section.
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
Zynq MPSoC's I/O banks signals connected to the B2B connectors:
...
B2B Connector
...
I/O Signal Count
...
64
...
HP
...
JM2
...
48
...
User
...
64
...
HP
...
JM2
...
2
...
User
...
HP
...
JM2
...
18
...
User
...
65
...
HP
...
JM3
...
16
...
User
...
66
...
HP
...
JM1
...
48
...
User
...
501
...
MIO
...
JM1
...
6
...
3.3V
...
505
...
GTR
...
JM3
...
4 lanes
...
-
...
505
...
GTR CLK
...
JM3
...
1 differential input
...
-
...
-
Table 3: General overview of board to board I/O signals
For detailed information about the pin-out, please refer to the Pin-out table.
MGT Lanes
The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
...
- B505_RX0_P
- B505_RX0_N
- B505_TX0_P
- B505_TX0_N
...
- JM3-26
- JM3-28
- JM3-25
- JM3-27
...
- PS_MGTRRXP0_505, F27
- PS_MGTRRXN0_505, F28
- PS_MGTRTXP0_505, E25
- PS_MGTRTXN0_505, E26
...
- B505_RX1_P
- B505_RX1_N
- B505_TX1_P
- B505_TX1_N
...
- JM3-20
- JM3-22
- JM3-19
- JM3-21
...
- PS_MGTRRXP1_505, D27
- PS_MGTRRXN1_505, D28
- PS_MGTRTXP1_505, D23
- PS_MGTRTXN1_505, D24
...
- B505_RX2_P
- B505_RX2_N
- B505_TX2_P
- B505_TX2_N
...
- JM3-14
- JM3-16
- JM3-13
- JM3-15
...
- PS_MGTRRXP0_505, B27
- PS_MGTRRXN0_505, B28
- PS_MGTRTXP0_505, C25
- PS_MGTRTXN0_505, C26
...
- B505_RX3_P
- B505_RX3_N
- B505_TX3_P
- B505_TX3_N
...
- JM3-8
- JM3-10
- JM3-7
- JM3-9
...
- PS_MGTRRXP1_505, A25
- PS_MGTRRXN1_505, A26
- PS_MGTRTXP1_505, B23
- PS_MGTRTXN1_505, B24
Table 4: MGT lanes
There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.
...
Table 5: MGT reference clock sources
JTAG Interface
JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.
...
JTAG Signal
...
B2B Connector Pin
...
Table 6: JTAG interface signals
Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.
System Controller CPLD I/O Pins
Special purpose pins are connected to System Controller CPLD and have following default configuration:
...
No hard wired function on PCB. When forced low, PGOOD goes low without effect on power management
...
Active low reset, gated to POR_B
...
Table 7: System Controller CPLD special purpose pins.
See also
- 4 x 5 SoM Integration Guide#4x5SoMIntegrationGuide-4x5ModuleControllerIOs
- TE0820 CPLD
- TE0820-REV01_REV02 CPLD
Default PS MIO Mapping
...
JM1-19
...
JM1-21
...
63
...
Table 8: TE0820-03 PS MIO mapping
Gigabit Ethernet
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.
Ethernet PHY connection
...
Table 9: General overview of the Gigabit Ethernet PHY signals
USB Interface
USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 52.000000 MHz oscillator (U14).
USB PHY connection
...
Table 10: General overview of the USB PHY signals.
I2C Interface
On-board I2C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I2C0 by default. Addresses for on-board I2C slave devices are listed in the table below:
...
Si5338A PLL
...
Table 11: Address table of the I2C bus slave devices.
On-board Peripherals
System Controller CPLD
The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.
See also TE0820 System Controller CPLD page.
eMMC Flash Memory
eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.
DDR4 Memory
By default TE0820-03 module has two 16-bit wide Samsung K4A8G165WB DDR4 SDRAM chips arranged into 32-bit wide memory bus providing total of 2 GBytes of on-board RAM. Different memory sizes are available optionally.
Quad SPI Flash Memory
Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U11).
High-speed USB ULPI PHY
Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U14).
MAC Address EEPROM
A Microchip 24AA025E48 serial EEPROM (U25) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x50.
Programmable Clock Generator
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.
A 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.
Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.
...
External clock signal supply from B2B connector JM3, pins JM3-32/JM3-34
...
IN3
...
25.000000 MHz
...
Fixed input clock signal from reference clock generator SiT8008BI-73-18S-25.000000E (U11)
...
IN5
...
-
...
Not connected
...
IN6
...
-
...
-
...
Bank 65 clock input, pins K9 and J9
...
CLK1 A/B
...
MGT reference clock 3 to FPGA Bank 505 PS GTR
...
CLK2 A/B
...
-
...
MGT reference clock 1 to FPGA Bank 505 PS GTR
...
Table 12: General overview of the on-board quad clock generator I/O signals
Oscillators
The module has following reference clock signals provided by on-board oscillators and external source from carrier board:
...
Table 13: Reference clock signals
On-board LEDs
...
Table 14: On-board LEDs
Power and Power-on Sequence
Power Supply
Power supply with minimum current capability of 3A for system startup is recommended.
Power Consumption
...
Table 15: Power consumption
* TBD - To Be Determined soon with reference design setup.
Single 3.3V power supply with minimum current capability of 4A for system startup is recommended.
For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
Warning |
---|
To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any Zynq's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Power Distribution Dependencies
...
anchor | Figure_3 |
---|---|
title | Figure 3: TE0820-03 Power Distribution Diagram |
...
Scroll Only |
---|
...
Power-On Sequence
The TE0820 SoM keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
...
anchor | Figure_4 |
---|---|
title | Figure 4: TE0820-03 Power-on Sequence Diagram |
...
Scroll Only |
---|
...
It is important that all carrier board I/Os are 3-stated at power-on until 3.3V_out or 1.8V_out is present on B2B connector JM2 pins 10 and 12, indicating that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.
Power Rails
...
1, 3, 5
...
Table 16: TE0820-03 power rails
Bank Voltages
...
Table 17: TE0820-03 I/O bank voltages
See Xilinx Zynq UltraScale+ datasheet DS925 for the voltage ranges allowed.
Board to Board Connectors
...
Variants Currently In Production
...
Technical Specifications
Absolute Maximum Ratings
...
Parameter
...
Units
...
Notes
...
VIN supply voltage
...
-0.3
...
7
...
V
...
Voltage on SC CPLD pins
...
-0.5
...
V
...
Storage temperature
...
-40
...
+85
...
°C
...
Table 18: Module absolute maximum ratings
Recommended Operating Conditions
...
Table 19: Recommended operating conditions
Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Note |
---|
See Xilinx datasheet DS925 for more information about absolute maximum and recommended operating ratings for the Zynq UltraScale+ chips. |
Physical Dimensions
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 5 mm. Please download the step model for exact numbers.
All dimensions are shown in millimeters.
Scroll Title | ||||
---|---|---|---|---|
| ||||
|
Revision History
Hardware Revision History
...
Notes
...
Table 20: Hardware revision history table
Scroll Title | ||||
---|---|---|---|---|
| ||||
Document Change History
HTML |
---|
<!--
Generate new entry:
1.add new row below first
2.Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number
3.Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description.
--> |
...
Date
...
Revision
...
...
...
...
...
...