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- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"
Template Change history: Date | Version | Changes | Author |
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| 4.2 | | ED |
| 4.1 | | ED |
| 4.0 | - Rework for smaller TRM which can be generated faster
- Reduce Signal Interfaces Pin
- Reduce On Board Periphery
- Reduce Power
- Move Configuration Signals from Overview to own section
| JH |
| 3.12 | - Version History
- changed from list to table
- all
- changed title-alignment for tables from left to center
| ma |
| 3.11 | - update "Recommended Operating Conditions" section
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| 3.1 | - New general notes for temperature range to "Recommended Operating Conditions"
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| 3.02 | - add again fix table of content with workaround to use it for pdf and wiki
- Export Link for key features examples
- Notes for different Types (with and without Main FPGA)
- Export Link for Signals, Interfaces and Pins examples
- Notes for different Types (Modul, Modul HyprideHybrid, Evalboard, Carrier)
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| 3.01 | - remove fix table of content and page layout ( split page layout make trouble with pdf export)
- changed and add note to signal and interfaces, to on board periphery section
- ...(not finished)
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| 3.00 | - → separation of Carrier/Module and evaluation kit TRM
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| 2.15 | - add excerpt macro to key features
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| 2.14 | - add fix table of content
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Important General Note:
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Note for Download Link of the Scroll ignore macro: |
Overview
The Trenz Electronic TE0820 is a powerful an industrial/extended 4 x 5 cm industrial/extended module integrated with a Xilinx SoM integrating an AMD Zynq UltraScale+ MPSoC. In addition, the module is equipped with 2x 8 Gb DDR4 SDRAM chip, up to 64 Gb eMMC chip, 2x 512 Mb , DDR4 SDRAM, eMMC memory, flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust Three high-speed connectors provide a large number of inputs and outputs. Additionally, the module provides Gigabit Ethernet and USB2USB 2.0 Transceivers0 transceivers.
The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.
All components cover at least the industrial temperature range. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.
Refer to http://trenz.org/te0820-info for for the current online version of this manual and other available documentation.
Key Features
Key Features
Package: SFVC784/FPGA ZU2 ...ZU5, *- ZU1 / ZU2 / ZU3 / ZU4 / ZU5 1)
- Engine: CG / EG
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, CG, EV, *Speed, , , , 3, *, **Temperature: I, E, *, **- / 3 1)
- Temperature Range: Extended / Industrial 1)
- Package: SFVC784
- RAM/Storage
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2x DDR4 SDRAM,- Data Width: 16 Bit
- Size: 8 Gb, *
- Speed: 2400 Mbps, ***
2x QSPI boot Flash in dual parallel mode- Data Width: 8 Bit
- Size: 512 Mb Gb, *
1x e.MMC Memory- Data Width: 16 Bit
- Size: 8 Gb, *
MAC address serial EEPROMOn Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- Hi-speed USB2 ULPI Transceiver
- 4x LEDS
Interface- 1 Gbps RGMII Ethernet interface
- Hi-speed USB2 ULPI transceiver with full OTG support
- Graphic Processor Mali-400 MP2, *
- 132x High Performance (HP)
- 4 x serial PS GTR transceivers
Power- All power regulators on board
DimensionNote- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
- Rugged for shock and high vibration
- 2 GByte DDR4 SDRAM 2)
- 2 x 64 MByte Serial Flash 3)
- 8 GByte eMMC 3)
- EEPROM with MAC address
- On Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- Hi-speed USB2 ULPI Transceiver
- 10/100/1000 Mbps Ethernet Transceiver
- 4x LEDS
- Interface
- 3 x B2B Connector (LSHM)
- up to 132 PL HP IO
- up to PS 14 MIO
- 4 PS GTR
- ETH (MDI) or SGMII
- USB
- SDIO
- CFG, JTAG
- Power
- 3.3 V power supply via B2B Connector needed 4).
- Dimension
- Notes
1) Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design. 2) Up to 4 GByte are possible with a maximum bandwidth of 2400 MBit/s. 3) Please, take care of the possible assembly options. 4) Higher input voltage may be possible
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Additional assembly options are available for cost or performance optimization upon requestBlock Diagram
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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.
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Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name. Example: TE0812 Block Diagram |
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All created DrawIOs should be named according to the Module name: Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD |
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anchor | Figure_OV_BD |
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title-alignment | center |
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title | TE0820-03 block diagram |
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draw.io Diagram |
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border | false |
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diagramName | TE0820 BD Block Diagram |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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lbox | true |
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diagramWidth | 641 |
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revision | 13 |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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anchor | Figure | anchor | Figure_OV_MC |
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title-alignment | center |
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title | TE0820 -03 main components |
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diagramName | TE0820 MC main components |
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revision | 13 |
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- Xilinx AMD Zynq UltraScale+ MPSoC, U1
- 1.8V, 512 Mbit QSPI flash memory, U71.8V, 512 Mbit QSPI flash memory, U17
- 8 Gbit (512 x 16) DDR4 SDRAM, U2
- 8 Gbit (512 x 16) DDR4 SDRAM, U3
- Marvell Alaska 88E1512 integrated 10/100/1000 Mbps energy efficient ethernet transceiver, U8
- 6A PowerSoC DC-DC converter (PL_VCCINT, 0.85V), U5
- B2B connector Samtec Razor Beam™ LSHM-150, JM1
- B2B connector Samtec Razor Beam™ LSHM-150, JM2
- B2B connector Samtec Razor Beam™ LSHM-130, JM3
- , U3
- eMMC memory, U6
- EEPROM, U25
- Ethernet transceiver, U8
- USB 2.0 ULPItransceiver, U18
- B2B Connector, JM1, JM2, JM38 GByte eMMC memory, U6
- Lattice Semiconductor MachXO2 System Controller CPLD, U21
- I2C programmable, any frequency , any output quad clock Clock generator, U10Highly integrated full featured hi-speed USB 2.0 ULPItransceiver, U18
- LED D1(Red) Done Pin
- LED D2 (Green) CPLD Status, User LED
- LED D3 (Red) PS Error
- Oscillator, U11, U14, U32
- Done LED, D1
- User LED, D2
- Error Out LED, D3
- Error Status LED, D4LED D4 (Green) PS Error Status
Initial Delivery State
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Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title-alignment | center |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style | widths |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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Dual QSPI MemoryNot MemoryNot Not not programmed |
| Programmable Clock Generator |
Not programmed | CPLD (LCMXO2-256HC) | Programmednot programmed |
| EEPROM | not programmed besides factory programmed MAC address |
| System Controller CPLD | programmed | TE0820 CPLD |
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Configuration
Signals
, Interfaces and Pins
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- Overview of Boot Mode, Reset, Enables.
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Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.Connectors
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title-alignment | center |
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title | Boot process.Board Connectors |
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MODE Pin | Boot Mode |
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High | QSPI* |
Low | SD Card* |
*changable also with other CPLD Firmware: TE0820 CPLD
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anchor | Table_OV_RST |
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title-alignment | center |
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title | Reset process. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signal | B2B | I/O | Note |
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EN1 | JM1-28 | Input | CPLD Enable Pin |
RESIN | JM2-18 | Input | General Reset |
Signals, Interfaces and PinsConnector Type | Designator | Interface | IO CNT | Notes |
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B2B | JM1 | ETH - MDI | ETH |
| B2B | JM1 | HP | 48 SE / 24 DIFF |
| B2B | JM1 | MIO | 8 x GPIO |
| B2B | JM1 | SDIO | SDIO or 6 x MIO |
| B2B | JM2 | HP | 68 SE / 33 DIFF |
| B2B | JM2 | CFG | JTAG |
| B2B | JM3 | ETH | SGMII |
| B2B | JM3 | MGT PS | 4 x MGT (RX/TX) |
| B2B | JM3 | MGT PS | MGT CLK |
| B2B | JM3 | CLK | DIFF CLK |
| B2B | JM3 | HP | 16 SE / 8 DIFF |
| B2B | JM3 | USB | USB |
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Test Points
Board to Board (B2B) I/Os
Zynq MPSoC's I/O banks signals connected to the B2B connectors:you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section. Example: Test Point | Signal | Notes1) |
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TP1 | PWR_PL_OK |
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1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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anchor | Table_SIP_B2BTPs |
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title-alignment | center |
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title | General PL I/O to B2B connectors informationTest Points Information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style | widths |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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BankType | B2B Connector | I/O Signal Count | Voltage | Notes | 64 | HP | JM2 | 48x Single Ended, 24x LVDS Pairs | Variable | Max voltage 1.8V | 64 | HP | JM2 | 2x Single Ended | Variable | Max voltage 1.8V | 65 | HP | JM2 | 18x Single Ended, 9x LVDS Pairs | Variable | Max voltage 1.8V | 65 | HP | JM3 | 16x Single Ended, 8x LVDS Pairs | Variable | Max voltage 1.8V | 66 | HP | JM1 | 48x Single Ended, 24x LVDS Pairs | Variable | Max voltage 1.8V | 500 | MIO | JM1 | 8x Single Ended | 1.8V | 501 | MIO | JM1 | 6x Single Ended | 3.3V | 505 | GTR | JM3 | 16x Single Ended, 8x LVDS Pairs | - | 4x Lanes | 505 | GTR CLK | JM3 | 1x differential Clock | - | |
For detailed information about the pin-out, please refer to the Pin-out table.
MGT Lanes
The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:
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anchor | Table_SIP_MGT |
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title-alignment | center |
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title | MGT Lanes connection |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Lane | Bank | Signal Name | B2B Pin | Note |
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0 | 505 | - B505_RX0_P
- B505_RX0_N
- B505_TX0_P
- B505_TX0_N
| | 1 | 505 | - B505_RX1_P
- B505_RX1_N
- B505_TX1_P
- B505_TX1_N
| | 2 | 505 | - B505_RX2_P
- B505_RX2_N
- B505_TX2_P
- B505_TX2_N
| | 3 | 505 | - B505_RX3_P
- B505_RX3_N
- B505_TX3_P
- B505_TX3_N
| | There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.
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anchor | Table_SIP_MGTCLK |
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title-alignment | center |
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title | MGT Clock Sources Information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Clock signal | Bank | Connected to | Notes |
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B505_CLK0_P | 505 | B2B, JM3-31 | Supplied by the carrier board |
B505_CLK0_N | 505 | B2B, JM3-33 | Supplied by the carrier board |
B505_CLK1_P | 505 | U10, CLK2A | On-board Si5338A |
B505_CLK1_N | 505 | U10, CLK2B | On-board Si5338A |
B505_CLK2_P | 505 | N/A | Not connected |
B505_CLK2_N | 505 | N/A | Not connected |
B505_CLK3_P | 505 | U10, CLK1A | On-board Si5338A |
B505_CLK3_N | 505 | U10, CLK1B | On-board Si5338A |
JTAG Interface
JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.
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anchor | Table_SIP_JTG |
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title-alignment | center |
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title | JTAG pins connection |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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JTAG Signal | B2B Connector Pin | Notes |
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TMS | JM2-93 | TDI | JM2-95 | TDO | JM2-97 | TCK | JM2-99 | JTAGEN | JM1-89 | Pulled Low: Xilinx Zynq UltraScale+ MPSoC Pulled High: Lattice MachXO CPLD |
Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.
I2C Addresses
On-board I2C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I2C0 by default. Addresses for on-board I2C slave devices are listed in the table below:
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anchor | Table_SIP_I2C |
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title-alignment | center |
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title | Address table of the I2C bus slave devices |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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I2C Device | I2C Address | Notes |
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PLL Clock Generator, U10 | 0x70/ 0x71 | EEPROM, U25 | 0x50 | MIOs
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anchor | Table_SIP_MIOs |
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title-alignment | center |
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title | MIOs pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Connected to | B2B | Notes |
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0...5 | QSPI Flash, U7 | - | SPI Flash |
7...12 | QSPI Flash, U17 | - | SPI Flash |
13...23 | eMMC, U6 | eMMC | 24 | ETH Transceiver, U8 | - | ETH_RST |
25 | USB2.0 Transceiver, U18 | - | OTG_RST |
26...33 | User MIO | JM1 | 34...37 | N.C | - | N.C |
38...39 | EEPROM, U25 | - | I2C_SDA/SCL |
40...45 | N.C | N.C | 46...51 | SD Card | JM1 | 52...63 | USB2.0 Transceiver, U18 | - | 63...77 | Ethernet Transceiver, U8 | - | Test Points
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title-alignment | center |
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title | Test Points Information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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cellHighlighting | true |
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Test Point | Signal | Connected to | Notes |
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1 | PS_LP0V85 | Voltage Regulator, U12 | 2 | DDR_2V5 | Voltage Regulator, U4 | 3 | PS_AVCC | Voltage Regulator, U9 | 4 | DDR_1V2 | Voltage Regulator, U15 | 5 | PS_AVTT | Voltage Regulator, U3 | 6 | VTT | Regulator, U16 | 7 | PS_FP0V85 | Voltage Regulator, U26 | 8 | VREFA | Regulator, U16 | 10 | PS_PLL | Voltage Regulator, U23 | 11 | PL_VCCINT | Voltage Regulator, U5 | 15 | PL_VCCINT_IO | Voltage Regulator, U27 | 16 | PL_VCU | Voltage Regulator, U24 | On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: #ClockSources, #CPLD, #QuadSPIFlash |
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anchor | Table_OBP |
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title-alignment | center |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Notes |
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QSPI Flash | U7, U17 | EEPROM | U25 | DDR4 SDRAM | U2,U3 | GigaBit Ethernet | U8 | USB2.0 Transceiver | U18 | eMMC Memory | U6 | Oscillators | U32, U14, U11 | Programmable Clock Generator | U10 | CPLD | U21 | LEDs | D1...3 | System Controller CPLD
The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module.
Special purpose pins are connected to System Controller CPLD and have following default configuration:
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anchor | Table_SIP_CPLD |
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title-alignment | center |
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title | System Controller CPLD special purpose pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin Name | Mode | Function | Default Configuration |
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EN1 | Input | Power Enable | No hard wired function on PCB. When forced low, PGOOD goes low without effect on power management |
PGOOD | Output | Power Good | Only indirect used for power status, see CPLD description |
NOSEQ | - | - | No used for Power sequencing, see CPLD description |
RESIN | Input | Reset | Active low reset, gated to POR_B |
JTAGEN | Input | JTAG Select | Low for normal operation, high for CPLD JTAG access |
Please check the entire information at TE0820 CPLD.
See also TE0820 System Controller CPLD page.
eMMC Memory
eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.
DDR4 Memory
The TE0820 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.
- Part number: K4A8G165WB-BIRC
- Supply voltage: 1.2V
- Speed: 2400 Mbps
- Temperature: -40 ~ 95 °C
Quad SPI Flash Memory
Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
Gigabit Ethernet
On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U11).
High-speed USB ULPI PHY
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anchor | Table_SIP_ETH |
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title-alignment | center |
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title | GigaBit Ethernet connection |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Note |
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MDIP0...3 | PHY_MDI0...3 | B2B, JM1 | MDC | ETH_MDC | MIO76 | MDIO | ETH_MDIO | MIO77 | S_IN | S_IN | B2B, JM3 | S_OUT | S_OUT | B2B, JM3 | TXD0..3 | ETH_TXD0...3 | MIO65...68 | TX_CTRL | ETH_TXCTL | MIO69 | TX_CLK | ETH_TXCK | MIO64 | RXD0...3 | ETH_RXD0...3 | MIO71...74 | RX_CTRL | ETH_RXCTL | MIO75 | RX_CLK | ETH_RXCK | MIO70 | LED1 | PHY_LED1 | CPLD, U21 | RESETn | ETH_RST | MIO24 | USB2.0 Transceiver
Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).
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anchor | Table_SIP_USB |
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title-alignment | center |
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title | General overview of the USB PHY signals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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PHY Pin | ZYNQ Pin | B2B Name | Notes |
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ULPI | MIO52..63 | - | Zynq USB0 MIO pins are connected to the USB PHY. |
REFCLK | - | - | 52.000000 MHz from on-board oscillator (U14). |
REFSEL[0..2] | - | - | Reference clock frequency select, all set to GND selects 52.000000 MHz. |
RESETB | MIO25 | - | Active low reset. |
CLKOUT | MIO52 | - | Connected to 1.8V, selects reference clock operation mode. |
DP, DM | - | OTG_D_P, OTG_D_N | USB data lines routed to B2B connector JM3 pins 47 and 49. |
CPEN | - | VBUS_V_EN | External USB power switch active high enable signal, routed to JM3 pin 17. |
VBUS | - | USB_VBUS | Connect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55. |
ID | - | OTG_ID | For an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23. |
Signal | Notes1) |
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TP1 | PS_LP0V85 |
| TP2 | DDR_2V5 |
| TP3 | PS_AVCC |
| TP4 | DDR_1V2 |
| TP5 | PS_AVTT |
| TP6 | VTT |
| TP7 | PS_FP0V85 |
| TP8 | VREFA |
| TP9 | DDR4-TEN | pulled-down to GND | TP10 | PS_PLL |
| TP11 | PL_VCCINT |
| TP12 | PG_ALL | pulled-up to 3.3VIN | TP15 | PL_VCCINT_IO |
| TP16 | PL_VCU |
|
1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection Example: Chip/Interface | Designator | Connected To | Notes |
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ETH PHY | U10 | | Gigabit ETH PHY |
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anchor | Table_OBP |
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title-alignment | center |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Chip/Interface | Designator | Connected To | Notes |
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QSPI Flash | U7, U17 | SoC - PS |
| EEPROM | U25 | SoC - PS |
| DDR4 SDRAM | U2, U3 | SoC - PS |
| GigaBit Ethernet | U8 | SoC - PS, B2B |
| USB2.0 Transceiver | U18 | SoC - PS, B2B |
| eMMC Memory | U6 | SoC - PS |
| Oscillator | U32 | SoC - PS |
| Oscillator | U14 | USB PHY |
| Oscillator | U11 | Clock Generator, ETH PHY |
| Programmable Clock Generator | U10 | SoC - PS, B2B |
| CPLD | U21 | SoC - PS, B2B |
| LED | D1 | SoC - PS | Red, Done LED (see U+ Zynq TRM) | LED | D2 | CPLD | Green, Status LED (see TE0820 CPLD) | LED | D3 | SoC - PS | Red, PS Error LED (see U+ Zynq TRM) | LED | D4 | SoC - PS | Green, PS Error Status LED (see U+ Zynq TRM) |
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Configuration and System Control Signals
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- Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
- In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)
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anchor | Table_OV_CNTRL |
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title-alignment | center |
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title | Controller signal. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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EEPROM
There is a 2Kb EEPROM (U25) provided on the module TE0820.
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anchor | Table_OBP_EEP |
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title-alignment | center |
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title | I2C EEPROM interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | Schematic | U25 Pin | Notes |
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MIO39 | I2C_SDA | SDA | MIO38 | I2C_SCL | SCL | Programmable Clock Generator
There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.
A 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.
Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.
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anchor | Table_OBP_PCLK |
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title-alignment | center |
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title | Programmable Clock Generator Inputs and Outputs |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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cellHighlighting | true |
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U25 Pin | Signal | Connected to | Direction | Note |
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IN0..1 | CLK_IN | JM3 | IN | IN2 | CLK_25M | Oscillator, U11 | IN | SCL | I2C_SCL | EEPROM,U25 | INOUT | SDA | I2C_SDA | EEPROM,U25 | INOUT | CLK0 | CLK0 | JM3 | OUT | CLK1 | B505_CLK3 | FPGA Bank 505 | IN | CLK2 | B505_CLK1 | FPGA Bank 505 | IN | CLK3 | CLK3_N | IN | Clock Sources
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anchor | Table_OBP_CLK |
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title-alignment | center |
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title | Osillators |
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orientation | portrait |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Designator | Description | Frequency | Clock Destination |
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U32 | MEMS Oscillator | 33.33 MHz | U11 | MEMS Oscillator | 25 MHz | U14 | MEMS Oscillator | 52 MHz | LEDs
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anchor | Table_OBP_LED |
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title-alignment | center |
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title | On-board LEDs |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Color | Connected to | Active Level | Note |
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D1 | Red | DONE | Low | D2 | Green | USR_LED | High | D3 | Red | ERR_OUT | High | D4 | Green | ERR_STATUS | High |
Power and Power-on 1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
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Power and Power-On Sequence
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| In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
Power Supply
Power supply with minimum current capability of 3A for system startup is recommended.
Power Consumption |
Enter the default value for power supply and startup of the module here. - Order of power provided Voltages and Reset/Enable signals
Link to Schematics, for power images or more details |
Power Rails
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List of all power rails which are accessible by the customer - Main Power Rails and Variable Bank Power
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anchor | Table_PWR_PCPR |
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title-alignment | center |
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title | Power ConsumptionModule power rails. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style | widths |
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sortByColumn | 1 |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* |
3.3VIN | TBD* |
* TBD - To Be Determined soon with reference design setup.
For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.
Warning |
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To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any Zynq's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence. |
Power Distribution Dependencies
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anchor | Figure_3 |
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title-alignment | center |
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title | Figure 3: TE0820-03 Power Distribution Diagram |
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diagramName | TE0820 power dd distribution diagram |
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diagramDisplayName | lbox | true |
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diagramWidth | 641 |
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revision | 1 |
See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0820 module.
Power Rail Name/ Schematic Name | Connector.Pin | Direction1) | Notes |
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VIN | JM1.1 / JM1.3 / JM1.5 / JM2.2 / JM2.4 / JM2.6 / JM2.8 | IN | Supply voltage from carrier board | 3.3VIN | JM1.13 / JM1.15 | IN | Supply voltage from carrier board | 3.3VIN | JM2.91 | OUT | JTAG reference voltage | +3.3V | JM2.10 / JM2.12 | OUT | Internal +3.3 V voltage level | +1.8V | JM1.39 | OUT | Internal +1.8V voltage level | VCCO_64 | JM2.7 / JM2.9 | IN | HP Bank voltage (max. +1.9 V) | VCCO_65 | JM2.5 | IN | HP Bank voltage (max. +1.9 V) | VCCO_66 | JM1.9 / JM1.11 | IN | HP Bank voltage (max. +1.9 V) | PSBATT | JM1.79 | IN | PS battery supply voltage |
1) Direction: - IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.
|
Recommended Power up Sequencing
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List baseboard design hints for final baseboard development. |
Power-On Sequence
The TE0820 SoM keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.
Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:
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title | Figure 4: TE0820-03 Power-on Sequence DiagramBaseboard Design Hints |
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For highest efficiency of the on-board DC-DC regulators, it is recommended to use one 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.ASC | repeatTableHeaders | default |
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sortByColumn | 1 |
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cellHighlighting | true |
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Sequence | Net name | Recommended Voltage Range | Pull-up/down | Description | Notes |
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0 | - | - | - | Configuration signal setup. | See Configuration and System Control Signals. | 1 1) | 3.3VIN | 3.3 V (± 5 %) | - | Management and SoC power supply. | Main module power supply for management and SoC. 1 A recommended. Power consumption depends mainly on design and cooling solution. | 2 1) | VIN | 3.3 V (± 5 %) 2) OR 5.0 V (± 5 %) 2) | - | Main module power supply. | Main module power supply for management and SoC. 3 A to 7 A recommended. Power consumption depends mainly on design and cooling solution. | 3 | 1.8V | - | - | 1.8 V on-module power supply. |
| 4 | 3.3V | - | - | 3.3 V on-module power supply. |
| 5 | VCCO_64 / VCCO_65 / VCCO_66 | 2) | - | Module bank voltages. | Enable bank voltages after 1.8 V and/or 3.3 V are available on carrier. |
1) In cases where VIN = 3.3VIN = 3.3 V, both voltages can be enabled together. 2) A higher or lower input voltage may be possible. 2) See DS925 for additional information. |
Board to Board Connectors
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- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
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| 6 x 6 SoM LSHM B2B Connectors |
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| 6 x 6 SoM LSHM B2B Connectors |
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|
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Include Page |
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| 4 x 5 SoM LSHM B2B Connectors |
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| 4 x 5 SoM LSHM B2B Connectors |
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|
Technical Specifications
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|
List of all power rails which are accessible by the customer - Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)
|
Absolute Maximum Ratings *)
It is important that all carrier board I/Os are 3-stated at power-on until 3.3V_out or 1.8V_out is present on B2B connector JM2 pins 10 and 12, indicating that all on-module voltages have become stable and module is properly powered up.
See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.
Power Rails
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anchor | Table_PWR_PR |
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title-alignment | center |
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title | Module power rails. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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Power Rail Name on B2B Connector | JM1 Pins | JM2 Pins | Direction | Notes |
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VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board |
3.3V | - | 10, 12 | Output | Internal 3.3V voltage level |
3.3VIN | 13, 15 | - | Input | Supply voltage from the carrier board |
1.8V | 39 | - | Output | Internal 1.8V voltage level |
JTAG VREF | - | 91 | Output | JTAG reference voltage. Attention: Net name on schematic is "3.3VIN" |
VCCO_64 | - | 7, 9 | Input | High performance I/O bank voltage |
VCCO_65 | - | 5 | Input | High performance I/O bank voltage |
VCCO_66 | 9, 11 | - | Input | High performance I/O bank voltage |
Bank Voltages Scroll Title |
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anchor | Table_PWRTS_BVAMR |
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title-alignment | center |
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title | Zynq SoC bank voltages.Absolute maximum ratings |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style | widths |
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cellHighlighting | true |
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FPGA Bank | Schematic | Voltage | Note |
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Bank 24 HD | N.C. | Not Connected | Bank 25 HD | N.C. | Not Connected | Bank 26 HD | N.C. | Not Connected | Bank 44 HD | N.C. | Not Connected | Bank 64 HP | VCCO_64 | Variable | Max voltage 1.8V |
Bank 65 HP | VCCO_65 | Variable | Max voltage 1.8V |
Bank 66 HP | VCCO_66 | Variable | Max voltage 1.8V |
Bank 500 PSMIO | VCCO_PSIO0_500 | 1.8V | Bank 501 PSMIO | VCCO_PSIO1_501 | 3.3V | Bank 502 PSMIO | VCCO_PSIO2_502 | 1.8V | Bank 503 PSCONFIG | VCCO_PSIO3_503 | 1.8V | Bank 504 PSDDR | DDR_1V2 | 1.2V |
Board to Board Connectors
Page properties |
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|
This section is optional and only for modules.use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors Include Page |
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6 x 6 SoM LSHM B2B Connectors | 6 x 6 SoM LSHM B2B Connectors | Include Page |
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4 x 5 SoM LSHM B2B Connectors | 4 x 5 SoM LSHM B2B Connectors | Technical Specifications
Absolute Maximum Ratings
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anchor | Table_TS_AMR |
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title-alignment | center |
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title | PS absolute maximum ratings |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Notes |
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VIN supply voltage | -0.3 | 7 | V | See EN6347QI and TPS82085SIL datasheets |
3.3VIN supply voltage | -0.1 | 3.630 | V | Xilinx DS925 and TPS27082L datasheet |
PS I/O supply voltage, VCCO_PSIO | -0.5 | 3.630 | V | Xilinx document DS925 |
PS I/O input voltage | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx document DS925 |
HP I/O bank supply voltage, VCCO | -0.5 | 2.0 | V | Xilinx document DS925 |
HP I/O bank input voltage | -0.55 | VCCO + 0.55 | V | Xilinx document DS925 |
PS GTR reference clocks absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 |
PS GTR absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 |
Voltage on SC CPLD pins | -0.5 | 3.75 | V | Lattice Semiconductor MachXO2 datasheet |
Storage temperature | -40 | +85 | °C | See eMMC datasheet |
Recommended Operating Conditions
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anchor | Table_TS_ROC |
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title-alignment | center |
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title | Recommended operating conditions. |
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orientation | portrait |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Parameter | Min | Max | Units | Notes |
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VIN supply voltage | 3.3 | 6 | V | See TPS82085S datasheet |
3.3VIN supply voltage | 3.3 | 3.465 | V | See LCMXO2-256HC, Xilinx DS925 datasheet |
PS I/O supply voltage, VCCO_PSIO | 1.710 | 3.465 | V | Xilinx document DS925 |
PS I/O input voltage | –0.20 | VCCO_PSIO + 0.20 | V | Xilinx document DS925 |
HP I/O banks supply voltage, VCCO | 0.950 | 1.9 | V | Xilinx document DS925 |
HP I/O banks input voltage | -0.20 | VCCO + 0.20 | V | Xilinx document DS925 |
Voltage on SC CPLD pins | -0.3 | 3.6 | V | Lattice Semiconductor MachXO2 datasheet |
Operating Temperature Range | 0 | 85 | °C | Xilinx document DS925, extended grade Zynq temperarure range |
Physical Dimensions
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|
In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.
For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
Power Rail Name/ Schematic Name | Description | Min | Max | Unit |
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VIN | Supply voltage | -0.3 | 7 | V | 3.3VIN | Supply voltage | -0.3 | 3.75 | V | VCCO_64 | I/O bank voltage | -0.5 | 2.0 | V | VCCO_65 | I/O bank voltage | -0.5 | 2.0 | V | VCCO_66 | I/O bank voltage | -0.5 | 2.0 | V | PSBATT | RTC / BBRAM | -0.5 | 2.0 | V |
|
*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.
Recommended Operating Conditions
This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
- Variants of modules are described here: Article Number Information
- Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
- Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
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anchor | Table_TS_ROC |
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title-alignment | center |
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title | Recommended operating conditions. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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Parameter | Min | Max | Units | Reference Document |
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VIN 1) | 3.135 OR 4.75 | 3.465 OR 5.25 | V
V |
| 3.3VIN | 3.135 | 3.465 | V |
| VCCO_64 | 0.950 | 1.900 | V | See FPGA datasheet. | VCCO_65 | 0.950 | 1.900 | V | See FPGA datasheet. | VCCO_66 | 0.950 | 1.900 | V | See FPGA datasheet. | PSBATT | 1.200 | 1.500 | V | See FPGA datasheet. |
1) Higher values may possible. For more information consult schematic and according datasheets. |
Physical Dimensions
PCB thickness: 1.66 mm (± 10 %).
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title | Physical Dimension |
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diagramName | TE0820_TS_PD PD |
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revision | 3 |
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| Image Added
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Currently Offered Variants
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anchor | Table_VCP_SO |
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title-alignment | center |
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title | Trenz Electronic Shop Overview |
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orientation | portrait |
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repeatTableHeaders | default |
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Revision History
Hardware Revision History
Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 5 mm. Please download the step model for exact numbers.
All dimensions are shown in millimeters.
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title | Physical Dimension |
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Image Removed
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Currently Offered Variants
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anchor | TableFigure_VCP_SO6 |
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title-alignment | center |
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title | Trenz Electronic Shop Overview Figure 6: Module hardware revision number |
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tablelayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlighting |
Trenz shop TE0820 overview page |
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English page | German page |
Revision History
Hardware Revision History
Page properties |
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|
Set correct links to download Carrier, e.g. TE0706 REV02:
TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents
Note:
Date format: YYYY-MM-DDExample:
Date | Revision | Changes | Documentation Link |
---|
2020-11-25 | REV02 | - Resistors R14 and R15 was replaced by 953R (was 5K1)
- Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
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diagramWidth | 260 |
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revision | 2 |
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| Image Added
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REV02
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anchor | Table_RH_HRH |
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title-alignment | center |
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title | Hardware Revision History |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default | style |
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widths | sortByColumn | 1 |
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cellHighlighting | true |
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Date | Revision | Changes | Documentation Link |
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2020-08-14 | 04 | - Fixed DDR4 connection (BG1), support B-die DDR4 Industrial grade chips
- Added R93, changed value C62, change obsolete U28
- Added R89 (10R)
- Added additional caps 4.7uF to PS_AVTT/PS_AVCC (Xilinx doc UG583)
- Changed R51 20k ->10K (PS_AVCC = 0.85V, Xilinx doc DS925 v1.17)
- Fixed DDR4 connection (Alert)
- Added 3.3V signal to CPLD
- Added testpoints
- LIB components update
| PCN-20200616 | TE0820-4 | 2019-01-02 | 03 | - Fixed VCU connection: add additional DCDC (0.9V)
- LIB components update
- Change package 1K resistors (0402 -> 0201)
- Added LEDs (1x user LED, 1x LED for ERR_STATUS, 1xLED for ERR_OUT)
- Change obsolete 2xSPI Flash (256MBit) -> 2xSPI Flash (512MBit)
- Added additional DCDCs (PL_VCCINT_IO, PS_FP0V85)
- Changed DCDC (U5) 6A (optional 4A)
| PCN-20190110 | TE0820-03 | 2017-08-17 | 02 | - Added MAC EEPROM (slave address)
- LIB components update
- Fixed SD Card connection
- Fixed sense connection from DCDC
- Made correct power connection for VCU (removed DCDC, added resistors and caps like as Xilinx recommended)
- Added resistors for variants (ZU+ with/without VCU)
- Added termination resistors (240R) to VRP pins fro all HP-banks
| PCN-20171117 | TE0820-02 | 2016-12-23 | 01 | Prototype only | - | TE0820-01 | |
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Image Removed2022-06-22 | 05 | - Changed EOL ferrite beads L1..5,L7,L9..12.
- Changed EOL DCDC U5 (EN6363QI -> MPM3860GQW-Z).
- Changed EOL load switch U28 (TPS27082LDDCR -> MP5077GG-Z ).
- Added additional decoupling capacitors and changed caps 4.7uF to 10uF (AMD doc UG583 v1.23).
- Added pull-down and testpoint to TEN DDR4 signal.
- Changed EOL transistor T1 (AO7800 -> BSD840NH6327XTSA1).
- Added voltage detector U30 (BD39040MUF-CE2).
- Changed EOL eMMC U6 (MTFC4GACAJCN-4M -> SDINBDG4-8G-XI2).
- Changed EOL MEMS U14 (SiT8008AI-73-XXS-52.000000E -> SiT8008BI-73-XXS-52.000000E).
- Added signal PG_ALL (U30) to CPLD (pin5).
- Added option (depends assembly variants, for all assembly variants R128 set as populated, instead special inquiry) signal POR_B through R128, T2 to CPLD (pin27).
- Added option (depends assembly variants, for all assembly variants R95 set as DNP, instead special inquiry) signal EN1 through R95 to DCDC U5.
- Added option (depends assembly variants, for all assembly variants U29 and R129 set as populated, instead special inquiry) signal PHY_LED1 through level translator U29 to FPGA (U1.K7).
- Added resistors R130 & R131 (select Power-on delay override, for all assembly variants R130 set as DNP -> Standard PL Power-on delay time).
- Added diode D5.
- Added Power Diagram sheet.
- LIB components update.
| TE0820-05 | 2020-08-14 | 04 | - Fixed DDR4 connection (BG1), support B-die DDR4 Industrial grade chips.
- Added R93, changed value C62, change obsolete U28.
- Added R89 (10R).
- Added additional caps 4.7uF to PS_AVTT/PS_AVCC (AMD doc UG583).
- Changed R51 20k ->10K (PS_AVCC = 0.85V, AMD doc DS925 v1.17).
- Fixed DDR4 connection (Alert).
- Added 3.3V signal to CPLD.
- Added testpoints.
- LIB components update.
| TE0820-04 | 2019-01-02 | 03 | - Fixed VCU connection: add additional DCDC (0.9V).
- LIB components update.
- Change package 1K resistors (0402 -> 0201).
- Added LEDs (1x user LED, 1x LED for ERR_STATUS, 1xLED for ERR_OUT).
- Change obsolete 2xSPI Flash (256MBit) -> 2xSPI Flash (512MBit).
- Added additional DCDCs (PL_VCCINT_IO, PS_FP0V85).
- Changed DCDC (U5) 6A (optional 4A).
| TE0820-03 | 2017-08-17 | 02 | - Added MAC EEPROM (slave address).
- LIB components update.
- Fixed SD Card connection.
- Fixed sense connection from DCDC.
- Made correct power connection for VCU (removed DCDC, added resistors and caps like as AMD recommended).
- Added resistors for variants (ZU+ with/without VCU).
- Added termination resistors (240R) to VRP pins fro all HP-banks.
| TE0820-02 | 2016-12-23 | 01 | Prototype | TE0820-01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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dateFormat | yyyy-MM-dd |
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| - Updated to new TRM style
- Updated for REV05
| | | | | 2021-12-17 | v.99 | Vadim Yunitski | - Corrected 'Bank voltages' table
| 2021-07-14 | v.98 | John Hartfiel | | 2021-07-05 | v.97 | John Hartfiel | | 2020-09-18 | v.95 | Pedram Babakhani | - Update to REV04
- Update the TRM format
- Technical Information update
| 2020-03-16 | v.87 | John Hartfiel | - Corrected PLL section
- Corrected Designators USB, ETH PHY, CLK section
| 2020-02-03 | v.85 | Martin Rohrmüller | - Corrected #MIOs for QSPI and USB in block diagram
| 2019-11-28 | v.81 | Martin Rohrmüller | - typo and designator in section USB interface corrected
| 2019-10-30 | v.80 | John Hartfiel | | 2019-09-17 | v79 | Martin Rohrmüller | - Updated according to PCN-20190110: eMMC, QSPI-Flash
| | v.78 | Martin Rohrmüller | - Corrected PJTAG Mio Pin29 in table 8
| 2019-05-08 | v.77 | John Hartfiel | - Corrected EEPROM I2C Address
- Correction USB PHY connection
| | v.74 | John Hartfiel | | | v.73 | John Hartfiel | - typo correction
- update CPLD section
- add LEDs to component list
- add 3D picture of REV03 instead of REV01 picture
| | v.69 | Ali Naseri | | | v.61 | John Hartfiel | - Rework chapter currently available products
- add PJTAG note to MIOtable
| 2018-03-12 | v.54 |
| - Correction Power Rail Section
| 2017-11-20 | v.51 | John Hartfiel | - Correction Default MIO Configuration Table
| 2017-11-10 | v.50 | John Hartfiel | - Replace B2B connector section
| 2017-10-18 | v.49 | John Hartfiel | | 2017-09-25 | v.48 | John Hartfiel | - Correction in the "Board to Board (B2B) I/Os" section
- Update in the "Variants Currently In Production" section
| 2017-09-18 | v.47 | John Hartfiel | | 2017-08-30 | v.46 | Jan Kumann | | | | John Hartfiel | - Correction in the "Key Features" section.
| 2017-08-21 | v.34 | John Hartfiel | - "Initial delivery state" section updated.
| 2017-08-21 | v.33 | Jan Kumann | - HW revision 02 block diagram added.
- Power distribution and power-on sequence diagram added.
- System Controller CPLD and DDR4 SDRAM sections added.
- TRM update to the template revision 1.6
- Weight section removed.
- Few minor corrections.
| | | John Hartfiel | - Style changes
- Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
- Correction of MIO SD Pin-out, System Controller chapter
- Update and new sub-sections on "On Board Peripherals and Interfaces" sections
| 2017-08-07 | v.5 | Jan Kumann | | -- | all | Page info |
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Table 21: Document change history
Disclaimer
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| IN:Legal Notices |
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| IN:Legal Notices |
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