Page History

...

• Mini-ITX form factor, PC Enclosure
• ATX power supply connector
• Optional 12V standard power plug
• Headers
  • Intel 10-pin HDA Audio
  • Intel 9-pin Power-/Reset-Button, Power-/HD-LED
  • PC-BEEPER
• On-board Power- / Reset-Switches
• 2x Configuration 4-bit DIP-switches
• 2x Optional 4-wire PWM fan connectors
• PCIe Slot - one PCIe lane (16 lane connector)
• CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
• 4x On-board configuration EEPROMs (1x Microchip 24LC128-I/ST, 3x  Microchip 24AA025E48T-I/OT)
• Dual SFP+ Connector (2x1 Cage)
• One Display-Port (single lane)
• One SATA Connector
• 2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
• 1x USB3.0 on-board header with two ports
• FMC HPC Slot (FMC_VADJ max. VCCIO)
• FMC Fan
• Gigabit Ethernet RGMII PHY with RJ45 MegJack
• All Carrier Board peripherals' I²C-interfaces muxed to MPSoC's I²C-interface on PS bank 503
• Quad programmable PLL clock generator SI5338A
• 2x SMA coaxial connectors for clock signals
• MicroSD- / MMC-Card Socket (bootable)
• 32 Gbit on-board eMMC memory (8 banks a 4 Gbit)
• Two System Controller CPLDs Lattice MachXO2 1200 HC
• One Samtec FireFly (4 GT lanes bidirectional)
• One Samtec FireFly connector for reverse loopback
• 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLDs
• 20 Pin ARM JTAG Connector (PS JTAG0)
• 3x PMOD connector (GPIO's and I²C interface to SC CPLDs / MPSoC module
• Carrier SC CPLD managing power-up sequence of MPSoC module
• On-board DCDC PowerSoCs

...

1. PMOD connector, P2
2. MicroSD Card socket (on bottom side), J16
3. Display Port socket, J13
4. USB3.0 A 2x , RJ45 1x (stacked), J7
5. SFP+ 2x1 cage, J14
6. PCIe x16 connector (one PCIe lane connected), J11
7. FMC HPC, J5
8. FMC-Fan connector 5V, J19
9. USB3.0 connector, J8
10. PC-BEEPER 4-pin header, J23
11. SMA coaxial connector (SI5338A clock output), J32
12. SMA coaxial connector (clock input to MPSoC module), J33
13. eMMC Card socket, J27
14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
18. CAN bus 6-pin header, J29
19. CAN bus 10-pin connector, J24
20. ARM-JTAG  20-pin connector, J30
21. ATX power supply connector, J20
22. 4-Wire PWM fan connector, J35
23. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to MPSoC module, J12
24. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to System Controller CPLDs, J28
25. Power Jack 2.1mm 12V, J25
26. 4x 4-bit DIP-switch, S5
27. Power Button, S1
28. Samtec FireFly Connector  for reverse loopback, J21/J22
29. Samtec FireFly Connector (4 GT lanes bidirectional), J6/J15
30. SATA Header, J31
31. 4-Wire PWM fan connector, J26
32. Programmable on-module PLL I²C interface 10-pin header, J17
33. Reset Button, S2
34. INTEL HDA 9-pin header, J9
35. Intel front panel (PWR-/RST-Button, HD-/PWR-LED) 9-pin header, J10
36. Samtec FireFly Connector J6/J15 I²C interface 3-pin header, J34
37. 4x 4-bit DIP-switch, S4
38. PMOD connector, P3
39. PMOD connector, P1
40. Battery Holder CR1220, B1

...

Table 1: Initial Delivery State of the flash memories

Signals, Interfaces and Pins

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Connections and Interfaces or B2B Pin's which are accessible by User
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Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector:

...

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the I/O's MIOx, MIOx ... MIOx, ... are depending on the base-board peripherals connected to these pins.

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TO-DO (future):
If Vivado board part files are available for this module, the standard configuration of the MIO pins by using this board part files should be mentioned here. This standard configuration of those pins are also apparent of the on-board peripherals of base-boards related to the module.
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MGT Lanes

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MGT Lanes should be separately listed, as those are more specifically not just I/O's.  
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...

MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21
MGT_TX4_P, MGT_TX4_N, pins J1-22, J1-20

MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15
MGT_TX5_P, MGT_TX5_N, pins J1-16, J1-14

MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9
MGT_TX6_P, MGT_TX6_N, pins J1-10, J1-8

MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5
MGT_TX7_P, MGT_TX7_N, pins J1-4, J1-6

...

1 Reference clock MGT_CLK3 from programmable
quad clock generator U16 to bank's pins AA6/AA5.

1 Reference clock MGT_CLK2 from B2B connector J3
(pins J3-81, J3-83) to bank's pins W6/W5.

FMC HPC Connector

The FMC (FPGA Mezzanine Card) connector J5 with high pin count (HPC) provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.

The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are usable as LVDS-pairs.

The I/O signals are routed from the FPGA banks as LVDS-pairs to the connector:

Table 2: FMC connector pin-outs of available logic banks of the MPSoC

The MGT-banks have also clock input-pins which are exposed to the FMC connector. Following MGT-lanes are available on the FMC connectors J5:

Table 2: FMC connector pin-outs of available MGT-lanes of the MPSoC

The FMC connector provides pins for reference clock output to the Mezzanine module:

Table 3: FMC connector pin-outs for reference clock output

The FMC connector provides further interfaces like 'JTAG' and 'I²C' to the System Controller CPLD:

Table 4: FMC connector pin-outs of available interfaces to the System Controller CPLD

Several VCCIO voltages are available on the FMC connector to operate the I/O's in order of the intended purpose:

Table 5:  Available VCCIO voltages on FMC connector

USB3.0 Interface

The TEBF0808 Carrier Board offers up to 4 USB3.0 superspeed ports, which are also downward compatible to USB2.0 highspeed ports. The USB3.0 ports are provided by the IC U4, Cypress Semiconductor CYUSB3324 4-port USB3.0 Hub.

On the Upstream-side, this chip is connected to the MGT1-lane of MPSoCs bank 505 to establish the USB3.0 lane. For the USB2.0 interface, the USB3.0 HUB U4 is connected to the on-board USB2.0 PHY U9.

Following block-diagram clarifies the wiring of the USB interface with the MPSoC.

MIO62..63 USB ULPI

JTAG Interface

JTAG access to the ... is provided through B2B connector .... 

...

JTAG Signal

...

B2B Connector Pin

...

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

...

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For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitfile of the SC CPLD.
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Quad SPI Interface

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

...

Gigabit Ethernet

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

...

USB Interface

USB PHY is provided with ...

...

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:

...

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.

...

MODE Signal State

...

high or open

...

SD Card

...

low or ground

...

QSPI

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I²C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

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Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I²C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL...

Programmable PLL Clock (Phase-Locked Loop)

There is a Silicon Labs I²C programmable quad PLL clock generator Si5338A (U..) ..

...

IN1/IN2

...

CLKIN_P, CLKIN_N

...

Reference clock signal from B2B connector J3, pins J3-74, J3-76
(base board decoupling capacitors and termination resistor necessary).

...

IN3

...

reference clock signal from oscillator SiTime SiT8008BI (U21)

...

IN4/IN6

...

IN5

...

not connected

...

CLK0 A/B

...

MGTCLK1_P, MGTCLK1_N

...

Reference clock signal to MGT bank 112, pins U6/U5
(100 nF decoupling capacitors).

...

MGTCLK3_P, MGTCLK3_N

...

Reference clock signal to MGT bank 111, pins AA6/AA5
(100 nF decoupling capacitors).

Oscillators

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

...

On-board LEDs

...

Power and Power-On Sequence

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Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

...

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.

Power Distribution Dependencies

regulator dependencies and max. current.

put diagram here...

See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Power-On Sequence Diagram

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

put diagram here...

Voltage Monitor Circuit

if this circuit is fitted on module, describe it here...

Power Rails

...

Voltages on B2B-Connectors

...

B2B

...

B2B

...

B2B

...

Input / Output

...

Bank Voltages

...

Bank

...

Voltage

...

Voltage Range

...

Board to Board Connectors

...

Variants Currently In Production

...

SoC Junction Temperature

...

Technical Specifications

Absolute Maximum Ratings

...

Parameter

...

Units

...

Reference Document

...

VIN supply voltage

...

V

...

Storage temperature

...

...

°C

...

Recommended Operating Conditions

...

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

• Module size: ... mm × ... mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard connectors: ... mm.

• PCB thickness: ... mm.

• Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

 Put mechanical drawings here...

Revision History

Hardware Revision History

...

Notes

...

01

...

Prototypes

...

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Put pic of PCB silk screen here showing model and revision ...

Document Change History

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...

Date

...

Revision

...

Contributors

...

Description

...

John Hartfiel

...

-removed weight section update template version

...

2017-06-08

...

v.20

...

John Hartfiel

...

add revision number and update document change history

...

2017-05-30

...

v.1

...

Jan Kumann

...

Initial document.

...

all

...

Jan Kumann, John Hartfiel

...

Disclaimer

...

...

Table of contents

Features

• Mini-ITX form factor
• ATX Power supply connector (Important 12V only Supply Required)
• optional 12V Standard Power Plug
• USB3 with USB3 HUB
• Gigabit Ethernet RJ45
• MicroSD Card (bootable)
• eMMC (bootable)
• PCIe slot - one PCIe lane (16 Lane Connector)
• Displayport Single Lane
• One SATA Connector
• FMC HPC Slot (1.8V max VCCIO)
• Dual SFP+
• One Samtec FireFly (4 GT lanes bidir)
• One Samtec FireFly connector for reverse loopback
• Fan connectors, PC Enclosure, FMC Fan
• Intel front panel connector (PWR/RST/LED)
• Intel HDA Audio connector
• CAN FD Transceiver (10 Pin IDC Connector)
• 20 Pin ARM JTAG Connector (PS JTAG0)

PC Enclosure Rear Panel Accessible I/O

• PCIe accepting 16 Lane PCIe cards (one lane used PS GT)
• FMC HPC
• Dual SFP+
• RJ45 Gigabit Ethernet
• 2x USB3 Host
• Displayport (Single lane)
• microSD
• Two LED's
• CAN FD (using DB9 to IDC10 Cable)
• One PMOD

PC Front Panel I/O

• Reset Button
• Power Button
• Power LED
• HD LED
• Intel HDA Audio
• One USB2 HS Host port
• One USB3 SS Host port

The above I/O interfaces are accessible using standard PC front panel cables.

...

Image RemovedTEBF0808-REV2 Component Locations

TEBF0808-REV2 Component Locations

...

Table: Board Component Description

TE0808 GT Transceivers

...

GT Lane Assignment

...

GT CLK Assignment

TE0808 MIO Assignment

...

MIO Assignment

TE0808 Si5345 PLL Settings

...

Recommended/Default settings for the Si5345

FMC Slot

FMC Slot is fitted as full FMC HPC.

Note: FMC VADJ maximum voltage is 1.8V (as HP banks do not support more than 1.8V).

...

Optional FAN can be mounted below the FMC slot. Ther are no components below the FMC card, so FMC cards with extended component heights can be used.

I2C Buses

...

1

...

4

...

List of I2C buses and devices (bus numbers as enumerated by Linux).

To init Si5345 use command

si534x /dev/i2c-13 0x69

DIP Switches

There are two 4 bit DIP Switches on the TEBF0808, they must be used to select some options. On TEBF0808-02 default CPLD-Firmware selects boot from SD-Card, Firmware update is needed for Boot-Mode selection.

...

DIP Switch S5 located close to PWR push-button. This DIP Switch is connected to the two baseboard control CPLD's.

...

DIP Switch S4 located close to PCIe slot.

LEDs

...

Power

ATX Power is supported but special 12V ATX power supply must be used.

System controller RGPIO 

Master CPLD Read

...

Bit

...

Master CPLD Write

...

Bit

...

Slave CPLD Read

...

Bit

...

Slave CPLD Write

...

Bit

...

PCB Revisions

Revision 02

Known Issues:

...

Revision 03