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Table of Contents

Overview

 

The Trenz Electronic TEBF0808 Carrier Board is a baseboard for the Xilinx Zynq Ultrascale+ MPSoC modules TE0808 and TE0803, which exposes the module's B2B connector pins to accessible connectors and provides a whole range of on-board components to test and evaluate the Zynq Ultrascale+ SoMs and for developing purposes.

Key Features

  • Mini-ITX form factor, PC Enclosure
  • ATX power supply connector
  • Optional 12V standard power plug
  • Headers
    • Intel 10-pin HDA Audio
    • Intel 9-pin Power-/Reset-Button, Power-/HD-LED
    • PC-BEEPER
  • On-board Power- / Reset-Switches
  • 2x Configuration DIP-switches
  • 2x Optional 4-wire PWM fan connectors
  • PCIe Slot - one PCIe lane (16 lane connector)
  • CAN FD Transceiver (10 Pin IDC connector and 6-pin header)
  • 4x On-board configuration EEPROMs
  • Dual SFP+ Connector (2x1 Cage)
  • One Display-Port (single lane)
  • One SATA Connector
  • 2x USB3.0 A Connector (Superspeed Host Port (Highspeed at USB2.0))
  • 1x USB3.0 on-board header with two ports
  • FMC HPC Slot (FMC_VADJ max. VCCIO)
  • FMC Fan
  • Gigabit Ethernet RGMII PHY with RJ45 MegJack
  • All Carrier Board peripherals' I²C-interfaces muxed to MPSoC's I²C-interface on PS bank 503
  • Quad programmable PLL clock generator SI5338A
  • 2x SMA coaxial connectors for clock signals
  • MicroSD- / MMC-Card Socket (bootable)
  • 32 Gbit on-board eMMC memory (8 banks a 4 Gbit)
  • Two System Controller CPLDs Lattice MachXO2 1200 HC
  • One Samtec FireFly (4 GT lanes bidirectional)
  • One Samtec FireFly connector for reverse loopback
  • 2x JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for programming MPSoC and SC CPLDs
  • 20 Pin ARM JTAG Connector (PS JTAG0)
  • 3x PMOD connector (GPIO's and I²C interface to SC CPLDs / MPSoC module
  • Carrier SC CPLD managing power-up sequence of MPSoC module
  • On-board DCDC PowerSoCs

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TEBF0808-04 Block Diagram

Main Components

Figure 2: TEBF0808-04 Carrier Board

  1. PMOD connector, P2
  2. MicroSD Card socket (on bottom side), J16
  3. Display Port socket, J13
  4. USB3.0 A 2x , RJ45 1x (stacked), J7
  5. SFP+ 2x1 cage, J14
  6. PCIe x16 connector (one PCIe lane connected), J11
  7. FMC HPC, J5
  8. FMC-Fan connector 5V, J19
  9. USB3.0 connector, J8
  10. PC-BEEPER 4-pin header, J23
  11. SMA coaxial connector (SI5338A clock output), J32
  12. SMA coaxial connector (clock input to MPSoC module), J33
  13. eMMC Card socket, J27
  14. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
  15. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
  16. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
  17. Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
  18. CAN bus 6-pin header, J29
  19. CAN bus 10-pin connector, J24
  20. ARM-JTAG  20-pin connector, J30
  21. ATX power supply connector, J20
  22. 4-Wire PWM fan connector, J35
  23. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to MPSoC module, J12
  24. JTAG/UART header ('XMOD FTDI JTAG Adapter'-compatible) for access to System Controller CPLDs, J28
  25. Power Jack 2.1mm 12V, J25
  26. 4x DIP-switch, S5
  27. Power Button, S1
  28. Samtec FireFly Connector  for reverse loopback, J21/J22
  29. Samtec FireFly Connector (4 GT lanes bidirectional), J6/J15
  30. SATA Header, J31
  31. 4-Wire PWM fan connector, J26
  32. Programmable on-module PLL I²C interface 10-pin header, J17
  33. Reset Button, S2
  34. INTEL HDA 9-pin header, J9
  35. Intel front panel (PWR/RST/LED) 9-pin header, J10
  36. Samtec FireFly Connector J6/J15 I²C interface 3-pin header, J34
  37. 4x DIP-switch, S4
  38. PMOD connector, P3
  39. PMOD connector, P1
  40. Battery Holder CR1220, B1

Initial Delivery State

Storage device name

Content

Notes

 

Not programmed

-
 Not programmed-
Si5345A programmable PLL NVM OTPNot programmed-
 Not programmed-
 Not programmed-
 Not programmed-

Table 1: Initial Delivery State of the flash memories

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

I/O signals connected to the SoCs I/O bank and B2B connector:

BankTypeB2B ConnectorI/O Signal CountLVDS Pairs CountBank VoltageNotes
       

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

For detailed information about the pin out, please refer to the Pin-out Tables. 

The configuration of the I/O's MIOx, MIOx ... MIOx, ... are depending on the base-board peripherals connected to these pins.

 

 

MGT Lanes

 

 

BankTypeLane CountB2B ConnectorSchematic Names / Connector PinsFPGA Pin NameMGT Bank's Reference Clock Inputs
111GTX4J1

MGT_RX4_P, MGT_RX4_N, pins J1-23, J1-21
MGT_TX4_P, MGT_TX4_N, pins J1-22, J1-20

MGT_RX5_P, MGT_RX5_N, pins J1-17, J1-15
MGT_TX5_P, MGT_TX5_N, pins J1-16, J1-14

MGT_RX6_P, MGT_RX6_N, pins J1-11, J1-9
MGT_TX6_P, MGT_TX6_N, pins J1-10, J1-8

MGT_RX7_P, MGT_RX7_N, pins J1-3, J1-5
MGT_TX7_P, MGT_TX7_N, pins J1-4, J1-6

 

1 Reference clock MGT_CLK3 from programmable
quad clock generator U16 to bank's pins AA6/AA5.

1 Reference clock MGT_CLK2 from B2B connector J3
(pins J3-81, J3-83) to bank's pins W6/W5.

JTAG Interface

JTAG access to the ... is provided through B2B connector .... 

JTAG Signal

B2B Connector Pin

TCK 
TDI 
TDO 
TMS 

System Controller I/O Pins

Special purpose pins are connected to smaller System Controller CPLD and have following default configuration:

Pin NameModeFunctionB2B Connector PinDefault Configuration
PGOODOutputPower GoodJ1-148Active high when all on-module power supplies are working properly.
JTAGENInputJTAG SelectJ2-131Low for normal operation.

Quad SPI Interface

Quad SPI Flash (U14) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO1 ... MIO6.

MIOSignal NameU14 Pin
1SPI-CSC2
2SPI-DQ0/M0D3
3SPI-DQ1/M1D2
4SPI-DQ2/M2C4
5SPI-DQ3/M3D4
6SPI-SCK/M4B2

Gigabit Ethernet

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

PHY PinPSPLB2BNotes
     

USB Interface

USB PHY is provided with ...

PHY PinPinB2B NameNotes
    

The schematics for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.

I2C Interface

On-board I2C devices are connected to MIO.. and MIO.. which are configured as I2C... by default. I2C addresses for on-board devices are listed in the table below:

I2C DeviceI2C AddressNotes
   

Boot Process

By default the ... supports QSPI and SD Card boot modes which is controlled by the MODE input signal from the B2B connector.

MODE Signal State

Boot Mode

high or open

SD Card

low or ground

QSPI

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U2) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and I2C between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller CPLD.

Other tasks of the System Controller CPLD are the monitoring of the power-on sequence and to display the programming state of the FPGA module.

For detailed information, refer to the reference page of the SC CPLD firmware of this module.

Quad SPI Flash Memory

On-board QSPI flash memory (U14) on the TE0745-02 is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

SPI Flash QE (Quad Enable) bit must be set to high or FPGA is unable to load its configuration from flash during power-on. By default this bit is set to high at the manufacturing plant.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U9), the 125MHz output clock signal CLK_125MHZ is connected to the pin J2-150 of B2B connector J2.

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO28..39, bank 501 (see also section). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U23) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x53.

RTC - Real Time Clock

An temperature compensated Intersil ISL...

Programmable PLL Clock (Phase-Locked Loop)

There is a Silicon Labs I2C programmable quad PLL clock generator Si5338A (U..) ..

Si5338A (U13) InputSignal Schematic NameNote

IN1/IN2

CLKIN_P, CLKIN_N

Reference clock signal from B2B connector J3, pins J3-74, J3-76
(base board decoupling capacitors and termination resistor necessary).

IN3

reference clock signal from oscillator SiTime SiT8008BI (U21)

25.000000 MHz fixed frequency.

IN4/IN6

pins put to GNDLSB (pin 'IN4') of the default I²C-adress 0x70 not activated.

IN5

not connected

-
Si5338A (U13) Output
Signal Schematic NameNote

CLK0 A/B

MGTCLK1_P, MGTCLK1_N

Reference clock signal to MGT bank 112, pins U6/U5
(100 nF decoupling capacitors).

CLK3 A/B

MGTCLK3_P, MGTCLK3_N

Reference clock signal to MGT bank 111, pins AA6/AA5
(100 nF decoupling capacitors).

Oscillators

The SoC module has following reference clocking signals provided by external baseboard sources and on-board oscillators:

Clock SourceSchematic NameFrequencyClock Input Destination
SiTime SiT8008BI oscillator, U21-25.000000 MHzQuad PLL clock generator U16, pin 3

On-board LEDs

LED ColorConnected toDescription and Notes
    

Power and Power-On Sequence

Power Consumption

The maximum power consumption of a module mainly depends on the design which is running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Power Input PinTypical Current
VINTBD*
3.3VINTBD*

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of on board DC-DC regulators it is recommended to powering the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared.

To avoid any damage to the SoC module, check for stabilized on-board voltages in steady state before powering up the SoC's I/O bank voltages VCCO_x. All I/O's should be tri-stated during power-on sequence.

Power Distribution Dependencies

regulator dependencies and max. current.

put diagram here...

See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Power-On Sequence Diagram

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DCDC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

put diagram here...

Voltage Monitor Circuit

if this circuit is fitted on module, describe it here...

Power Rails

Voltages on B2B-Connectors

B2B

B2B

B2B

Input / Output

Note
      

Bank Voltages

Bank

Schematic Name

Voltage

Voltage Range

500 (MIO0)PS_1.8V 1.8V-
501 (MIO1)PS_1.8V1.8V-
502 (DDR3)1.35V1.35V-
12 HRVCCIO_12UserHR: 1.2V to 3.3V
13 HRVCCIO_13UserHR: 1.2V to 3.3V
33 HPVCCIO_33UserHP: 1.2V to 1.8V
34 HPVCCIO_34UserHP: 1.2V to 1.8V
35 HPVCCIO_35UserHP: 1.2V to 1.8V

Board to Board Connectors

Unable to render {include} The included page could not be found.

Variants Currently In Production

 Module VariantZynq SoC

SoC Junction Temperature

Operating Temperature Range
TE0745-02-30-1IXC7Z030-1FBG676I–40°C to +100°CIndustrial
TE0745-02-35-1CXC7Z035-1FBG676C0°C to +85°CCommercial
TE0745-02-45-1CXC7Z045-1FBG676C0°C to +85°CCommercial
TE0745-02-45-2IXC7Z045-2FBG676I–40°C to +100°CIndustrial

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference Document

VIN supply voltage

  

V

-

Storage temperature

 

 

°C

-
Assembly variants for higher storage temperature range are available on request.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document
VIN supply voltage    
Operating temperature    
Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings.

Operating Temperature Ranges

Commercial grade: 0°C to +70°C.

Industrial grade: -40°C to +85°C.

Extended grade: 0°C to +85°C.

Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

  • Module size: ... mm × ... mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: ... mm.

  • PCB thickness: ... mm.

  • Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.

 All dimensions are given in millimeters.

 Put mechanical drawings here...

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
-

01

Prototypes

  

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Put pic of PCB silk screen here showing model and revision ...

Document Change History


Date

Revision

Contributors

Description

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v.20

John Hartfiel

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v.1

Jan Kumann

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Jan Kumann, John Hartfiel

 

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Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

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Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

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REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


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Table of contents

 

 

Features

  • Mini-ITX form factor
  • ATX Power supply connector (Important 12V only Supply Required)
  • optional 12V Standard Power Plug
  • USB3 with USB3 HUB
  • Gigabit Ethernet RJ45
  • MicroSD Card (bootable)
  • eMMC (bootable)
  • PCIe slot - one PCIe lane (16 Lane Connector)
  • Displayport Single Lane
  • One SATA Connector
  • FMC HPC Slot (1.8V max VCCIO)
  • Dual SFP+
  • One Samtec FireFly (4 GT lanes bidir)
  • One Samtec FireFly connector for reverse loopback
  • Fan connectors, PC Enclosure, FMC Fan
  • Intel front panel connector (PWR/RST/LED)
  • Intel HDA Audio connector
  • CAN FD Transceiver (10 Pin IDC Connector)
  • 20 Pin ARM JTAG Connector (PS JTAG0)

PC Enclosure Rear Panel Accessible I/O

  • PCIe accepting 16 Lane PCIe cards (one lane used PS GT)
  • FMC HPC
  • Dual SFP+
  • RJ45 Gigabit Ethernet
  • 2x USB3 Host
  • Displayport (Single lane)
  • microSD
  • Two LED's
  • CAN FD (using DB9 to IDC10 Cable)
  • One PMOD

PC Front Panel I/O

  • Reset Button
  • Power Button
  • Power LED
  • HD LED
  • Intel HDA Audio
  • One USB2 HS Host port
  • One USB3 SS Host port

The above I/O interfaces are accessible using standard PC front panel cables.

TEBF0808-REV2 Component Locations

TEBF0808-REV2 Component Locations

CalloutFeatureComponent Designator
1PMod 2x6  SocketP2
2MicroSD Connector (Bottom)J16
3Display Port SocketJ13
4USB3.0 A 2x , RJ45 1x  StackedJ7
5Dual SFP+J14
6PCIe x16 Connector (one PCIe lane connected)J11
7FMC (1.8V max VCCIO)J5
8FAN-FMC 2 Pol.J19
9USB3 Connector 19 Pol.J8
10USB 3.0 A ConnectorJ18
11SMA (SI5338 CLK1A)J32
12SMA (B2B-IN2_P)J33
13SD Card SocketJ27
14CAN PIN-Header 6 Pol.J29
15CAN Connector 10 Pol.J24
164x Samtec B2B -Connector for TE0808J1,J2,J3,J4
17eMMC (MTFC16GJVEC-2M WT)U2
18Battery holder CR1220B1
19JTAG Connector 20 Pol.J30
20ATX Power supply connectorJ20
21PMod 2x6  SocketP3
22FFA I2C Pin HeaderJ34
23Jumper 2x4 (Configuration)S4
24BEEPER  PIN Header 4 Pol. J23
25Pin Header 12 Pol. (XMOD-FPGA Access)J12
26Pin Header 12 Pol. (XMOD-Carrier CPLD Access)J28
27Pin Header 9 Pol. (Intel front panel (PWR/RST/LED))J10
28PMod 2x6  SocketP1
29INTEL HDA Header 9 Pol.J9
30PLL I2C Connector 10 Pol.J17
31RST Push ButtonS2
32Samtec FireFly (4 GT lanes bidirectional)J6,J15
33SATA HeaderJ31
34FAN-1 4 Pol.J26
35Samtec FireFly Connector for reverse loopbackJ21,J22
36Jumper 2x4- CPLDS5
37PWR Push ButtonS1
38Power Jack 2.1mm 12VJ25

Table: Board Component Description

TE0808 GT Transceivers

GT LaneFunctionRef ClockComment
PS 0PCIe100 
PS 1USB3100 
PS 2SATA150 
PS 3DP.027 
B128 0..3FireFly  
B228 0..3FMC 0..3  
B229 0..3FMC 4..7  
B230 0.1FMC 8..9  
B230 2SFP125/156.25 
B230 3SFP125/156.25 

GT Lane Assignment

 

GT ClockFromDefaultNotes
PS 0OscillatorUsernot fitted oscillator
PS 1Oscillator150MHzSATA
PS 2Si5345100MhzUSB/PCIe
PS 3Si534527MhzDisplayPort
B128 0Si5345  
B128 1not used  
B228 0FMC GTCLK 0User 
B228 1Si5345  
B229 0FMC GTCLK 1User 
B229 1Si5345User 
B230 0Si5345User 
B230 1Si5345  

GT CLK Assignment

TE0808 MIO Assignment

 

MIODefaultAlternateNotes
0..12Dual QSPI-Bootable
13..23SD0: eMMC-Bootable
24, 25 CPLD MUXED 
26..29PJTAG0CPLD MUXEDBootable JTAG
30 CPLD MUXED 
31PCIeCPLD MUXEDSame as ZCU102
32 CPLD MUXED 
33PMUCPLD MUXEDSame as ZCU102
34..37DPauxCPLD MUXED 
38, 39I2C0- 
40, 41CAN1CPLD MUXED 
42, 43UART0CPLD MUXED 
44I2C InterruptCPLD MUXED 
45..51SD1: SD-Bootable SD Card
52..63USB0- 
64..75GEM3- 
76, 77MDIO  

MIO Assignment

TE0808 Si5345 PLL Settings

 

Input/OutputConnected toFrequencyUsed asNotes
IN0Oscillator25MHzInternal Reference 
IN2SMAUserExternal Reference 
OUT0PCIe100MHzPCIe REFCLK 
OUT1B230 CLK0125MHzFMC GT Clock 
OUT2B229 CLK1UserFMC GT Clock 
OUT3B228 CLK1UserFMC GT Clock 
OUT4B505 CLK2100MHzPCIe and USB Clock 
OUT5B505 CLK327MHzDisplayPort GT SERDES  Clock 
OUT6B128 CLK0157.6MHz (2 x 78.8)DP Video Pixel ClockSeems to be needed for DP to work
OUT7B230 CLK1156.25MhzSFP Clock 
OUT8Si5338 IN125MhzSi5338 Reference 

Recommended/Default settings for the Si5345

By default Si5345 is not programmed after power on, so if FSBL is executed without proper Si5345 init or if psu_init.tcl is invoked and the design does use PS GT, then FSBL or psu_init.tcl would freeze on SERDES init code. Si5345 init does persist over reset sequence so it is possible to use known good boot files to init Si5345 and then FSBL debugging is also possible.

 

FMC Slot

FMC Slot is fitted as full FMC HPC.

Note: FMC VADJ maximum voltage is 1.8V (as HP banks do not support more than 1.8V).

SignalsMPSoC PS/PL 
FMC LAHPMapped to PL HP Banks
FMC HAHP/HDHP/HD banks mixed
FMC HBHP/HDHP/HD banks mixed
CLK0PL ClockHP Bank
CLK1PL ClockHD Bank
CLK2Clock from Si5345use as clock input not supported
CLK3Clock from Si5345use as clock input not supported
GT CLK0B228 CLK1 
GT CLK1B229 CLK1 
I2CPS I2Cvia I2C multplexer
GA0, GA10Address set to 00

Optional FAN can be mounted below the FMC slot. Ther are no components below the FMC card, so FMC cards with extended component heights can be used.

 

I2C Buses

Bus #Device(s)AddressesNotes
0MUX U16  

1

Si5338 on base0x70 
2GPIO Extender0x26 
3PCIe SMBus  

4

SFP  
5SFP  
6GPIO, EEPROM0x27, 0x50, 0x51, 0x52, 0x54 
7FMC0x50 FRU EEPROMother address depend on FMC Card
8USB3 HUB For REV 2 - DO NOT SCAN will cause I2C bus freeze!
9PMOD  
10ADAU17610x38 
11FireFly  
12FireFly  
13Si53450x69Access to PLL on TE0808
14CPLD- 
15GPIO0x24 
16PMOD  

List of I2C buses and devices (bus numbers as enumerated by Linux).

Do not scan bus 8, this would cause the I2C bus multiplexer to freeze until power off or hardware reset.

 

To init Si5345 use command

si534x /dev/i2c-13 0x69

 

DIP Switches

There are two 4 bit DIP Switches on the TEBF0808, they must be used to select some options. On TEBF0808-02 default CPLD-Firmware selects boot from SD-Card, Firmware update is needed for Boot-Mode selection.

 

1234Description
ONONONONDefault, boot from SD/eMMC, 1.8V FMC VADJ
ONONxxBoot from microSD, SD or SPI Flash
OFFONxxBoot from eMMC
ONOFFxxBoot mode  PJTAG0
OFFOFFxxBoot mode main  JTAG
xxxONFMC VADJ = 1.8V
xxxOFFFMC VADJ = 1.2V

DIP Switch S5 located close to PWR push-button. This DIP Switch is connected to the two baseboard control CPLD's.

 

1234Description
OFFOFFOFFONDefault
ONxxxPUDC = 0
OFFxxxPUDC = High

DIP Switch S4 located close to PCIe slot.

 

LEDs

LEDPositionDescription
D4Green LED near DisplayPort Connector 
D5Red LED near DisplayPort Connector 
D6Green LED near Reset Button 
D7Red LED near Reset Button 

 

Power

ATX Power is supported but special 12V ATX power supply must be used.

 

System controller RGPIO 

Master CPLD Read

Bit

Description
31'1' - Constant value
30'0' - Constant value
29'1' - Constant value
28'0' - Constant value
27 
26 
25 
24 
23 
22 
21SCL
20SDA
19DP PHD
18JTAG TMS
17JTAG TDI
16JTAG TCK
15JTAG SRST
14JTAG TRST
13FMC CLKDIR
12FMC TDO
11PHY LED2
10PHY LED1
9PHY LED0
8CAN Fault
7MIO29
6MIO28
5MIO27
4MIO26
3XMOD Button
2SD WP
1SW4
0SW3

Master CPLD Write

Bit

Description
31'1' - Constant value
30'0' - Constant value
29'1' - Constant value
28'0' - Constant value
27 
26 
25 
24 
23 
22 
21 
20 
19 
18 
17 
16 
15 
14 JLED2B
13 JLED2A
12 JLED1
11 SFP_LED3
10 SFP_LED2
9 SFP_LED1
8 SFP_LED0
7 LED1
6 LED0
5 USB HUB MODE1 ('1' for ROM Mode)
4 USB HUB MODE0 ('1' for ROM Mode)
3 Ethernet PHY Reset (Active High)
2 I2C Reset (Active High)
1USB HUB Reset (Active High)
0USB PHY Reset (Active High)

 

 

Slave CPLD Read

Bit

Description
31'1' - Constant value
30'0' - Constant value
29'1' - Constant value
28'0' - Constant value
27 
26 
25 
24 
23 
22 
21 
20 
19 
18 
17 
16 
15 
14 
13 
12 
11 
10 
9PLL LOL 
8XMOD Button 
7Power OK 
6Fan Senese 
5SD Detect 
4Micro SD Detect
3Power Button 
2Reset Button 
1SW2 
0SW1

Slave CPLD Write

Bit

Description
31'1' - Constant value
30'0' - Constant value
29'1' - Constant value
28'0' - Constant value
27 
26 
25 
24 
23 
22 
21 
20 
19 
18 
17 
16 
15 
14 
13 
12 
11 FAN_EN
10 HDLED_P
9 HDLED_N
8 LED_P
7 LED_N
6 LED3
5 LED2
4 FPGA PROG (Active High)
3 PCIe Reset (Active High)
2 MRESET Reset (Active High)
1SRST Reset (Active High) 
0 PLL Reset (Active High)

PCB Revisions

 

Revision 02

Known Issues:

  • signal SFP1 LOS is not connected (fixed in REV 03)

Revision 03

 

 

 

 

 

 

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