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Table 4: JTAG interface signals.

System Control  I/O Pins

Table 5: System Controller CPLD I/O pins.

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For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD.
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SD Card Interface

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Table 5: System Control I/O pins.

<!--
For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD.
Add link to the Wiki reference page of the SC CPLD, if available.
   -->

SD Card Interface

Table 6: SD Card interface signals and connections.

Ethernet Interface

The TEB0724 Carrier Board has a RJ45 Gigabit Ethernet MagJack (J3) with two LEDs. On-board Ethernet MagJack pins are routed to B2B connector J1 via MDI. LEDs are also routed to the B2B connector.

Ethernet PHY connection

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Table 6: SD Card interface signals and connections.

Ethernet Interface

On board Gigabit Ethernet PHY is provided with ...

Ethernet PHY connection

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Table x: ...Table 7: Ethernet MagJack

I2C Interface

On-board I²C bus is connected to accaessable with the following pins:

Table x8: I²C slave device addressespins.

On-board Peripherals

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Components on the Module, like Flash, PLL, PHY...
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Gigabit Ethernet PHY

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PHY

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...

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...

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Oscillators

The module has the following reference clock signals provided by on-board oscillators and external source from carrier boardon-board oscillators:

Table 9: Reference clock signals.

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Table 10: On-board LEDs.

Power and Power-On Sequence

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If power sequencing and distribution is not so much, you can join both sub sections together
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Power Consumption

The maximum power consumption of a module mainly depends on the design running on the FPGA.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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On-board Push Buttons

Table 11: On-board Push Buttons.

Power and Power-On Sequence

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If power sequencing and distribution is not so much, you can join both sub sections together
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Power Consumption

The maximum power consumption depends on the attached module the design running on the module and additional peripherals.

Xilinx provide a power estimator excel sheets to calculate power consumption for FPGAs. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

Table 12: Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of 3A for system startup is recommended.

Table : Typical power consumption.

 * TBD - To Be Determined soon with reference design setup.

Power supply with minimum current capability of ...A for system startup is recommended.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

The on-board voltages of the TE07xx SoC module will be powered-up in order of a determined sequence after the external voltages '...', '...' and '...' are available. All those power-rails can be powered up, with 3.3V power sources, also shared. <-- What?

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Regulator dependencies and max. current.

Put power distribution diagram here...

Figure : Module power distribution diagram.

See Xilinx data sheet ... for additional information. User should also check related base board documentation when intending base board design for TE07xx module.

Power-On Sequence

The TE07xx SoM meets the recommended criteria to power up the Xilinx Zynq MPSoC properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

Put power-on diagram here...

User should also check related module documentation Xilinx data sheet, respectively.

Power-On Sequence

The power-on sequence is solely controlled by the attached module.  Optional signals for integration of additional hardware are PWR_GPIO2 and PWR_GPIO4.

If the attached module uses the adjustable bank power VCCIO_35, this hat to be powered up after the the SOCs powerrails are upFigure : Module power-on diagram.

Power Rails

NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

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The TEB0724 base board has two 160-pin double-row REF-189019-02 connectors on the bottom side.

Table 15: Connectors for module and baseboard.

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