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| Pin Name | Mode | Function | B2B Connector Pin | Default Configuration |
|---|---|---|---|---|
| JTAG_EN | Input | JTAG select | J1-148 | During normal operating mode the JTAG_EN pin should be in the low state for JTAG signals to be forwarded to the Zynq SoC. |
| RST_IN_N | Input | Reset | J2-131 | Low-active Power-On reset pin, controls POR_B-signal (bank 500, pin C23) of Zynq chip. |
| PS_SRST | Input | Reset | J2-152 | Low-active PS system-reset pin of Zynq chip. |
| BOOTMODE_1 | Output | Boot mode | J2-133 | Control line which sets in conjunction with signal 'BOOTMODE1BOOTMODE' (B2B-pin J2-133) Permanent logic high in standard SC-CPLD firmware. |
| PWR_PL_OK | Input | Power good | J2-135 | Indicates stable state of PL supply voltage (low-active) after power-up sequence. |
| PWR_PS_OK | Input | Power good | J2-139 | Indicates stable state of PS supply voltage (low-active) after power-up sequence. |
| EN_PL | Output | Enable signal | - | Low active Enable-signal for activating PL supply voltage. Permanent logic high in standard SC-CPLD firmware. |
| MIO8 | Input | PS MIO | - | User I/O (pulled-up to PS_1.8V). |
| MIO0 | Input | PS MIO | J2-137 | User I/O. |
| RTC_INT | Input | Interrupt signal | - | Interrupt-signal from on-board RTC. |
| LED | Output | LED control | - | Green LED D1, indicates SC-CPLD activity by blinking. |
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| Date | Revision | Contributors | Description | ||||||||||||||||||||||||
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| 2019-06-14 | v.84 | John Hartfiel |
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2018-04-11 | v.81 | John Hartfiel |
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2017-11-14 | v.80 | John Hartfiel |
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| 2017-11-13 | V v.79 | Ali Naseri, Jan Kumann, John Hartfiel |
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