Page History

Custom_table_size_100

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Date	Version	Changes	Author	3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma	3.11	update "Recommended Operating Conditions" section	3.1	New general notes for temperature range to "Recommended Operating Conditions"	3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)	3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)	3.00	→ separation of Carrier/Module and evaluation kit TRM	2.15	add excerpt macro to key features	2.14	add fix table of content add table size as macro
2024-08-07	4.3	add article name encoding table link to "Currently offert Variants" chapter removed empty lines	JH/ED
	4.2.1	Error correction in tables "Power Rails" and "Configuration and System Control Signals"	KJ
	4.2	Changes Xilinx to AMD	ED
	4.1	Minor changes Notes Tables	ED
	4.0	Rework for smaller TRM which can be generated faster Reduce Signal Interfaces Pin Reduce On Board Periphery Reduce Power Move Configuration Signals from Overview to own section	JH
	3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
	3.11	update "Recommended Operating Conditions" section
	3.1	New general notes for temperature range to "Recommended Operating Conditions"
	3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hybrid, Evalboard, Carrier)
	3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
	3.00	→ separation of Carrier/Module and evaluation kit TRM
	2.15	add excerpt macro to key features
	2.14	add fix table of content add table size as macro

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
Scroll Title
anchor Table_tablename
title-alignment center
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
sortByColumn 1
sortEnabled false
cellHighlighting

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
- Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:

Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

style	widths
orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistant consistent across TRMs. A incomplete list of examples is given below

<type>_<main section>_<name>
- type: Figure, Table
- main section:
  - "OV" for Overview
  - "SIP" for Signal Interfaces and Pins,
  - "OBP" for On board Peripherals,
  - "PWR" for Power and Power-On Sequence,
  - "B2B" for Board to Board Connector,
  - "TS" for Technical Specification
  - "VCP" for Variants Currently in Production
  - "RH" for Revision History
- name: custom, some fix names, see below
Fix names:
- "Figure_OV_BD" for Block Diagram
- "Figure_OV_MC" for Main Components
- "Table_OV_IDS" for Initial Delivery State
- "Table_PWR_PC" for Power Consumption
- "Figure_PWR_PD" for Power Distribution
- "Figure_PWR_PS" for Power Sequence
- "Figure_PWR_PM" for Power Monitoring
- "Table_PWR_PR" for Power Rails
- "Table_PWR_BV" for Bank Voltages
- "Table_TS_AMR" for Absolute_Maximum_Ratings
- "Table_TS_ROC" for Recommended_Operating_Conditions
- "Figure_TS_PD" for Physical_Dimensions
- "Table_VCP_SO" for TE_Shop_Overview
- "Table_RH_HRH" for Hardware_Revision_History
- "Figure_RH_HRN" for Hardware_Revision_Number
- "Table_RH_DCH" for Document_Change_History

Use Anchor in the document: add link macro and add "#<anchorname>

Refer to Anchror Anchor from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

OverviewOverview

The Trenz Electronic TE0820 is a powerful an industrial/extended 4 x 5 cm industrial/extended module integrated with a Xilinx SoM integrating an AMD Zynq UltraScale+ MPSoC. In addition, the module is equipped with 2x 8 Gb DDR4 SDRAM chip, up to 64 Gb eMMC chipmemory, 2x 512 Mb flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust Three high-speed connectors provide a large number of inputs and outputs. Additionally, the module provides Gigabit Ethernet and USB2USB 2.0 Transceivers0 transceivers.

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

Refer to http://trenz.org/te0820-info for for the current online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples fro for different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Key Features

Package: SFVC784

Excerpt
SoC

/FPGA

- Device:

ZU2 ...ZU5, *

- ZU1 / ZU2 / ZU3 / ZU4 / ZU5 ¹⁾
- Engine: CG / EG

, CG, EV, *Speed

- / EV ¹⁾
- Speedgrade: -1

,

- / -1L

,

- / -2

,

- / -2L

, 3, *, **

- / 3 ¹⁾
- Temperature

: I, E, *, **

- Range: Extended / Industrial ¹⁾
- Package: SFVC784
RAM/Storage

2x DDR4 SDRAM,

Data Width: 16 Bit
Size: 8 Gb, *
Speed: 2400 Mbps, ***

2x QSPI boot Flash in dual parallel mode

Data Width: 8 Bit
Size: 512 Mb Gb, *

1x e.MMC Memory

Data Width: 16 Bit
Size: 8 Gb, *

MAC address serial EEPROM

- 2 GByte DDR4 SDRAM ²⁾
- 2 x 64 MByte Serial Flash ³⁾
- 8 GByte eMMC ³⁾
- EEPROM with MAC address
On Board
- Lattice

On Board
Lattice

- MachXO2 CPLD
- Programmable Clock Generator
- Hi-speed USB2 ULPI Transceiver
- 10/100/1000 Mbps Ethernet Transceiver
- 4x LEDS
Interface

1 Gbps RGMII Ethernet interface

Hi-speed USB2 ULPI transceiver with full OTG support

Graphic Processor Mali-400 MP2, *

132x High Performance (HP)

4 x serial PS GTR transceivers

PCI Express interface
SATA 3.1 interface
DisplayPort interface with video resolution up to 4k x 2k
2x USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate

Power

All power regulators on board

Dimension

40 x 50 mm

Note

* depends on assembly version
** also non low power assembly options possible
*** depends on used U+ Zynq and DDR4 combination
Rugged for shock and high vibration

Additional assembly options are available for cost

- 3 x B2B Connector (LSHM)
  - up to 132 PL HP IO
  - up to PS 14 MIO
  - 4 PS GTR
  - ETH (MDI) or SGMII
  - USB
  - SDIO
  - CFG, JTAG
Power
- 3.3 V power supply via B2B Connector needed ⁴⁾.
Dimension
- 40 mm x 50 mm
Notes
¹⁾ Please, take care of the possible assembly options. Furthermore, check whether the power supply is powerful enough for your FPGA design.
²⁾ Up to 4 GByte are possible with a maximum bandwidth of 2400 MBit/s.
³⁾ Please, take care of the possible assembly options.
⁴⁾ Higher input voltage may be possible

or performance optimization upon request

.

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	TE0820 -03 block diagram

Scroll Ignore

draw.io Diagram

border	false

diagramName	TE0820 BD Block Diagram
simpleViewer	false
width
links	auto
tbstyle	hidden
diagramDisplayName
lbox	true
diagramWidth	641
revision	14

Scroll Only
Image RemovedImage Added

Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photos, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	TE0820 -03 main components

Scroll Ignore

draw.io Diagram

border	false

diagramName	TE0820 MC main components
simpleViewer	false
width
links	auto
tbstyle	hidden
diagramDisplayName
lbox	true
diagramWidth	641
revision	13

Scroll Only
Image Removed Image Added

Xilinx AMD Zynq UltraScale+ MPSoC, U1
1.8V, 512 Mbit QSPI flash memory, U71.8V, 512 Mbit QSPI flash memory, U17
8 Gbit (512 x 16) DDR4 SDRAM, U2
8 Gbit (512 x 16) DDR4 SDRAM, U3
Marvell Alaska 88E1512 integrated 10/100/1000 Mbps energy efficient ethernet transceiver, U8
6A PowerSoC DC-DC converter (PL_VCCINT, 0.85V), U5
B2B connector Samtec Razor Beam™ LSHM-150, JM1
B2B connector Samtec Razor Beam™ LSHM-150, JM2
B2B connector Samtec Razor Beam™ LSHM-130, JM3
, U3
eMMC memory, U6
EEPROM, U25
Ethernet transceiver, U8
USB 2.0 ULPItransceiver, U18
B2B Connector, JM1, JM2, JM38 GByte eMMC memory, U6
Lattice Semiconductor MachXO2 System Controller CPLD, U21
I2C programmable, any frequency , any output quad clock generator, U10

Highly integrated full featured hi-speed USB 2.0 ULPItransceiver

, U18

Clock generator, U10
Oscillator, U11, U14, U32
Done LED, D1
User LED, D2
Error Out LED, D3
Error Status LED, D4
LED D1(Red) Done Pin
LED D2 (Green) CPLD Status, User LED
LED D3 (Red) PS Error
LED D4 (Green) PS Error Status

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Programmed

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

widths

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes

Dual QSPI

Quad SPI Flash

Memory

Not

not programmed
eMMC

Memory

Not

not programmed
DDR4 SDRAM

Not

not programmed
Programmable Clock Generator

Not

not programmed
EEPROM

CPLD (LCMXO2-256HC)

not programmed besides factory programmed MAC address
System Controller CPLD	programmed	TE0820 CPLD

Configuration

Signals, Interfaces and Pins

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Overview of Boot Mode, Reset, Enables.

Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.

For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
Table with all connectors and Designator List of different interfaces per connector IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

*changable also with other CPLD Firmware: TE0820 CPLD

Scroll Title

anchor	Table_OVSIP_BPC
title-alignment	center
title	Boot process.Board Connectors

Scroll Table Layout

style

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

MODE Pin

Boot Mode

High

QSPI*

Low

SD Card*

Scroll Title

anchor	Table_OV_RST
title-alignment	center
title	Reset process.

Scroll Table Layout

orientation

portrait

sortDirection

ASC

repeatTableHeaders

default

style

widths

sortByColumn

1

sortEnabled

false

cellHighlighting

true

Signal

B2B

I/O

Note

EN1

JM1-28

Input

CPLD Enable Pin

RESIN

JM2-18

Input

General Reset

Signals, Interfaces and Pins

Connector Type	Designator	Interface	IO CNT
B2B	JM1	ETH - MDI	ETH
B2B	JM1	HP	48 SE / 24 DIFF
B2B	JM1	MIO	8 x GPIO
B2B	JM1	SDIO	SDIO or 6 x MIO
B2B	JM2	HP	68 SE / 33 DIFF
B2B	JM2	CFG	JTAG
B2B	JM3	ETH	SGMII
B2B	JM3	MGT PS	4 x MGT (RX/TX)
B2B	JM3	MGT PS	MGT CLK
B2B	JM3	CLK	DIFF CLK
B2B	JM3	HP	16 SE / 8 DIFF
B2B	JM3	USB	USB

Test Points

For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

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Note

Modules has mostly B2B Connector with Interface subsections

Hybride Modules have B2B Connector with Interface subsections and additional "real" connector

Carrier has B2B connector (maybe not all interfaces like modules has) and "real" connectors

Evaluation boards has only "real" connectors

Modules with main SoC have an additional MIO section, where dedication MIO Pin assignment will be shown

Board to Board (B2B) I/Os

Zynq MPSoC's I/O banks signals connected to the B2B connectors:

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section.

Example:

Test Point	Signal	Notes¹⁾
TP1	PWR_PL_OK

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Scroll Title

anchor	Table_SIP_B2BTPs
title-alignment	center
title	General PL I/O to B2B connectors informationTest Points Information

Scroll Table Layout

style

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Bank

Test Point

Type

B2B Connector

I/O Signal Count

Voltage

Notes

64

HP

JM2

48x Single Ended, 24x LVDS Pairs

Variable

Max voltage 1.8V

64

HP

JM2

2x Single Ended

Variable

Max voltage 1.8V

65

HP

JM2

18x Single Ended, 9x LVDS Pairs

Variable

Max voltage 1.8V

65

HP

JM3

16x Single Ended, 8x LVDS Pairs

Variable

Max voltage 1.8V

66

HP

JM1

48x Single Ended, 24x LVDS Pairs

Variable

Max voltage 1.8V

500

MIO

JM1

8x Single Ended

1.8V

501

MIO

JM1

6x Single Ended

3.3V

505

GTR

JM3

16x Single Ended, 8x LVDS Pairs

-

4x Lanes

505

GTR CLK

JM3

1x differential Clock

-

For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Scroll Title

anchor	Table_SIP_MGT
title-alignment	center
title	MGT Lanes connection

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueLaneBankSignal NameB2B PinNote0505

B505_RX0_P
B505_RX0_N
B505_TX0_P
B505_TX0_N

JM3-26
JM3-28
JM3-25
JM3-27

1505

B505_RX1_P
B505_RX1_N
B505_TX1_P
B505_TX1_N

JM3-20
JM3-22
JM3-19
JM3-21

2505

B505_RX2_P
B505_RX2_N
B505_TX2_P
B505_TX2_N

JM3-14
JM3-16
JM3-13
JM3-15

3505

B505_RX3_P
B505_RX3_N
B505_TX3_P
B505_TX3_N

JM3-8
JM3-10
JM3-7
JM3-9

There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

Scroll Title

anchor	Table_SIP_MGTCLK
title-alignment	center
title	MGT Clock Sources Information

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueClock signalBankConnected toNotesB505_CLK0_P505B2B, JM3-31Supplied by the carrier boardB505_CLK0_N505B2B, JM3-33Supplied by the carrier boardB505_CLK1_P505U10, CLK2AOn-board Si5338AB505_CLK1_N505U10, CLK2BOn-board Si5338AB505_CLK2_P505N/ANot connectedB505_CLK2_N505N/ANot connectedB505_CLK3_P505U10, CLK1AOn-board Si5338AB505_CLK3_N505U10, CLK1BOn-board Si5338A

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.

Scroll Title

anchor	Table_SIP_JTG
title-alignment	center
title	JTAG pins connection

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue

JTAG Signal

B2B Connector Pin

NotesTMSJM2-93TDIJM2-95TDOJM2-97TCKJM2-99 JTAGENJM1-89Pulled Low: Xilinx Zynq UltraScale+ MPSoC
Pulled High: Lattice MachXO CPLD

Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.

I2C Addresses

On-board I²C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I²C0 by default. Addresses for on-board I²C slave devices are listed in the table below:

Scroll Title

anchor	Table_SIP_I2C
title-alignment	center
title	Address table of the I2C bus slave devices

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueI2C DeviceI2C AddressNotes

PLL Clock Generator, U10

0x70/ 0x71EEPROM, U250x50

MIOs

Scroll Title

anchor	Table_SIP_MIOs
title-alignment	center
title	MIOs pins

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueMIO PinConnected toB2BNotes0...5QSPI Flash, U7-SPI Flash7...12QSPI Flash, U17-SPI Flash13...23eMMC, U6eMMC24ETH Transceiver, U8-ETH_RST25USB2.0 Transceiver, U18-OTG_RST26...33User MIOJM134...37N.C-N.C38...39EEPROM, U25-I2C_SDA/SCL40...45N.CN.C46...51SD CardJM152...63USB2.0 Transceiver, U18-63...77Ethernet Transceiver, U8-

Test Points

Scroll Title

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueTest PointSignalConnected toNotes1PS_LP0V85Voltage Regulator, U122DDR_2V5Voltage Regulator, U43PS_AVCCVoltage Regulator, U94DDR_1V2Voltage Regulator, U155PS_AVTTVoltage Regulator, U36VTTRegulator, U167PS_FP0V85Voltage Regulator, U268VREFARegulator, U1610PS_PLLVoltage Regulator, U2311PL_VCCINTVoltage Regulator, U515PL_VCCINT_IOVoltage Regulator, U2716PL_VCUVoltage Regulator, U24

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example: #ClockSources, #CPLD, #QuadSPIFlash

Scroll Title

anchor	Table_OBP
title-alignment	center
title	On board peripherals

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueChip/InterfaceDesignatorNotesQSPI FlashU7, U17EEPROMU25DDR4 SDRAMU2,U3GigaBit EthernetU8USB2.0 TransceiverU18eMMC MemoryU6OscillatorsU32, U14, U11Programmable Clock GeneratorU10CPLDU21LEDsD1...3

System Controller CPLD

The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module.

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Scroll Title

anchor	Table_SIP_CPLD
title-alignment	center
title	System Controller CPLD special purpose pins

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtruePin NameModeFunctionDefault ConfigurationEN1InputPower Enable

No hard wired function on PCB. When forced low, PGOOD goes low without effect on power management

PGOODOutputPower GoodOnly indirect used for power status, see CPLD descriptionNOSEQ--No used for Power sequencing, see CPLD descriptionRESINInputReset

Active low reset, gated to POR_B

JTAGENInputJTAG SelectLow for normal operation, high for CPLD JTAG access

Please check the entire information at TE0820 CPLD.

See also TE0820 System Controller CPLD page.

eMMC Memory

eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.

DDR4 Memory

The TE0820 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.

Part number: K4A8G165WB-BIRC
Supply voltage: 1.2V
Speed: 2400 Mbps
Temperature: -40 ~ 95 °C

Quad SPI Flash Memory

Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Gigabit Ethernet

On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U11).

High-speed USB ULPI PHY

Scroll Title

anchor	Table_SIP_ETH
title-alignment	center
title	GigaBit Ethernet connection

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtruePinSchematicConnected toNoteMDIP0...3

PHY_MDI0...3

B2B, JM1

MDC

ETH_MDC

MIO76

MDIOETH_MDIOMIO77S_INS_INB2B, JM3S_OUTS_OUTB2B, JM3TXD0..3ETH_TXD0...3MIO65...68TX_CTRLETH_TXCTLMIO69TX_CLKETH_TXCKMIO64RXD0...3ETH_RXD0...3MIO71...74RX_CTRLETH_RXCTLMIO75RX_CLKETH_RXCKMIO70LED1PHY_LED1CPLD, U21RESETnETH_RSTMIO24

USB2.0 Transceiver

Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).

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Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue PHY PinZYNQ PinB2B NameNotesULPIMIO52..63-Zynq USB0 MIO pins are connected to the USB PHY.REFCLK--52.000000 MHz from on-board oscillator (U14).REFSEL[0..2]--Reference clock frequency select, all set to GND selects 52.000000 MHz.RESETBMIO25-Active low reset.CLKOUTMIO52-Connected to 1.8V, selects reference clock operation mode.DP, DM-OTG_D_P, OTG_D_NUSB data lines routed to B2B connector JM3 pins 47 and 49.CPEN-VBUS_V_ENExternal USB power switch active high enable signal, routed to JM3 pin 17.VBUS-USB_VBUSConnect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55.ID-OTG_IDFor an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23.

Signal	Notes¹⁾
TP1	PS_LP0V85
TP2	DDR_2V5
TP3	PS_AVCC
TP4	DDR_1V2
TP5	PS_AVTT
TP6	VTT
TP7	PS_FP0V85
TP8	VREFA
TP9	DDR4-TEN	pulled-down to GND
TP10	PS_PLL
TP11	PL_VCCINT
TP12	PG_ALL	pulled-up to 3.3VIN
TP15	PL_VCCINT_IO
TP16	PL_VCU

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/Interface	Designator	Connected To	Notes
ETH PHY	U10	B2B connector J1 SoC MIO	Gigabit ETH PHY

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Chip/Interface	Designator	Connected To	Notes
QSPI Flash	U7, U17	SoC - PS
EEPROM	U25	SoC - PS
DDR4 SDRAM	U2, U3	SoC - PS
GigaBit Ethernet	U8	SoC - PS, B2B
USB2.0 Transceiver	U18	SoC - PS, B2B
eMMC Memory	U6	SoC - PS
Oscillator	U32	SoC - PS
Oscillator	U14	USB PHY
Oscillator	U11	Clock Generator, ETH PHY
Programmable Clock Generator	U10	SoC - PS, B2B
CPLD	U21	SoC - PS, B2B
LED	D1	SoC - PS	Red, Done LED (see U+ Zynq TRM)
LED	D2	CPLD	Green, Status LED (see TE0820 CPLD)
LED	D3	SoC - PS	Red, PS Error LED (see U+ Zynq TRM)
LED	D4	SoC - PS	Green, PS Error Status LED (see U+ Zynq TRM)

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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

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title	Controller signal.

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EEPROM

There is a 2Kb EEPROM (U25) provided on the module TE0820.

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Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueMIO PinSchematicU25 PinNotesMIO39I2C_SDASDAMIO38I2C_SCLSCL

Programmable Clock Generator

There is a Silicon Labs I²C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I²C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). For this, proper I²C bus logic has to be implemented in FPGA.

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U25 PinSignalConnected toDirectionNote

IN0..1

CLK_INJM3ININ2CLK_25MOscillator, U11INSCLI2C_SCLEEPROM,U25INOUTSDAI2C_SDAEEPROM,U25INOUTCLK0CLK0JM3OUTCLK1B505_CLK3FPGA Bank 505INCLK2B505_CLK1FPGA Bank 505INCLK3CLK3_NIN

Clock Sources

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Designator

Description

Frequency

Clock Destination

U32

MEMS Oscillator

33.33 MHz

U11

MEMS Oscillator

25 MHz

U14

MEMS Oscillator

52 MHz

LEDs

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Connector+Pin	Signal Name	Direction¹⁾	Description
JM1-7	NOSEQ	IN/OUT	See 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-28	EN1	IN	See 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-30	PGOOD	IN/OUT	See 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-32	MODE	IN	See 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM1-89	JTAGEN	IN	See 4 x 5 SoM Integration Guide and TE0820 CPLD.
JM2-18	RESIN	IN	Reset signal, see 4 x 5 SoM Integration Guide.
JM2-93 / JM2-95 / JM2-97 / JM2-99	TMS / TDI / TDO / TCK	Signal-dependent	JTAG configuration and debugging interface. JTAG reference voltage: 3.3VIN

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueDesignatorColorConnected toActive LevelNoteD1RedDONELowD2GreenUSR_LEDHighD3RedERR_OUTHighD4GreenERR_STATUSHighPower and Power-on Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
Power on-sequence
Power distribution
Voltage monitoring circuit
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Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power

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Power

Input PinTypical Current

Rail Name/ Schematic Name	Connector.Pin	Direction¹⁾	Notes
VIN

TBD*

3.3VIN

TBD*

* TBD - To Be Determined soon with reference design setup.

For the lowest power consumption and highest efficiency of the on-board DC-DC regulators it is recommended to power the module from one single 3.3V supply. All input power supplies should have a nominal value of 3.3V. Although the input power supplies can be powered up in any order, it is recommended to power them up simultaneously.

Warning
To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any Zynq's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

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See also Xilinx datasheet DS925 for additional information. User should also check related base board documentation when intending base board design for TE0820 module.

JM1.1 / JM1.3 / JM1.5 / JM2.2 / JM2.4 / JM2.6 / JM2.8	IN	Supply voltage from carrier board
3.3VIN	JM1.13 / JM1.15	IN	Supply voltage from carrier board
3.3VIN	JM2.91	OUT	JTAG reference voltage
+3.3V	JM2.10 / JM2.12	OUT	Internal +3.3 V voltage level
+1.8V	JM1.39	OUT	Internal +1.8V voltage level
VCCO_64	JM2.7 / JM2.9	IN	HP Bank voltage (max. +1.9 V)
VCCO_65	JM2.5	IN	HP Bank voltage (max. +1.9 V)
VCCO_66	JM1.9 / JM1.11	IN	HP Bank voltage (max. +1.9 V)
PSBATT	JM1.79	IN	PS battery supply voltage

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

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Power-On Sequence

The TE0820 SoM keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

Following diagram clarifies the sequence of enabling the particular on-board voltages, which will power-up in descending order as listed in the blocks of the diagram:

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For highest efficiency of the on-board DC-DC regulators, it is recommended to use one 3.3V power source for both VIN and 3.3VIN power rails. Although VIN and 3.3VIN can be powered up in any order, it is recommended to power them up simultaneously.

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Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration signal setup.	See Configuration and System Control Signals.
1 ¹⁾	3.3VIN	3.3 V (± 5 %)	-	Management and SoC power supply.	Main module power supply for management and SoC. 1 A recommended. Power consumption depends mainly on design and cooling solution.
2 ¹⁾	VIN	3.3 V (± 5 %) ²⁾ OR 5.0 V (± 5 %) ²⁾	-	Main module power supply.	Main module power supply for management and SoC. 3 A to 7 A recommended. Power consumption depends mainly on design and cooling solution.
3	1.8V	-	-	1.8 V on-module power supply.
4	3.3V	-	-	3.3 V on-module power supply.
5	VCCO_64 / VCCO_65 / VCCO_66	²⁾	-	Module bank voltages.	Enable bank voltages after 1.8 V and/or 3.3 V are available on carrier.

¹⁾ In cases where VIN = 3.3VIN = 3.3 V, both voltages can be enabled together.

²⁾ A higher or lower input voltage may be possible.

²⁾ See DS925 for additional information.

Board to Board Connectors

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
6 x 6 SoM LSHM B2B Connectors
6 x 6 SoM LSHM B2B Connectors

Include Page

	4 x 5 SoM LSHM B2B Connectors
	4 x 5 SoM LSHM B2B Connectors

Technical Specifications

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List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings ^*)

It is important that all carrier board I/Os are 3-stated at power-on until 3.3V_out or 1.8V_out is present on B2B connector JM2 pins 10 and 12, indicating that all on-module voltages have become stable and module is properly powered up.

See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.

Power Rails

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Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtruePower Rail Name on B2B ConnectorJM1 PinsJM2 PinsDirectionNotesVIN

1, 3, 5

2, 4, 6, 8InputSupply voltage from the carrier board3.3V-10, 12OutputInternal 3.3V voltage level3.3VIN13, 15-InputSupply voltage from the carrier board1.8V39-OutputInternal 1.8V voltage levelJTAG VREF-91OutputJTAG reference voltage.
Attention: Net name on schematic is "3.3VIN"VCCO_64-7, 9InputHigh performance I/O bank voltageVCCO_65-5InputHigh performance I/O bank voltageVCCO_669, 11-InputHigh performance I/O bank voltageBank Voltages

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FPGA Bank Schematic Voltage Note
Bank 24 HD N.C. Not Connected Bank 25 HD N.C. Not Connected Bank 26 HD N.C. Not Connected Bank 44 HD N.C. Not Connected
Bank 64 HP VCCO_64 Variable Max voltage 1.8V
Bank 65 HP
VCCO_65
Variable Max voltage 1.8V
Bank 66 HP VCCO_66 Variable Max voltage 1.8V
Bank 500 PSMIO VCCO_PSIO0_500 1.8V
Bank 501 PSMIO
VCCO_PSIO1_501
3.3V
Bank 502 PSMIO VCCO_PSIO2_502 1.8V Bank 503 PSCONFIG VCCO_PSIO3_503 1.8V Bank 504 PSDDR DDR_1V2 1.2V

Board to Board Connectors

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This section is optional and only for modules.

Power Rail Name/ Schematic Name	Description	Min	Max	Unit
VIN	Supply voltage	-0.3	7	V
3.3VIN	Supply voltage	-0.3	3.75	V
VCCO_64	I/O bank voltage	-0.5	2.0	V
VCCO_65	I/O bank voltage	-0.5	2.0	V
VCCO_66	I/O bank voltage	-0.5	2.0	V
PSBATT	RTC / BBRAM	-0.5	2.0	V

^*) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these
or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C

use "include page" macro and link to the general B2B connector page of the module series,

For example: 6 x 6 SoM LSHM B2B Connectors
Include Page6 x 6 SoM LSHM B2B Connectors6 x 6 SoM LSHM B2B Connectors Include Page4 x 5 SoM LSHM B2B Connectors4 x 5 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

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Parameter

Min

Max

Units

Notes

VIN supply voltage

-0.3

7

V

See EN6347QI and TPS82085SIL datasheets

3.3VIN supply voltage

-0.1

3.630

V

Xilinx DS925 and TPS27082L datasheet

PS I/O supply voltage, VCCO_PSIO

-0.5

3.630

V

Xilinx document DS925

PS I/O input voltage

-0.5

VCCO_PSIO + 0.55

V

Xilinx document DS925

HP I/O bank supply voltage, VCCO

-0.5

2.0

V

Xilinx document DS925

HP I/O bank input voltage

-0.55

VCCO + 0.55

V

Xilinx document DS925

PS GTR reference clocks absolute input voltage

-0.5

1.1

V

Xilinx document DS925

PS GTR absolute input voltage

-0.5

1.1

V

Xilinx document DS925

Voltage on SC CPLD pins

-0.5

3.75

V

Lattice Semiconductor MachXO2 datasheet

Storage temperature

-40

+85

°C

See eMMC datasheet

Recommended Operating Conditions

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Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueParameterMinMaxUnitsNotesVIN supply voltage3.36VSee TPS82085S datasheet3.3VIN supply voltage3.33.465VSee LCMXO2-256HC, Xilinx DS925 datasheetPS I/O supply voltage, VCCO_PSIO1.7103.465VXilinx document DS925PS I/O input voltage–0.20VCCO_PSIO + 0.20VXilinx document DS925HP I/O banks supply voltage, VCCO0.9501.9VXilinx document DS925HP I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS925Voltage on SC CPLD pins-0.33.6VLattice Semiconductor MachXO2 datasheetOperating Temperature Range085°CXilinx document DS925, extended grade Zynq temperarure range

Physical Dimensions

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

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Parameter	Min	Max	Units	Reference Document
VIN¹⁾	3.135 OR 4.75	3.465 OR 5.25	V V
3.3VIN	3.135	3.465	V
VCCO_64	0.950	1.900	V	See FPGA datasheet.
VCCO_65	0.950	1.900	V	See FPGA datasheet.
VCCO_66	0.950	1.900	V	See FPGA datasheet.
PSBATT	1.200	1.500	V	See FPGA datasheet.

¹⁾ Higher values may possible. For more information consult schematic and according datasheets.

Physical Dimensions

Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.

PCB thickness: 1.66 mm (± 10 %).

Page properties

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guideline" .

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Currently Offered Variants

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

Set correct Link for Name encoding table

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Module size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm
PCB thickness: 1.6 mm
Highest part on PCB: approximately 5 mm. Please download the step model for exact numbers.

All dimensions are shown in millimeters.

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Currently Offered Variants

ASC
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Trenz shop TE0820 overview page*
English page	German page

*) Module article name encoding table: Zynq Ultrascale+ based modules (MPSoC, RFSoC)

Revision History

Hardware Revision History

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

links to download Carrier, e.g. TE0706 REV02:

TE0706-02 -> ENG Page: https://shop.trenz-electronic.de/enDownload/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD
Example:
Date Revision Changes Documentation Link
2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

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Revision History

Hardware Revision History

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Set correct links to download Carrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD

Example:

DateRevisionChangesDocumentation Link2020-11-25REV02

Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)



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Date	Revision	Changes	Documentation Link

2020-08-14

04

Fixed DDR4 connection (BG1), support B-die DDR4 Industrial grade chips
Added R93, changed value C62, change obsolete U28
Added R89 (10R)
Added additional caps 4.7uF to PS_AVTT/PS_AVCC (Xilinx doc UG583)
Changed R51 20k ->10K (PS_AVCC = 0.85V, Xilinx doc DS925 v1.17)
Fixed DDR4 connection (Alert)
Added 3.3V signal to CPLD
Added testpoints
LIB components update

PCN-20200616

TE0820-4

2019-01-02

03

Fixed VCU connection: add additional DCDC (0.9V)
LIB components update
Change package 1K resistors (0402 -> 0201)
Added LEDs (1x user LED, 1x LED for ERR_STATUS, 1xLED for ERR_OUT)
Change obsolete 2xSPI Flash (256MBit) -> 2xSPI Flash (512MBit)
Added additional DCDCs (PL_VCCINT_IO, PS_FP0V85)
Changed DCDC (U5) 6A (optional 4A)

PCN-20190110

TE0820-03

2017-08-17

02

Added MAC EEPROM (slave address)
LIB components update
Fixed SD Card connection
Fixed sense connection from DCDC
Made correct power connection for VCU (removed DCDC, added resistors and caps like as Xilinx recommended)
Added resistors for variants (ZU+ with/without VCU)
Added termination resistors (240R) to VRP pins fro all HP-banks

PCN-20171117

TE0820-02

2016-12-23

01

Prototype only

-

TE0820-01

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2022-06-22	05	Changed EOL ferrite beads L1..5,L7,L9..12. Changed EOL DCDC U5 (EN6363QI -> MPM3860GQW-Z). Changed EOL load switch U28 (TPS27082LDDCR -> MP5077GG-Z ). Added additional decoupling capacitors and changed caps 4.7uF to 10uF (AMD doc UG583 v1.23). Added pull-down and testpoint to TEN DDR4 signal. Changed EOL transistor T1 (AO7800 -> BSD840NH6327XTSA1). Added voltage detector U30 (BD39040MUF-CE2). Changed EOL eMMC U6 (MTFC4GACAJCN-4M -> SDINBDG4-8G-XI2). Changed EOL MEMS U14 (SiT8008AI-73-XXS-52.000000E -> SiT8008BI-73-XXS-52.000000E). Added signal PG_ALL (U30) to CPLD (pin5). Added option (depends assembly variants, for all assembly variants R128 set as populated, instead special inquiry) signal POR_B through R128, T2 to CPLD (pin27). Added option (depends assembly variants, for all assembly variants R95 set as DNP, instead special inquiry) signal EN1 through R95 to DCDC U5. Added option (depends assembly variants, for all assembly variants U29 and R129 set as populated, instead special inquiry) signal PHY_LED1 through level translator U29 to FPGA (U1.K7). Added resistors R130 & R131 (select Power-on delay override, for all assembly variants R130 set as DNP -> Standard PL Power-on delay time). Added diode D5. Added Power Diagram sheet. LIB components update.	TE0820-05
2020-08-14	04	Fixed DDR4 connection (BG1), support B-die DDR4 Industrial grade chips. Added R93, changed value C62, change obsolete U28. Added R89 (10R). Added additional caps 4.7uF to PS_AVTT/PS_AVCC (AMD doc UG583). Changed R51 20k ->10K (PS_AVCC = 0.85V, AMD doc DS925 v1.17). Fixed DDR4 connection (Alert). Added 3.3V signal to CPLD. Added testpoints. LIB components update.	TE0820-04
2019-01-02	03	Fixed VCU connection: add additional DCDC (0.9V). LIB components update. Change package 1K resistors (0402 -> 0201). Added LEDs (1x user LED, 1x LED for ERR_STATUS, 1xLED for ERR_OUT). Change obsolete 2xSPI Flash (256MBit) -> 2xSPI Flash (512MBit). Added additional DCDCs (PL_VCCINT_IO, PS_FP0V85). Changed DCDC (U5) 6A (optional 4A).	TE0820-03
2017-08-17	02	Added MAC EEPROM (slave address). LIB components update. Fixed SD Card connection. Fixed sense connection from DCDC. Made correct power connection for VCU (removed DCDC, added resistors and caps like as AMD recommended). Added resistors for variants (ZU+ with/without VCU). Added termination resistors (240R) to VRP pins fro all HP-banks.	TE0820-02
2016-12-23	01	Prototype	TE0820-01

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Date

Revision

Contributor

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

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Updated to new TRM style
Updated for REV05

2022-11-02

v.100

John Hartfiel

Corrected Key features

2021-12-17

v.99

Vadim Yunitski

Corrected 'Bank voltages' table

2021-07-14

v.98

John Hartfiel

bugfix boot mode

2021-07-05

v.97

John Hartfiel

published
style changes

2020-09-18

v.95

Pedram Babakhani

Update to REV04
Update the TRM format
Technical Information update

2020-03-16

v.87

John Hartfiel

Corrected PLL section
Corrected Designators USB, ETH PHY, CLK section

2020-02-03

v.85

Martin Rohrmüller

Corrected #MIOs for QSPI and USB in block diagram

2019-11-28

v.81

Martin Rohrmüller

typo and designator in section USB interface corrected

2019-10-30

v.80

John Hartfiel

typo correction

2019-09-17

v79

Martin Rohrmüller

Updated according to PCN-20190110: eMMC, QSPI-Flash

2019-07-17

v.78

Martin Rohrmüller

Corrected PJTAG Mio Pin29 in table 8

2019-05-08

v.77

John Hartfiel

Corrected EEPROM I2C Address
Correction USB PHY connection

2018-11-12

v.74

John Hartfiel

update boot section

2018-08-30

v.73

John Hartfiel

typo correction
update CPLD section
add LEDs to component list
add 3D picture of REV03 instead of REV01 picture

2018-07-12

v.69

Ali Naseri

Update PCB Rev03

2018-06-11

v.61

John Hartfiel

Rework chapter currently available products
add PJTAG note to MIOtable

2018-03-12

v.54

Correction Power Rail Section

2017-11-20

v.51

John Hartfiel

Correction Default MIO Configuration Table

2017-11-10

v.50

John Hartfiel

Replace B2B connector section

2017-10-18

v.49

John Hartfiel

add eMMC section

2017-09-25

v.48

John Hartfiel

Correction in the "Board to Board (B2B) I/Os" section
Update in the "Variants Currently In Production" section

2017-09-18

v.47

John Hartfiel

Update PS MIO table

2017-08-30

v.46

Jan Kumann

MGT lanes section added.

2017-08-24

v.36

John Hartfiel

Correction in the "Key Features" section.

2017-08-21

v.34

John Hartfiel

"Initial delivery state" section updated.

2017-08-21

v.33

Jan Kumann

HW revision 02 block diagram added.
Power distribution and power-on sequence diagram added.
System Controller CPLD and DDR4 SDRAM sections added.
TRM update to the template revision 1.6
Weight section removed.
Few minor corrections.

2017-08-18

v.7

John Hartfiel

Style changes
Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
Correction of MIO SD Pin-out, System Controller chapter
Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

Initial version

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Table 21: Document change history

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Trenz Electronic Documentation

Page History

Versions Compared

Old Version 100

New Version Current

Key

OverviewOverview

Key Features

Block Diagram

Main Components

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Test Points

Board to Board (B2B) I/Os

MGT Lanes

JTAG Interface

I2C Addresses

MIOs

Test Points

On-board Peripherals

System Controller CPLD

eMMC Memory

DDR4 Memory

Quad SPI Flash Memory

Gigabit Ethernet

USB2.0 Transceiver

On-board Peripherals

QSPI Flash

EEPROM

DDR4 SDRAM

GigaBit Ethernet

USB2.0 Transceiver

eMMC Memory

Oscillator

Programmable Clock Generator

CPLD

LED

Configuration and System Control Signals

EEPROM

Programmable Clock Generator

Clock Sources

LEDs

Power and Power-On Sequence

Power Rails

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:Power on-sequencePower distributionVoltage monitoring circuit Page propertieshiddentrueidComments NoteFor more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power Distribution Dependencies

Recommended Power up Sequencing

Power-On Sequence

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings *)

Power Rails

Board to Board Connectors

Recommended Operating Conditions

Technical Specifications

Recommended Operating Conditions

Physical Dimensions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

Absolute Maximum Ratings ^*)