Page History

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Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Image RemovedImage Added

Figure 1: TEB0729-02 03 block diagram.

Main Components

Figure 2: TEB0729-02 03 main components (picture shows PCB REV02).

5V barrel jack, J12
RJ-45 Gigabit Ethernet MegJack, J3
RJ-45 10/100-BaseT Ethernet MegJack, J4
RJ-45 10/100-BaseT Ethernet MegJack, J5
VG96 connector placeholder, J9
XMOD (TE0790) header, JB3
2-pin header for VBAT-IN supply-voltage, J2
2x6 pin header for setting VCCIO_33, J6
2x6 pin header for setting VCCIO_13, J7
MicroSD Card socket, J1
Red LED, D1
Push Button, S1
Micro USB2.0 B Receptacle (optional USB2.0 Type A socket)
VG96 connector placeholder, J8
B2B Connector, JB1
B2B Connector, JB2
4-bit DIP-switch, S2

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The TEB0729 Carrier Board's Board-to-Board Connectors (B2B) have the same pin-assignment as the mounted Zynq SoM due to its hermaphroditic structure. By this connectors, the MIO- and PL-IO-bank's pins and further interfaces of the Zynq SoM can be accessed. A large quantity of these I/O's are also usable as as LVDS-pairs. The connectors provide also VCCIO voltages to operate the I/O's properly.

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B2B Connector	Interfaces	Count of IO's	Notes
JB1	User IO	24 single ended	-
JB1	User IO	User IO	48 single ended or 24 differential	-
JB2	User IO	54 single ended	-User IO
	User IO	10 single ended or 5 differential	-
	I²C	2	-
	SD IO	7	-
	UART	2	-
	USB2.0	6	-
	2x 10/100-BaseT Ethernet	1412	-
	GbE MDI and SGMII	14	-
	JTAG	4	-

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On the VG96 connector J9 are signals assigned to control the SoM and the interfaces of the SoM's Zynq chip device and of its on-module peripherals:

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VG96 Connector	Control Signals and Interfaces	Count of IO's	Notes
J8	User IO	24 single ended	-
J8	User IO	User IO	48 single ended or 24 differential	-
J9	User IO	54 single ended	-
	User IO	User IO	10 single ended or 5 differential	-
	'NRST_IN' (pin J9-A29), 'NRSTRST_OUTSTATUS' , pins (pin J9-A29, J9-B30)	2SoM reset signals ¹⁾	These pins are dedicated to the specific Reset-functionality of the TE0729 SoM.
	'BOARD_STAT' , pins (pin J9-B32)	1	-
	'BOOT_MODE1' (pin J9-C31), 'BOOT_MODE2' , pins (pin J9-C31, J9-C32)	2	Binary bootmode code of SoM, also connected to DIP S2
	I²C, pins J9-A30, J9-A31	2	I²C1 interface of module
	GbE SGMII	4	SGMII interface of on-module GbE PHY

Table 3: General overview of PL I/O signals, SoM's interfaces and control signals connected to the VG96 connectors.

HW-modification Concerning Reset-Signals

¹⁾ The pins with the schematic net names 'NRST_IN' (JB2-89) and 'NRST_OUT' (JB2-91) are swapped as part of a HW-modification to rework the Reset-signals of the Carrier-Board in conjunction with the TE0729 SoM.

Refer to the SC CPLD documentation, section "Watchdog" to get further detailed information about the Reset-functionality of the Carrier Board and SoM before and after the HW-modification and the required SC CPLD firmware revision of the TE0729 SoM for each version of the SoM.

JTAG Interface

JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JB3. With the TE0790 XMOD USB2.0 to JTAG adapter, the Zynq device on the mounted SoM can be programed via USB2.JTAG access to the mounted SoM is provided through B2B connector JB2 and is also routed to the XMOD header JB3. With the TE0790 XMOD USB2.0 to JTAG adapter, the Zynq chip on the mounted SoM can be programed via USB2.0 interface.

JTAG Signal	B2B Connector Pin	XMOD Header JB3	Note
TCK	JB2-119	JB3-4	-
TDI	JB2-115	JB3-10	-
TDO	JB2-117	JB3-8	-
TMS	JB2-113	JB3-12	-
JTAGSEL	JB2-111	-	Select SoM's JTAG programming mode on DIP-switch S2-1.

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The SD IO interface of the SoM's Zynq chip device (MIO-bank) is routed to the on-board MicroSD Card socket J1. By this interface, the Zynq chip device can be booted from an inserted MicroSD Card:

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The TEB0729 Carrier Board is equipped with a Micro USB2.0 B (receptacle) socket J11 with board-revision TEB0729-0203B, USB2.0 Type A socket is fitted on board-revision TEB0729-0203A.

The differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the USB2.0 transceiver of the mounted SoM. The USB2.0 connector can be used for Device mode, OTG Mode or Host Modes. For USB Host mode, the Carrier Board is additionally equipped with a power distribution switch U3 to provide the USB2.0 interface with the USB supply voltage USB-VBUS with nominal value of 5V. OTG mode is not available with USB2.0 Type A socket.

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10/100-BaseT PHY Signal Schematic Name	B2B	Connected to	Notes
ETH1_RX_P	JB2-26	J4-3	-
ETH1_RX_N	JB2-28	J4-6	-
ETH1_TX_P	JB2-20	J4-1	-
ETH1_TX_N	JB2-22	J4-2	-
ETH1_CTREF	JB2-30	J4-4, J4-5	Centre Tap Reference point	ETH1_LED0	JB2-34	Yellow MegJack J4 LED	-
ETH1_LED1	JB2-32	Green MegJack J4 LED	-

ETH2_RX_P	JB2-8	J5-3	-
ETH2_RX_N	JB2-10	J5-6	-
ETH2_TX_P	JB2-2	J5-1	-
ETH2_TX_N	JB2-4	J5-2	-
ETH2_CTREF	JB2-18	J5-4, J5-5	Centre Tap Reference point	ETH2_LED0	JB2-16	Yellow MegJack J5 LED	-
ETH2_LED1	JB2-14	Green MegJack J5 LED	-

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JB3 pin	Signal Schematic Net Name	B2B	Note
C (pin 4)	TCK	JB2-119	-
D (pin 8)	TDO	JB2-117	-
F (pin 10)	TDI	JB2-115	-
H (pin 12)	TMS	JB2-113	-
A (pin 3)	USART0_TX	JB2-96	-
B (pin 7)	USART0_RX	JB2-94	-
E (pin 9)	BOARD_STAT	JB2-112	also connected to VG96 connector pin J9-B32
G (pin 11) ²⁾	NRST_IN ²⁾	JB2-89	also connected to VG96 connector pin J9-A29

Table 12: XMOD header signals and connections. ²⁾ Swapped at HW-Modification with signal 'NRST_OUT' in board-revision 2
Pin connected to push button S1 on XMOD FTDI JTAG Adapter

When using XMOD FTDI JTAG Adapter TE0790, the adapter-boardWhen using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the Carrier Board. Set the DIP-switch with the setting:

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Table 13: XMOD adapter board DIP-switch positions for voltage configuration.

On-board Peripherals

Note

Use Xilinx compatible TE0790 adapter board (designation TE0790-xx with out 'L') to program the Zynq device.

The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download.

On-board Peripherals

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Configuration EEPROM

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DIP-switches S2	Signal Schematic Net Name	Function	Note
S2-1	JTAGSEL	Select Zynq chip device or SC CPLD programming of mounted SoM: OFF: Zynq chip programming.device in JTAG chain ON: SC CPLD programmingin JTAG chain	Refer also to the TE0729 SC CPLD documentation for detailed information about JTAG update.
S2-2	BOOT_MODE1	Select first bit of boot mode code	Refer to TE0729 TRM and SC CPLD documentation for detailed information about boot modes.
S2-3	BOOT_MODE2	Select second bit boot mode code
S2-4	x	x	not used

Table 14: DIP-Switch S2 SoM configuration settings.

TE0729 Bootmodes

If TE0729 is mounted, following bootmodes can be configured by setting the DIP-switches S2-2 and S2-3:

Boot Mode	S2-2	S2-3
JTAG	ON	ON
SD	OFF	OFF
QSPI	ON	OFF

Table 15: Bootmode Boot Modes configuration via DIP-switch S2 .

The selected bootmode via DIP-switch S2 depends also on the current configured SC CPLD firmware on the mounted SoM and may vary.

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with default TE0729 CPLD Firmware

VCCIO Selection Jumper

The Carrier Board VCCIO for the PL IO-banks of the mounted SoM are selectable by the jumpers J6 and J7.

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VCCIO vs. Voltage Levels	VCCIO_13	VCCIO_33	Note
1.8V	J7:pins 1-2	J6: pins 1-2	-
2.5V	J7: pins 3-4	J6: pins 3-4	-
3.3V	J7: pins 5-6	J6: pins 5-6	-

Table 16: VCCIO jumper settings.

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The maximum power consumption of the Carrier Board depends mainly on the mounted SoM's FPGA design running on the Zynq chipdevice.

Xilinx provide a power estimator excel sheets to calculate power consumption. It's also possible to evaluate the power consumption of the developed design with Vivado. See also Trenz Electronic Wiki FAQ.

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Figure 3: Board power distribution diagram.

Power Rails

The voltage direction of the power rails is directed at on-board connectors' view:

Module Connector (B2B) Designator	VCC / VCCIO	Direction	Pins	Notes
JB1	VIN33	Out	Pin 1, 2, 3, 4, 5, 6	3.3V module supply voltage
	VCCIO_13	Out	Pin 101, 102	PL IO-bank VCCIO
	VCCIO_33	Out	Pin 29, 30	PL IO-bank VCCIO
	3.3V	In	Pin 65, 66	voltage output from module
JB2	1.8V	In	Pin 49	voltage output from module
	2.5V	In	Pin 13	voltage output from module
	USB-VBUS	Out	Pin 107	USB Host supply voltage
	VBAT_IN	Out	Pin 118	RTC buffer voltage

Table 19: Power pin description of B2B Module Connector.

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Jumper / Header Designator	VCC / VCCIO	Direction	Pins	Notes
J6	VCCIO_33	OutIn	Pin 2, 4, 6	-
	1.8V	InOut	5	-
	2.5V	InOut	3	-
	3.3V	InOut	1	-
J7	VCCIO_13	OutIn	Pin 2, 4, 6	-
	1.8V	InOut	5	-
	2.5V	InOUt	3	-
	3.3V	InOut	1	-

Table 20: Power Pin description of VCCIO selection jumper pin header.

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Main Power Jack and Pins Designator	VCC / VCCIO	Direction	Pins	Notes
J12	5VIN	In	-	-
J9	5VIN	In	Pin A1, A2	'5VIN' power supply to the Carrier Board as alternative to J12
J2	VBAT_IN	In	Pin 1	Attention: Pin 2 connected to ground. VBAT_IN voltage on this pin cause short-circuit.

Table 21: Main Power jack and pins description.

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	5VIN	In	1	-
J9	5VIN	In / Out	A1, A2	also usable as '5VIN' power supply to the Carrier Board as alternative to J12
J2	VBAT_IN	In	1	Attention: Pin 2 connected to ground. VBAT_IN voltage on this pin cause short-circuit.

Table 21: Main Power jack and pins description.

Peripheral Socket Designator	VCC / VCCIO	Direction	Pins	Notes
J10 / J11	USB-VBUS	In / Out	1	Direction depends on USB2.0 mode
J1	VIN33	Out	4	MikroSD Card socket VDD

Table 22: Power pin description of peripheral connector.

XMOD Header Designator	VCC / VCCIO	Direction	Pins	Notes
JB3	3.3V	-	5	not connected
JB3	VIO	Out	6	connected to VIN33

Table 23: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

The TE0729 module has two 120-pin double-row REF-189019-02 connectors on the bottom side which are compatible with Samtec BSE-060-01-L-D-A connectors. Mating connectors on the baseboard are REF-189019-01, which are compatible with Samtec BTE-060-01-L-D-A connectors.

Order number	REF Number	Samtec Number	Type	Mated Height	Data sheet	Comment
-	REF-189019-02	BTE-060-01-L-D-A-K-TR	Module connector	5 mm	http://suddendocs.samtec.com/catalog_english/bte.pdf	Standard connector used on module
26663	REF-189019-01	BSE-060-01-L-D-A-TR	Baseboard connector	5 mm	http://suddendocs.samtec.com/catalog_english/bse.pdf	Standard connector used on board

Table 24: B2B Connectors.

Connector Specifications	Value
Insulator material	Liquid crystal polymer
Stacking height	5 mm
Contact material	Phosphor-bronze
Plating	Au or Sn over 50 μ" (1.27 μm) Ni
Current rating	2 A per pin (1 pin powered per row)
Operating temperature range	-55 °C to +125 °C
Voltage rating	225 VAC with 5 mm stack height
Max cycles	100
RoHS compliant	Yes

Table 25: B2B Connector specifications.

Table 22: Power pin description of peripheral connector.

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Table 23: Power pin description of XMOD/JTAG Connector.

Board to Board Connectors

Include PageIN:Samtec LSHMIN:Samtec LSHM

Variants Currently In Production

Module Variant	Operating Temperature	USB Socket	Temperature Range
TEB0729-0203-A	-40°C to +125°C	USB2.0 Type A socket fitted	Industrial
TEB0729-0203-B	-40°C to +125°C	Micro USB2.0 B socket fitted	Industrial

Table 2426: Module Board variants.

Technical Specifications

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Parameter	Min	Max	Units	Reference Document
5VIN supply voltage	-0.3	7	V	MP5010A, EN6347QI data sheet
Storage temperature	-65	150	°C	-

Table 2527: Module absolute maximum ratings.

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Parameter	Min	Max	Units	Reference Document
5VIN supply voltage	4.75	5.25	V	USB2.0 specification concerning 'VBUS' voltage
Operating temperature	-40	125	°C	-

Table 2628: Module recommended operating conditions.

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Hardware Revision History

First -

Date

Revision

Notes

PCNSchematic Change Notes

Documentation Link

Note

-

01

First Production Release

-

TEB0729-01

-

02

Second Production Release

HW-Modification since 22.08.2017
Refer to Changes list in Schematic
for further details in changes to REV01

-

TEB0729-0102

-

02

Second Production Release

-

03

Rework Reset-Signals by Pin-Swap
Refer to Changes

Refer to Changes

list in Schematic

TEB0729-02

HW-Modification since 22.08.2017

for
further details in changes to REV02

-

TEB0729-03

Table 29Table 27: Module hardware revision history.

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Date

Revision

Contributors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Ali Naseri

update TRM to board revision 03

2017-10-27

v.14

Ali Naseri

initial document to board revision 02

Table 2830: Document change history.

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Trenz Electronic Documentation

Versions Compared

Old Version 13

New Version Current

Key

Block Diagram

Main Components

HW-modification Concerning Reset-Signals

JTAG Interface

JTAG Interface

On-board Peripherals

On-board Peripherals

Configuration EEPROM

TE0729 Bootmodes

VCCIO Selection Jumper

Power Rails

Board to Board Connectors

Board to Board Connectors

Variants Currently In Production

Technical Specifications

Hardware Revision History